DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 2, 23 and 28 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 2, 23 and 28 recite the limitation “wherein the SAM is disposed between the conductive feature and the barrier layer such that an entirety of the SAM directly contacts the conductive feature”. Looking to the specification of the instant application for support as how a SAM which is between two features can, in its entirety contact one of those features, the Examiner notices that this phrase is repeated in Para [0009} but there is not further information as to how the SAM is disposed between the conductive feature and the barrier layer such that an entirety of the SAM directly contacts the conductive feature. Further drawings Fig 10 and Fig 11 and Fig 16 of the elected species fail to show this feature.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 3, 4, 23 and 28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 2, 23 and 28 recite the limitation “wherein the SAM is disposed between the conductive feature and the barrier layer such that an entirety of the SAM directly contacts the conductive feature”. It is not clear how the SAM which is between two features can, contact one of those features in its entirety. For purposes of Examination, Examiner interprets “wherein the SAM is disposed between the conductive feature and the barrier layer such that an entirety of the SAM directly contacts the conductive feature” as “wherein the SAM is disposed between the conductive feature and the barrier layer such that one surface of the SAM directly contacts the conductive feature”.
Claims 3 and 4 are indefinite as they rely on the feature of Claim 2 described above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Claims 1-5 and 21-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kodera et al. (US 2006/0234499 A1, hereinafter Kodera ‘499).
With respect to Claim 1 Kodera ‘499 discloses a semiconductor structure (Fig 21A-21C and 22), comprising:
a semiconductor substrate (Para [0230] discloses structure on a substrate, hereinafter SUB);
a dielectric layer (302, Fig 22, Para [0230]) disposed over the semiconductor substrate (SUB);
a conductive feature (306, Fig 22, Para [0231]) embedded in the dielectric layer (302);
a barrier layer (305/307, Fig 22, Para [0230]) disposed between the conductive feature (306/307) and the dielectric layer (305)(Fig 22 discloses 305 between 306/307 and 302); and
a self-assembled monolayer (SAM) (336(333), Fig 22, Para [0069-0070] discloses plating inhibiting material layer as a self-assembled monolayer, and Para [0230] discloses 336 as the plating inhibiting material of Fig 22) disposed over (disclosed in Fig 22) the barrier layer (305/307), at least a portion of the SAM (336(333)) directly contacting (disclosed in Fig 22) the conductive feature (306),
wherein a bottom surface (bottom of 306) of the conductive feature (306) directly contacts (disclosed in Fig 22) the barrier layer (305/307).
With respect to Claim 2 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 1, and Kodera ‘499 further discloses wherein the SAM (336(333)) is disposed between (shown in Fig 22) the conductive feature (306) and the barrier layer (305/307) such that an entirety (Note Examiner’s above interpretation of “an entirety” as “one surface”) of the SAM (336(333)) directly contacts the conductive feature (306)(annotated Fig 22 of Kodera ‘499 discloses that 336(333) directly contacts one surface of 306).
With respect to Claim 3 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 2, and Kodera ‘499 further discloses wherein the SAM (336(333)) directly contacts a sidewall (sidewall of 306 as disclosed in annotated Fig 22 of Kodera ‘499) of the conductive feature (306) and a sidewall (sidewall of 305/307 as disclosed in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307).
With respect to Claim 4 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 2, wherein the conductive feature (306) directly contacts sidewalls (sidewalls of 305/307 as disclosed in Fig 22) and a bottom surface (bottom of 305/307 as disclosed in Fig 22) of the barrier layer (305/307).
With respect to Claim 5 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 1, and Kodera ‘499 further discloses (reference annotated Fig 22 of Kodera ‘499) wherein the SAM (336(333)) directly contacts a top portion (top portion of a sidewall of the barrier layer as shown in annotated Fig 22 of Kodera ‘499) of a sidewall (sidewall of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307), and wherein the conductive feature (306) directly contacts a bottom portion (bottom portion of the sidewall of the barrier layer as shown in annotated Fig 22 of Kodera ‘499) of the sidewall (sidewall of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307) below the top portion (top portion of a sidewall of the barrier layer as shown in annotated Fig 22 of Kodera ‘499).
With respect to Claim 21 Kodera ‘499 discloses a semiconductor structure (Fig 21A-21C and 22), comprising:
a substrate (Para [0230] discloses structure on a substrate, hereinafter SUB);
a dielectric layer (302, Fig 22, Para [0230]) disposed over the substrate (SUB) and including a recess (recess in 302 shown in Fig 22);
a conductive feature (306, Fig 22, Para [0231]) disposed in the recess (recess in 302 shown in Fig 22) of the dielectric layer (302);
a barrier layer (305/307, Fig 22, Para [0230]) disposed between (disclosed in Fig 22) the dielectric layer (302) and the conductive feature (306); and
a self-assembled monolayer (SAM) (336(333)), Fig 22, Para [0069-0070] discloses plating inhibiting material layer as a self-assembled monolayer, and Para [0230] discloses 336 as the plating inhibiting material of Fig 22) directly contacting a top portion (top portion of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307)(annotated Fig 22 of Kodera ‘499 discloses 336(333) directly contacts the top portion of 305/307),
wherein the conductive feature (306) directly contacts (disclosed in Fig 22) a bottom portion (bottom portion of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307) below the top portion (top portion of 305/307 as shown in annotated Fig 22 of Kodera ‘499).
With respect to Claim 22 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 21, and Kodera ‘499 discloses further wherein the SAM (336(333)) is disposed between (disclosed in Fig 22) the conductive feature (306) and the barrier layer (305/307).
With respect to Claim 23 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 21, and Kodera ‘499 discloses further wherein an entirety (Note Examiner’s above interpretation of “an entirety” as “one surface”) of the SAM (336(333)) directly contacts the conductive feature (306)(annotated Fig 22 of Kodera ‘499 discloses that 336(333) directly contacts one surface of 306).
With respect to Claim 24 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 21, and Kodera ‘499 discloses further wherein the SAM (336(333)) directly contacts a sidewall (sidewall of 306 as shown in annotated Fig 22 of Kodera ‘499) of the conductive feature (306) and a sidewall (sidewall of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307)(arrangement shown in annotated Fig 22 of Kodera ‘499).
With respect to Claim 25 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 21, and Kodera ‘499 discloses further wherein the conductive feature (306) directly contacts sidewalls (sidewalls of 305/307 as disclosed in Fig 22) of the barrier layer (305/307).
With respect to Claim 26 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 21, wherein the SAM (336(333)) directly contacts (disclosed in annotated Fig 22 of Kodera ‘499) a sidewall (sidewall of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307), and wherein the conductive feature (306) directly contacts a bottom portion (bottom portion of sidewall of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the sidewall (sidewall of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307) below the top portion (top portion of 305/307 as shown in annotated Fig 22 of Kodera ‘499).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 6 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Kodera ‘499 in view of Valckx et al. (US 2015/0171241 A1, hereinafter Valckx ‘241), in view of the following arguments.
With respect to Claim 6 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 1, but Kodera ‘499 fails to explicitly disclose wherein an interface between a top portion of the conductive feature and a top portion of the barrier layer has an inwardly sloped profile.
Nevertheless, in a related endeavor (Fig. 1-4B of Valckx ‘241), Valckx ‘241 teaches wherein an interface (interface between top portion of 71/72 and top portion of 6a as shown in annotated Fig 4 of Valckx ‘241) between a top portion (top portion of 71/72 as shown in annotated Fig 4 of Valckx ‘241) of the conductive feature (71/72, Fig 4 of Valckx ‘241, Para [0072]) and a top portion (top portion of 6a as shown in annotated Fig 4 of Valckx ‘241) of the barrier layer (6a, Fig 2 of Valckx, Para [0054] discloses 6a as comprising Ti) has an inwardly sloped profile (inward sloped profile of 71/72 is disclosed in Fig 4 of Valckx ‘241 and Para [0091-0096] disclose the SAM (a alkyl phosphonic acid compound) is used to manipulate the contact angle of the surface impacting the angle of the conductive feature 72).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Valckx ‘241’s teaching wherein an interface between a top portion of the conductive feature and a top portion of the barrier layer has an inwardly sloped profile into Kodera ‘499’s semiconductor structure. Kodera ‘499 discloses a conductive semiconductor structure with a SAM structure to manipulate the formation of the conductive feature (Para [0231]). Valckx ‘241 teaches a conductive semiconductor structure and teaches details about how to use the SAM to affect the interface surface energy to manipulate the formation of the conductive structure (Para [0091-0096]). Valckx ‘241 teaches, disclosed in Fig 4B, that this can create a conductive structure with an inward slope at the interface of a barrier layer. Therefore the ordinary artisan would have been motivated to modify Kodera ‘499 in the manner set forth above, at least, because Valckx ‘241 teaches a sloped profile for the conductive features that one of ordinary skill in the art would recognize aids in direct bonding and Valckx ‘241 further teaches in Para [0033] that this shape can create an electrical connection that has less resistance.
As incorporated, the teaching of the teaching of Valckx ‘241 of using the SAM to manipulate the surface energy of the interface between a barrier and the contact feature to create an inward slope of the conductive feature would be used in Kodera ‘499 so that the interface of barrier layer (560 of Kodera ‘499) and the conductive feature (306 of Kodera ’499) would have an inwardly sloped profile.
With respect to Claim 27 Kodera ‘499 discloses all limitations of the semiconductor structure of claim 21, but Kodera ‘499 fails to explicitly disclose wherein an interface between a top portion of the conductive feature and a top portion of the barrier layer has an inwardly sloped profile.
Nevertheless, in a related endeavor (Fig. 1-4B of Valckx ‘241), Valckx ‘241 teaches wherein an interface (interface between top portion of 71/72 and top portion of 6a as shown in annotated Fig 4 of Valckx ‘241) between a top portion (top portion of 72 as shown in annotated Fig 4 of Valckx ‘241) of the conductive feature (71/72, Fig 4 of Valckx ‘241, Para [0072]) and a top portion (top portion of 6a as shown in annotated Fig 4 of Valckx ‘241) of the barrier layer (6a, Fig 2 of Valckx, Para [0054] discloses 6a as comprising Ti) has an inwardly sloped profile (inward sloped profile of 7172 is disclosed in Fig 4 of Valckx ‘241 and Para [0091-0096] disclose the SAM (a alkyl phosphonic acid compound) is used to manipulate the contact angle of the surface impacting the angle of the conductive feature 72).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Valckx ‘241’s teaching wherein an interface between a top portion of the conductive feature and a top portion of the barrier layer has an inwardly sloped profile into Kodera ‘499’s semiconductor structure. Kodera ‘499 discloses a conductive semiconductor structure with a SAM structure to manipulate the formation of the conductive feature (Para [0231]). Valckx ‘241 teaches a conductive semiconductor structure and teaches details about how to use the SAM to affect the interface surface energy to manipulate the formation of the conductive structure (Para [0091-0096]). Valckx ‘241 teaches, disclosed in Fig 4B, that this can create a conductive structure with an inward slope at the interface of a barrier layer. Therefore the ordinary artisan would have been motivated to modify Kodera ‘499 in the manner set forth above, at least, because Valckx ‘241 teaches a sloped profile for the conductive features that one of ordinary skill in the art would recognize aids in direct bonding and Valckx ‘241 further teaches in Para [0033] that this shape can create an electrical connection that has less resistance.
As incorporated, the teaching of the teaching of Valckx ‘241 of using the SAM to manipulate the surface energy of the interface between a barrier and the contact feature to create an inward slope of the conductive feature would be used in Kodera ‘499 so that the interface of barrier layer (560 of Kodera ‘499) and the conductive feature (306 of Kodera ’499) would have an inwardly sloped profile.
Claims 8, 11-12 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Kodera ‘499 in view of Kim et al. (US 2017/0358553 A1, hereinafter Kim ‘553), in view of the following arguments.
With respect to Claim 8 Kodera ‘499 discloses a semiconductor structure (Fig 21A-21C and 22), comprising:
a semiconductor substrate (Para [0230] discloses structure on a substrate, hereinafter SUB);
a dielectric layer (302, Fig 22, Para [0230]) disposed over the semiconductor substrate (SUB), the dielectric layer (302) having a recess (recess in 302 shown in Fig 22);
a conductive feature (306, Fig 22, Para [0231]) disposed in the recess (recess in 302 shown in Fig 22); and
a barrier layer (305/307, Fig 22, Para [0230]) disposed between the dielectric layer (302) and the conductive feature (306)(arrangement disclosed in Fig 22), and a bottom portion of the sidewall (bottom of sidewall of 305/307) of the barrier layer (305/307) has a vertical profile (annotated Fig 22 of Kodera ‘499 discloses the bottom portion of the sidewall of 305/307 having a vertical profile); and
a self-assembled monolayer (SAM) (336(333), Fig 22, Para [0069-0070] discloses plating inhibiting material layer as a self-assembled monolayer, and Para [0230] discloses 336 as the plating inhibiting material of Fig 22) directly contacting (disclosed in Fig 22) the barrier layer (305/307),wherein the conductive feature (306) directly contacts (disclosed in Fig 22) a bottom portion (bottom portion of 305/307) of the barrier layer (305/307).
But Kodera ‘499 fails to disclose wherein a top portion of a sidewall of the barrier layer has a sloped profile.
Nevertheless, in a related endeavor (Fig 2A-2E of Kim ‘553), Kim ‘553 teaches a top portion of a sidewall of the barrier layer (115’-1, Fig 2A of Kim ‘553, Para [0022]) has a sloped profile. (Fig 2A of Kim ‘553 discloses a sloped sidewall conductive connection structure with a sloped barrier layer 115’-1 sidewall).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Kim ‘553’s teaching of a sloped connection structure and a sloped sidewall of the barrier layer in the connection structure into Kodera ‘499’s device. Kodera ‘499 discloses a conductive semiconductor structure and is open to the shape of the via (Para [0280]). Kim ‘553 teaches a conductive connection structure and shows shapes for that conductive via to aid in direct bonding. The ordinary artisan, therefore would have been motivated to modify Kodera ‘499 in the manner set forth above, at least, because as one of ordinary skill in the art would recognize, vias have sloped sides as part of the formation process and as Kim ‘553 teaches in Para [0005] teaches these pads shapes can help to create effective direct bond pads.
As incorporated, the teaching of using a sloped sidewall on a via as taught by Kim ‘553 would be used in the recess area (308 of Kodera ‘499) so that the a top portion of a sidewall of the barrier layer (top portion of the sidewall of 305/307) would have a sloped profile.
With respect to Claim 11 Kodera ‘499 as modified by Kim ‘553 discloses all the semiconductor structure of claim 8, and Kodera ‘499 discloses further wherein the SAM (336(333)) is disposed between (disclosed in Fig 22) the barrier layer (305/307) and the conductive feature (306).
With respect to Claim 12 Kodera ‘499 as modified by Kim ‘553 discloses all the semiconductor structure of claim 8, and Kodera ‘499 further discloses (reference annotated Fig 22 of Kodera ‘499) wherein the SAM (336(333)) directly contacts the top portion (top portion of a sidewall of the barrier layer as shown in annotated Fig 22 of Kodera ‘499) of the sidewall (sidewall of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307), and wherein the conductive feature (306) directly contacts a bottom portion (bottom portion of the sidewall of the barrier layer as shown in annotated Fig 22 of Kodera ‘499) of the sidewall (sidewall of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307) below the top portion (top portion of a sidewall of the barrier layer as shown in annotated Fig 22 of Kodera ‘499).
With respect to Claim 28 Kodera ‘499 as modified by Kim ‘553 discloses all limitations of the semiconductor structure of claim 8, and Kodera ‘499 further discloses wherein an entirety (Note Examiner’s above interpretation of “an entirety” as “one surface”) of the SAM (336(333)) directly contacts the conductive feature (306)(annotated Fig 22 of Kodera ‘499 discloses that 336(333) directly contacts one surface of 306).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kodera ‘499 in view of Kim ‘553 in further view of Fountain Jr. et al. (US 2019/0096842 A1, hereinafter Fountain, Jr ‘842), in view of the following arguments.
With respect to Claim 9 Kodera ‘499 as modified by Kim ‘553 discloses all the limitations of the semiconductor structure of claim 8, But Kodera ‘499 as modified by Kim ‘553 fails to explicitly teach wherein the sloped profile is an inwardly sloped profile.
Nevertheless in a related endeavor (Fig 2 of Fountain, Jr ‘842), Fountain, Jr ‘842 teaches wherein the sloped profile is an inwardly sloped profile. (Para [0049] and Fig 2 of Fountain Jr ‘842 discloses sides of vias and sides of barrier layer 206 have a curvature).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Fountain, Jr ‘842’s teaching of a sloped connection structure and a sloped sidewall of the barrier layer in the connection structure into Kodera ‘499 as modified by Kim ‘553’s device. Kodera ‘499 as modified by Kim ‘553 discloses a conductive semiconductor structure with a sloped shape. Fountain, Jr ‘842 teaches that rounding resulting in an inward slope of the top of a barrier layer can occur as a result of the process. The ordinary artisan, therefore would have been motivated to modify Kodera ‘499 as modified by Kim ‘553 in the manner set forth above, at least, because as one of ordinary skill in the art would recognize the well-known feature that vias have inward sloped sides as part of the formation process and as Fountain Jr ‘842 teaches in Para [0049] and Fountain Jr ‘842 further teaches these pads shapes can be used to create direct bond connections.
As incorporated, the teaching Fountain Jr ‘842 of the sloped profile is an inwardly sloped profile would be used as the profile of the top of the barrier layer (305/307) of Kodera ‘499 as modified by Kim ‘553.
Claims 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Kodera ‘499 in view of Kim ‘553 and in further view of Valckx ‘241, in view of the following arguments.
With respect to Claim 29 Kodera ‘499 as modified by Kim ‘553 discloses all limitations of the semiconductor structure of claim 8, but Kodera ‘499 as modified by Kim ‘553 fails to explicitly disclose wherein an interface between a top portion of the conductive feature and a top portion of the barrier layer has an inwardly sloped profile.
Nevertheless, in a related endeavor (Fig. 1-4B of Valckx ‘241), Valckx ‘241 teaches wherein an interface (interface between top portion of 71/72 and top portion of 6a as shown in annotated Fig 4 of Valckx ‘241) between a top portion (top portion of 72 as shown in annotated Fig 4 of Valckx ‘241) of the conductive feature (71/72, Fig 4 of Valckx ‘241, Para [0072]) and a top portion (top portion of 6a as shown in annotated Fig 4 of Valckx ‘241) of the barrier layer (6a, Fig 2 of Valckx, Para [0054] discloses 6a as comprising Ti) has an inwardly sloped profile (inward sloped profile of 71/72 is disclosed in Fig 4 of Valckx ‘241 and Para [0091-0096] disclose the SAM (a alkyl phosphonic acid compound) is used to manipulate the contact angle of the surface impacting the angle of the conductive feature 72).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Valckx ‘241’s teaching wherein an interface between a top portion of the conductive feature and a top portion of the barrier layer has an inwardly sloped profile into Kodera ‘499 as modified by Kim ‘553’s semiconductor structure. Kodera ‘499 as modified by Kim ‘553 discloses a conductive semiconductor structure with a SAM structure to manipulate the formation of the conductive feature (Para [0231]). Valckx ‘241 teaches a conductive semiconductor structure and teaches details about how to use the SAM to affect the interface surface energy to manipulate the formation of the conductive structure (Para [0091-0096]). Valckx ‘241 teaches, disclosed in Fig 4B, that this can create a conductive structure with an inward slope at the interface of a barrier layer. Therefore the ordinary artisan would have been motivated to modify Kodera ‘499 in the manner set forth above, at least, because Valckx ‘241 teaches a sloped profile for the conductive features that one of ordinary skill in the art would recognize aids in direct bonding and Valckx ‘241 further teaches in Para [0033] that this shape can create an electrical connection that has less resistance.
As incorporated, the teaching of the teaching of Valckx ‘241 of using the SAM to manipulate the surface energy of the interface between a barrier and the contact feature to create an inward slope of the conductive feature would be used in Kodera ‘499 so that the interface of barrier layer (560 of Kodera ‘499 as modified by Kim ‘553) and the conductive feature (306 of Kodera ’499 as modified by Kim ‘553) would have an inwardly sloped profile.
With respect to Claim 30 Kodera ‘499 as modified by Kim ‘553 and further modified by Valckx ‘241 discloses all limitations of the semiconductor structure of claim 29, and Kodera ‘499 discloses further wherein the interface (interface of 306 and 305/307 as shown in annotated Fig 22 of Kodera ‘499) is between a top portion (top portion of 306 as shown in annotated Fig 22 of Kodera ‘499) of the conductive feature (306) and the top portion (top portion of 305/307 as shown in annotated Fig 22 of Kodera ‘499) of the barrier layer (305/307)(annotated Fig 22 of Kodera ‘499 discloses interface between top portion of 306 and top portion of 305/307).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898