DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are being examined in this office action.
Prior rejection of Claims 12-17 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments to claim 12.
Prior additional rejection of Claims 15 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments to claim 15.
Drawings
Prior objection to drawing is withdrawn in view of corrected Fig. 4B.
Claim Objections
Claim 18 is objected to because of the following informalities: Claim 18 recites in line 3, “…wherein -- the the active region -- includes...” Examiner believes that the limitation should recite, “…wherein -- the active region -- includes...”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation “the active region” in lines 4 and 5. There is insufficient antecedent basis for this limitation in the claim. The limitation will be treated as “an active region” in line 4.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rastogi et al. (US 2018/0102364 A1).
Re Claim 1, Rastogi teaches a semiconductor device, comprising:
a substrate (110, Figs. 1-3, para [0022]);
an active region on the substrate (marked “active region” in annotated Fig. 1 below), wherein the active region includes:
a plurality of source/drain structures (S/D regions 170, Figs. 1-3, paras [0033] and [0037], note that the source/drains 170 connects all the three fins FA1 in the y-axis, see Fig. 3 for a cross-sectional view);
a first transistor (marked “1st transistor” in annotated Fig. 1 below) having a gate structure (gate line “GL”, Figs. 1-2, para [0033]), a source conductor (marked “source contact CP1” in annotated Fig. 1 below, para [0037]), and a drain conductor (marked “drain contact CP1” in annotated Fig. 1 below, para [0037]) disposed on the active region, wherein
the drain conductor (“drain contact CP1”) and the source conductor (“source contact CP1”) are disposed on opposite sides of the gate structure (see annotated Fig. 1 below);
the source conductor (“source contact CP1”) is shorter than the drain conductor (“drain contact CP1”, see annotated Fig. 1 below);
a first edge of the source conductor is aligned with a first edge of the drain conductor (bottom edges of “source contact CP1” and “drain contact CP1” are aligned, see annotated Fig. 1 below), and a second edge of the source conductor (top edge of “source contact CP1”) is misaligned (see annotated Fig. 1 below) with a second edge of the drain conductor (top edge of “drain contact CP1”); and
a portion of a top surface of one of the plurality of source/drain structures is exposed (marked “exposed S/D” in annotated Fig. 1 below) from the second edge of the source conductor (top edge of “source contact CP1”).
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Re Claim 2, Rastogi teaches the semiconductor device of Claim 1, wherein the first edge of the source conductor (bottom edge of “source contact CP1”) is located outside the active region (“active region”, see annotated Fig. 1 above), and wherein the second edge of the source conductor (top edge of “source contact CP1”) is located within the active region from a top view (“active region”, see annotated Fig. 1 above).
Re Claim 3, Rastogi teaches the semiconductor device of Claim 1, wherein the first edge of the source conductor (bottom edge of “source contact CP1”) and the first edge of the drain conductor (bottom edge of “drain contact CP1”) are located outside the active region (bottom edges of “source contact CP1” and “drain contact CP1” are outside the “active region”, see annotated Fig. 1 above).
Re Claim 4, Rastogi teaches the semiconductor device of Claim 2, wherein the first edge of the source conductor (bottom edge of “source contact CP1”) is located outside the active region (“active region”, see annotated Fig. 1 above), and wherein the second edge of the source conductor (top edge of “source contact CP1”) is located between a first boundary and a second boundary of the active region (upper and lower boundary of “active region”, see annotated Fig. 1 above).
Re Claim 5, Rastogi teaches the semiconductor device of Claim 3, wherein the second edge of the source conductor (top edge of “source contact CP1”) is located between a first boundary and a second boundary of the active region (upper and lower boundary of “active region”, see annotated Fig. 1 above).
Re Claim 6, Rastogi teaches the semiconductor device of Claim 3, wherein the first edge of the source conductor (bottom edge of “source contact CP1”) is spaced apart from a first boundary of the active region (lower boundary of “active region”, see annotated Fig. 1 above) by a first distance (marked “distance d1” in annotated Fig. 1 above), and wherein the first edge of the drain conductor (bottom edge of “drain contact CP1”) is spaced apart from the first boundary of the active region (lower boundary of “active region”, see annotated Fig. 1 above) by a second distance identical to the first distance (“distance d1”, see annotated Fig. 1 above).
Re Claim 7, Rastogi teaches the semiconductor device of Claim 1, further comprising:
a second transistor (marked “2nd transistor” in annotated Fig. 1 above) having a gate structure (gate line “GL”, Figs. 1-2, para [0033]), a drain conductor (marked “2nd drain contact CP1” in annotated Fig. 1 above, para [0037]), and a source conductor (marked “2nd source contact CP1” in annotated Fig. 1 above, para [0037]) disposed on the active region (“active region”, see annotated Fig. 1 above), wherein
the gate structure of the first transistor (“GL” of 1st transistor) is electrically connected to the drain conductor of the first transistor (“drain contact CP1”, see annotated Fig. 1 above); and
the gate structure of the first transistor (“GL” of 1st transistor) is electrically connected to the gate structure of the second transistor (“GL” of 2nd transistor, see annotated Fig. 1 above).
Re Claim 8, Rastogi teaches the semiconductor device of Claim 7, wherein the source conductor of the second transistor (“2nd source contact CP1”) is shorter (see annotated Fig.1 above) than the drain conductor of the second transistor (“2nd drain contact CP1”).
Re Claim 9, Rastogi teaches the semiconductor device of Claim 8, wherein a first edge of the source conductor of the second transistor is aligned with a first edge of the drain conductor of the second transistor (bottom edges of “2nd source contact CP1” and “2nd drain contact CP1” are aligned, see annotated Fig. 1 above), and a second edge of the source conductor of the second transistor (top edge of “2nd source contact CP1”) is misaligned (see annotated Fig. 1 above) with a second edge of the drain conductor of the second transistor (top edge of “2nd drain contact CP1”).
Re Claim 10, Rastogi teaches the semiconductor device of Claim 8, wherein a first edge of the source conductor of the second transistor is aligned with a first edge of the drain conductor of the second transistor (bottom edges of “2nd source contact CP1” and “2nd drain contact CP1” are aligned, see annotated Fig. 1 above), and wherein the first edge of the source conductor of the second transistor and the first edge of the drain conductor of the second transistor are located outside the active region (both the bottom edges of the “2nd source contact CP1” and “2nd drain contact CP1” are outside the “active region”, see annotated Fig. 1 above).
Re Claim 18, Rastogi teaches A method of manufacturing a semiconductor device, comprising:
forming a substrate (110, Figs. 1-3, para [0022]);
forming an active region on the substrate (marked “active region” in annotated Fig. 1 above), wherein the active region includes a plurality of source/drain structures (S/D regions 170, Figs. 1-3, paras [0033] and [0037], note that the source/drains 170 connects all the three fins FA1 in the y-axis, see Fig. 3 for a cross-sectional view);
forming a first transistor having (marked “1st transistor” in annotated Fig. 1 above) a gate structure (gate line “GL”, Figs. 1-2, para [0033]), a source conductor (marked “source contact CP1” in annotated Fig. 1 above, para [0037]), and a drain conductor (marked “drain contact CP1” in annotated Fig. 1 above, para [0037]) on the active region, wherein
the drain conductor (“drain contact CP1”) and the source conductor (“source contact CP1”) are disposed on opposite sides of the gate structure (see annotated Fig. 1 above);
the source conductor (“source contact CP1”) is shorter than the drain conductor (“drain contact CP1”, see annotated Fig. 1 above);
a first edge of the source conductor is aligned with a first edge of the drain conductor (bottom edges of “source contact CP1” and “drain contact CP1” are aligned, see annotated Fig. 1 above), and a second edge of the source conductor (top edge of “source contact CP1”) is misaligned (see annotated Fig. 1 above) with a second edge of the drain conductor (top edge of “drain contact CP1”); and
a portion of a top surface of one of the plurality of source/drain structures is exposed (marked “exposed S/D” in annotated Fig. 1 above) from the second edge of the source conductor (top edge of “source contact CP1”).
Re Claim 19, Rastogi teaches the method of Claim 18 wherein the first edge of the source conductor (bottom edge of “source contact CP1”) is located outside the active region (“active region”, see annotated Fig. 1 above), and wherein the second edge of the source conductor (top edge of “source contact CP1”) is located within the active region from a top view (“active region”, see annotated Fig. 1 above).
Re Claim 20, Rastogi teaches the method of Claim 18, wherein the first edge of the source conductor (bottom edge of “source contact CP1”) and the first edge of the drain conductor (bottom edge of “drain contact CP1”) are located outside the active region (bottom edges of “source contact CP1” and “drain contact CP1” are outside the “active region”, see annotated Fig. 1 above).
Claims 12-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rastogi et al. (US 2018/0102364 A1).
Re Claim 12, Rastogi teaches a semiconductor device, comprising:
a substrate (110, Figs. 1-3, para [0022]);
a plurality of source/drain structures (S/D regions 170, Figs. 1-3, paras [0033] and [0037], note that the source/drains 170 connects all the three fins FA1 in the y-axis, see Fig. 3 for a cross-sectional view) on the substrate; and
a first transistor (marked “1st transistor” in annotated Fig. 1-v2 below) having a gate structure (gate line “GL”, Figs. 1-2, para [0033]), a drain conductor (marked “drain contact CP1” in annotated Fig. 1-v2 below, para [0037]), and a source conductor (marked “source contact CP1” in annotated Fig. 1-v2 below, para [0037]) disposed on the substrate, wherein
the drain conductor (“drain contact CP1”) and the source conductor (“source contact CP1”) are disposed on opposite sides of the gate structure (see annotated Fig. 1-v2 below);
the source conductor (“source contact CP1”) is isolated from at least one of the source/drain structures (marked “isolated S/D” in annotated Fig. 1-v2 below);
a first edge of the source conductor is aligned with a first edge of the drain conductor (bottom edges of “source contact CP1” and “drain contact CP1” are aligned, see annotated Fig. 1-v2 below), and a second edge of the source conductor (top edge of “source contact CP1”) is misaligned (see annotated Fig. 1-v2 below) with a second edge of the drain conductor (top edge of “drain contact CP1”); and
a first portion of a top surface of one of the plurality of source/drain structures is exposed (marked “exposed S/D” in annotated Fig. 1-v2 below) from the second edge of the source conductor (top edge of “source contact CP1”), and the source conductor contacts a second portion of the top surface of the plurality of source/drain structures (see Fig. 1-v2 below, note that the S/D 170 connects all the three FA1 fins as shown in Fig. 3, and the “source contact CP1” does not contact the portion of S/D structure on the top FA1 fin but contacts the S/D of the other two FA1 fins, see Fig. 1-v2 below).
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Re Claim 13, Rastogi teaches the semiconductor device of Claim 12, wherein the source conductor (“source contact CP1”) is shorter than the drain conductor (“drain contact CP1”) in the top view perspective (see annotated Fig. 1-v2 above).
Re Claim 14, Rastogi teaches the semiconductor device of Claim 12, wherein the first edge of the source conductor (bottom edge of “source contact CP1”) is located outside an active region (“active region”, see annotated Fig. 1-v2 above), and wherein the second edge of the source conductor (top edge of “source contact CP1”) is located within the active region from a top view (“active region”, see annotated Fig. 1-v2 above).
Re Claim 15, Rastogi teaches the semiconductor device of Claim 12, wherein the first edge of the source conductor (bottom edge of “source contact CP1”) and the first edge of the drain conductor (bottom edge of “drain contact CP1”) are located outside an active region (bottom edges of “source contact CP1” and “drain contact CP1” are outside the “active region”, see annotated Fig. 1-v2 above).
Re Claim 16, Rastogi teaches the semiconductor device of Claim 12, wherein the first transistor further comprising:
a second gate structure (2nd gate line “GL” within “1st transistor”, see Fig. 1-v2 above) disposed adjacent to the drain conductor (“drain contact CP1”);
a second source conductor (marked “2nd source contact CP1” in annotated Fig. 1-v2 above) disposed adjacent to second gate structure (2nd gate line “GL”), wherein
the second gate structure (2nd gate line “GL”) is electrically connected (see Fig. 1) to the gate structure (gate line “GL”);
the second source conductor (“2nd source contact CP1”) is electrically connected to the source conductor (source contact CP1”); and
the second source conductor (“2nd source contact CP1”) is shorter than the drain conductor (“drain contact CP1”) in the top view perspective (see annotated Fig. 1-v2 above).
Re Claim 17, Rastogi teaches the semiconductor device of Claim 16, wherein the second source conductor (“2nd source contact CP1”) is isolated from at least one of the source/drain structures (marked “isolated S/D” in annotated Fig. 1-v2 above).
Rejection 2
Claims 1 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rastogi et al. (US 2018/0102364 A1).
Re Claim 1 (Rejection 2), Rastogi teaches a semiconductor device, comprising:
a substrate (110, Figs. 1-3, para [0022]);
an active region on the substrate (marked “active region” in annotated Fig. 1-v3 below), wherein the active region includes:
a plurality of source/drain structures (S/D regions 170, Figs. 1-3, paras [0033] and [0037], note that the source/drains 170 connects all the three fins FA1 in the y-axis, see Fig. 3 for a cross-sectional view);
a first transistor (marked “1st transistor” in annotated Fig. 1-v3 below) having a gate structure (gate line “GL”, Figs. 1-2, para [0033]), a source conductor (marked “source contact CP1” in annotated Fig. 1-v3 below, para [0037]), and a drain conductor (marked “drain contact CP1” in annotated Fig. 1-v3 below, para [0037]) disposed on the active region, wherein
the drain conductor (“drain contact CP1”) and the source conductor (“source contact CP1”) are disposed on opposite sides of the gate structure (see annotated Fig. 1-v3 below);
the source conductor (“source contact CP1”) is shorter than the drain conductor (“drain contact CP1”, see annotated Fig. 1-v3 below);
a first edge of the source conductor is aligned with a first edge of the drain conductor (bottom edges of “source contact CP1” and “drain contact CP1” are aligned, see annotated Fig. 1-v3 below), and a second edge of the source conductor (top edge of “source contact CP1”) is misaligned (see annotated Fig. 1-v3 below) with a second edge of the drain conductor (top edge of “drain contact CP1”); and
a portion of a top surface of one of the plurality of source/drain structures is exposed (marked “exposed S/D” in annotated Fig. 1-v3 below) from the second edge of the source conductor (top edge of “source contact CP1”).
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Re Claim 11, Rastogi teaches the semiconductor device of Claim 1 (Rejection-2), wherein the first transistor further comprising:
a second gate structure (2nd gate line “GL” within “1st transistor”) disposed adjacent to the drain conductor (“drain contact CP1”);
a second source conductor (marked “2nd source contact CP1” in annotated Fig. 1-v3 above) disposed adjacent to second gate structure (2nd gate line “GL”), wherein
the second gate structure (2nd gate line “GL”) is electrically connected (see Fig. 1) to the gate structure (gate line “GL”);
the second source conductor (“2nd source contact CP1”) is electrically connected to the source conductor (source contact CP1”); and
the second source conductor (“2nd source contact CP1”) is shorter than the drain conductor (“drain contact CP1”, see annotated Fig. 1-v3 above).
Response to Arguments
Applicant’s arguments with respect to claims 1, 12 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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