DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 4, 5, 11-20 have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2, 4, 5, 11-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites at the 3rd from last line of the claim recites “the interface is between the first well region (121 of fig. 4 of the instant application) and the second well region (122) is positioned between the first isolation component (111) and the first doping region (151)” therefore the interface is under the gate structure. The newly added limitation recites “a third isolation component (113) formed in the first well region (121) and the second well region (122) and across an interface between the first well region and the second well region (122)” is not supported in the specification as filed because the interface cannot be both the interface under the gate and the interface under isolation 113.
Claim 20 lacks support within the elected embodiment of fig. 4 since the fourth isolation component 114 is not formed in the first well region and the second well region but rather the first well region and the substrate 100.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US PGPub 2014/0320174; hereinafter “Lu”) in view of Tseng et al. (US 10,157,981; hereinafter “Tseng”) and Hsu et al. (US PGPub 2014/0091389; hereinafter “Hsu”).
Re claim 1: Lu teaches (e.g. LDMOS of fig. 5) a semiconductor device, comprising: a substrate (P-substrate 201; e.g. paragraph 21) having a first conductivity type (P-substrate 201; e.g. paragraph 21); a first well region (P-type well region 203, 202; e.g. paragraph 21), formed in the substrate (201) and having the first conductivity type (P-type well region 203, 202; e.g. paragraph 21); a second well region (N-type field region 206; e.g. paragraph 21), formed in the substrate (201) and having a second conductivity type (N-type field region 206; e.g. paragraph 21); a first isolation component (STI regions 229; e.g. paragraph 21) formed in the second well region (206), a second isolation component (STI regions 230; e.g. paragraph 21) formed in the first well region (203, 202); a gate structure (gate electrodes 231, 241; e.g. paragraph 21) formed on the substrate (201), wherein the gate structure (231, 241) spans over the first well region (203) and the second well region (206); and a first doping region (N+ source region 205; e.g. paragraph 21) formed in the first well region (203) and a second doping region (N+ drain region 207; e.g. paragraph 21) formed in the second well region (206), wherein the first doping region (205) and the second doping region (207) have the second conductivity type (N-type) and are disposed at opposite sides of the gate structure (231, 241), wherein the interface (interface between 203 and 206 that is under 231, 241; hereinafter “IF1”) between the first well region (203) and the second well region (206) is positioned between the first isolation component (229) and the first doping region (205), and the interface (IF) is separated from the bottom surface the isolation component (bottom surface of 229) by a lateral distance.
Lu is silent as to explicitly teaching a third isolation component formed in the first well region and the second well region and across an interface between the first well region and the second well region; and a third well region formed in the second well region, wherein the third well region has the first conductivity type and is in contact with a bottom surface of the first isolation component.
Tseng teaches (e.g. fig. 1H) a third isolation component (148D) formed in the first well region (122, 126 which is equivalent to 202, 203 of Lu) and the second well region (140 which is equivalent to 206 of Lu) and across an interface (S4) between the first well region (126) and the second well region (14q0).
Hsu teaches (e.g. LDMOS of fig. 3) a third well region (P-type implant region 140 and is complementary to conductivity type of the source/drain regions; e.g. paragraphs 18 and 19) formed in the second well region (N-type well 140; e.g. paragraph 15), wherein the third well region (P-type implant region 140; e.g. paragraphs 18 and 19) has the first conductivity type (P-type) and is in contact with a bottom surface of the first isolation component (insulating region 108; e.g. paragraph 18).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the third isolation between the drain contact and the substrate contact as taught by Tseng and to use the counter doped third well region under the isolation component as taught by Hsu in the device of Lu in order to have the predictable result of improving device performance by preventing the possibility of device breakdown between 162 and 166, and in order to have the predictable result of providing a reduced surface field effect and improving the breakdown voltage of the LDMOS device of Lu (see paragraph 19 of Hsu), respectively.
Re claim 2: Lu in view of Hsu teaches the semiconductor device as claimed in claim 1, wherein the third well region (140 of Hsu) directly covers a portion of the bottom surface or the entire bottom surface of the first isolation component (229 of Lu/108 of Hsu).
Re claim 11: Lu in view of Hsu teaches the semiconductor device as claimed in claim 1, wherein the third well region (140 of Hsu) is a strip-shaped region (140 of Hsu has a strip shape), and the first doping region (112 of Hsu), the third well (140 of Hsu) and the second doping region (104 of Hsu) extend in the same direction (each of the claimed element extends in the left-right direction of fig. 3) as viewed from a top of the substrate (102 of Hsu).
Re claim 12: Lu in view of Hsu teaches the semiconductor device as claimed in claim 1, wherein the third well region (140 of Hsu) is electrically connected (there is an electrical connection between 140 and 112 through 104) to the first well region (112 of Hsu).
Re claim 13: Lu in view of Hsu teaches the semiconductor device as claimed in claim 1, wherein the third well region (140 of Hsu) is electrically insulated (the diode formed between 104 and 140 and between 104 and 112 provides some electrical isolation) from the first well region (112 of Hsu).
Re claim 14: Lu in view of Hsu teaches the semiconductor device as claimed in claim 1, further comprising: a conductive portion (241) over the substrate (201) and positioned at one side of a gate electrode (left of 231) of the gate structure (231, 241), wherein the conductive portion (241) is electrically insulated (232 electrically isolated side surface of 231 and 241) from the gate electrode (231), and wherein the conductive portion (241) is correspondingly positioned above (141 is above 229) the first isolation component (229).
Re claim 15: Lu in view of Hsu teaches the semiconductor device as claimed in claim 14, wherein the conductive portion (241) is correspondingly positioned above (GE is above 116) the third well region (140 of Hsu).
Re claim 16: Lu in view of Hsu teaches the semiconductor device as claimed in claim 14, wherein the conductive portion (241) is grounded (when the LDMOS is turned off, 241 would have a ground potential and when the LDMOS is turned on 241 would have a positive potential).
Re claim 17: Lu teaches the semiconductor device as claimed in claim 1, further comprising: a third doping region (P+ contact 204, 209; e.g. paragraph 21 of Lu) formed in the first well region (203, 202), wherein the third doping region (204, 209) has the first conductivity type(P-type), wherein the first doping region (205) is disposed between the third doping region (204, 209) and the first isolation component (229), and a doping concentration of the third well region (p-region 203) is less than a doping concentration of the third doping region (P+ region 204, 209).
Re claim 18: Lu in view of Hsu teaches the semiconductor device as claimed in claim 17, wherein as viewed from a top of the substrate (201), the third doping region (P+ region 204, 209) is a circular doping region (209 surrounds DVNWELL 210) and closely surrounds the first doping region (205), the gate structure (231), the second well region (206), the third well region (140 of Hsu) and the second doping region (207).
Re claim 19: Lu in view of Hsu teaches the semiconductor device as claimed in claim 17, wherein the second isolation component (230) is positioned between the third doping region (204) and the first doping region (205), wherein a bottom surface of the third well region (140 of Hsu) is closer (since 229 and 230 have the same depth, 140 of Hsu would be closer to the bottom surface of the substrate than the bottom surface of 230 is to the bottom surface of the substrate) to a bottom surface of the substrate (201) than a bottom surface of the second isolation component (230).
Re claim 20: Lu in view of Tseng and Hsu teaches the semiconductor device as claimed in claim 19, wherein the second doping region (207 of Lu/162 of Tseng) is positioned between the first isolation component (229 of Lu/148C of Tseng) and the third isolation component (148D of Tseng); and the semiconductor device further comprises: a fourth isolation component (228) formed in the first well region (203,202) and the second well region (202), wherein the fourth isolation component (228) and the third isolation component (148D of Tseng) are disposed at the opposite sides of the gate structure (231), and the third doping region (204, 209) is positioned between the fourth isolation component (228) and the second isolation component (230), wherein the bottom surface of the third well region (140 of Hsu) is closer to the bottom surface of the substrate (201) than a bottom surface of the third isolation component (227) and a bottom surface of the fourth isolation component (228).
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Tseng and Hsu as applied to claim 1 above, and further in view of Disney et al. (US PGPub 2016/0315188; hereinafter “Disney”).
Re claim 4: Lu in view of Tseng and Hsu teaches substantially the entire device as claimed in claim 1, except explicitly teaching the semiconductor device, wherein a doping concentration of the third well region (140 of Hsu) is greater than a doping concentration of the second well region (206 of Lu).
Disney teaches (e.g. LDMOS of fig. 1b) the semiconductor device as claimed in claim 1, wherein a doping concentration of the third well region (116 which is P-type has a net charge of 1.5x1012cm-2; therefore has a density greater than the concentration of n-type drift 112; e.g. paragraph 28) is greater than a doping concentration of the second well region (n-type drift 112 has a concentration of 1x1015cm-3; e.g. paragraph 22).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the dopant concentration as taught by Disney in the device of Lu in view of Tseng and Hsu in order to have the predictable result of using known dopant concentrations within an LDMOS which achieves the best off-state and on-state performance (see paragraph 28 of Disney).
Re claim 5: Lu in view of Tseng and Hsu teaches substantially the entire device as claimed in claim 1, except explicitly teaching the semiconductor device, wherein a doping concentration of the third well region is less than a doping concentration of the first well region.
Disney teaches the semiconductor device as claimed in claim 1, wherein a doping concentration of the third well region (as explained above in claim 4, 116 has a concentration slightly above 112, approximately 1.5x1015cm-3; e.g. paragraph 28) is less than a doping concentration of the first well region (p-type well region 114 is doped to 1x1016cm-3; e.g. paragraph 25).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the dopant concentration as taught by Disney in the device of Lu in view of Tseng and Hsu in order to have the predictable result of using known dopant concentrations within an LDMOS which achieves the best off-state and on-state performance (see paragraph 28 of Disney).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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