Prosecution Insights
Last updated: October 01, 2026
Application No. 18/314,446

Complementary Field Effect Transistors and Methods of Forming the Same

Non-Final OA §103
Filed
May 09, 2023
Priority
Jan 27, 2023 — provisional 63/481,826
Examiner
TURNER, BRIAN
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
3 (Non-Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
641 granted / 769 resolved
+15.4% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
51 currently pending
Career history
820
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
61.8%
+21.8% vs TC avg
§102
21.7%
-18.3% vs TC avg
§112
12.8%
-27.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 769 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/26/2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 21-23, 25 and 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (PG Pub. No. US 2021/0265348 A1) in view of Lee et al. (PG Pub. No. US 2023/0120551 A1). Regarding claim 21, Xie teaches a method comprising: growing a first epitaxial source/drain region (¶ 0049: 302) adjacent to a first semiconductor nanostructure (¶ 0035, fig. 3: 302 grown adjacent to stack of lower nanostructures 108); forming a first source/drain contact (¶ 0079: 902/silicide) adjacent to the first epitaxial source/drain region (fig. 9: 902 formed adjacent to 302), the first source/drain contact having a smaller resistance than the first epitaxial source/drain region (¶¶ 0051, 0079: 902 comprises metal material, 302 comprises semiconductor material); forming an isolation dielectric (¶ 0059: 402) on the first source/drain contact and on the first epitaxial source/drain region (fig. 9: 402 at least indirectly arranged on 902 and 302); growing a second epitaxial source/drain region (¶ 0060: 502) on the isolation dielectric and adjacent to a second semiconductor nanostructure (¶¶ 0035, fig. 9: 502 formed at least indirectly on 402 and adjacent to upper stack of nanostructures 108), the second semiconductor nanostructure stacked over the first semiconductor nanostructure (fig. 9 among others: upper nanostructures 108 stacks over lower nanostructures 108), the isolation dielectric separating the second epitaxial source/drain region from the first epitaxial source/drain region (fig. 9: 402 separates 502 from 302); and forming a second source/drain contact (¶ 0080: 904 and/or non-illustrated silicide) adjacent to the second epitaxial source/drain region (fig. 9: 904 formed adjacent to 502), the second source/drain contact having a smaller resistance than the second epitaxial source/drain region (¶¶ 0061, 0079: 904 comprises metal material, 502 comprises semiconductor material), the isolation dielectric separating the second source/drain contact from the first source/drain contact (fig. 5: 402 separates 904 from 902). Xie does not teach the step of forming an isolation dielectric on the first source/drain contact and on the first epitaxial source/drain region is performed after forming the first source/drain contact. Lee teaches a method of forming a semiconductor device (figs. 10-12 among others) including forming an isolation dielectric (¶ 0102: 130) on a first source/drain contact and on a first epitaxial source/drain region (fig. 12: 130 formed on a first source/drain contact BC1 and a first epitaxial source/drain region BSD1/BSD2) after forming the first source/drain contact (¶¶ 0100-0102: 130 formed on insulating layer 102, which surrounds BSD1/BSD2; since 130 is formed on 120 and BSD1/2, the broadest reasonable interpretation of “after forming the first source/drain contact” is met). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Xie with the sequence of Lee, as a means to provide the isolation dielectric fully surrounding the second source/drain region, avoiding formation of undesired features such as voids. Regarding claim 22, Xie in view of Lee teaches the method of claim 21, wherein the first source/drain contact and the second source/drain contact are formed of the same contact material (Xie, ¶¶ 0055, 0064: in at least one embodiment, 304 and 504 formed of same material). Regarding claim 23, Xie in view of Lee teaches the method of claim 21, wherein the first source/drain contact and the second source/drain contact are formed of different contact materials (Xie, ¶¶ 0055, 0064: in at least one embodiment, 304 and 504 formed of different materials). Regarding claim 25, Xie in view of Lee teaches the method of claim 21, wherein the first epitaxial source/drain region and the first source/drain contact are each formed in a recess adjacent to the first semiconductor nanostructure (Xie, ¶ 0079 & fig. 9: 302, 304 formed in recess adjacent to lower nanostructure stack 108), and the first source/drain contact occupies more of the recess than the first epitaxial source/drain region (Xie, fig. 5: 304 occupies more of the recess than 302). Regarding claim 27, Xie in view of Lee teaches the method of claim 21, wherein forming the first source/drain contact comprises: depositing a conductive material (Xie, ¶ 0055: in at least one embodiment, 304 formed with conductive dielectric material); and recessing the conductive material using an etch-back process (Xie, ¶ 0056 & figs. 3-4: recessed below a below spacer 202 by a wet or dry etch-back process). Regarding claim 28, Xie in view of Lee teaches the method of claim 21, wherein forming the isolation dielectric comprises: depositing a dielectric material (Xie, ¶ 0055: 304); and recessing the dielectric material using an isotropic etch (Xie, ¶ 0056: 304 recessed with wet etch, which is inherently isotropic). Regarding claim 29, Xie in view of Lee teaches the method of claim 21, wherein growing the first epitaxial source/drain region comprises stopping growth of the first epitaxial source/drain region before the first epitaxial source/drain region merges with adjoining epitaxial growth (Xie, fig. 3: 302 growth stopped before vertically or laterally merging). Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Lee as applied to claim 21 above, and further in view of Chu et al. (PG Pub. No. US 2022/0069135 A1). Regarding claim 24, Xie in view of Lee teaches the method of claim 21, comprising a first epitaxial source/drain region (Xie, 302). Xie in view of Lee does not teach wherein the first epitaxial source/drain region has a thickness in a range of 1 nm to 5 nm measured in a direction extending between a sidewall of the first semiconductor nanostructure and a sidewall of the first source/drain contact. Chu teaches a method including forming a first epitaxial source/drain region (¶ 0028: 236, similar to 302 of Xie), wherein the first epitaxial source/drain region has a thickness in a range of 4 nm to 6 nm measured in a direction extending between a sidewall of a first semiconductor nanostructure and a sidewall of a first source/drain contact (¶ 0028, fig. 13A: 236 has a thickness of 4 nm to 6 nm along the x direction, between nanostructures 208 and source/drain contacts 238). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first epitaxial source/drain region of Xie in view of Lee with the thickness of Chu, as a means to reduce resistance (Chu, ¶¶ 0004, 0030). Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed epitaxial source/drain thickness range of 4 nm to 6 nm overlaps the range disclosed by Chu. Claims 26 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Lee as applied to claim 21 above, and further in view of Ma. Regarding claim 26, Xie in view of Lee teaches the method of claim 21, comprising growing a first epitaxial source/drain region (Xie, 302). Xie in view of Lee does not teach the method further comprising: forming a stop material prior to growing the first epitaxial source/drain region, wherein the first epitaxial source/drain region and the first source/drain contact are each formed on the stop material. Ma teaches a method including: forming a stop material (¶¶ 0020, 0039: undoped layer 232) in a recess (fig. 4); and growing a first epitaxial source/drain region (234) on the stop material (fig. 4). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Xie in view of Lee with the stop material of Ma, as a means to provide lattice mismatch with source/drain materials (Ma, ¶ 0048), improving performance of the source/drain regions (Ma, ¶ 0012). Furthermore, the combination of Xie and Ma would implicitly include forming the first source/drain contact of Xie at least indirectly on the stop material of Ma. Allowable Subject Matter Claims 15-20 and 30-34 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitations stating: “the first source/drain contact and the first epitaxial source/drain region each directly contact a top surface of the stop material” as recited in claim 15, and “the isolation dielectric directly contacts and extends continually across an upper surface of the first epitaxial source/drain region and a lower surface of the second epitaxial source/drain region” as recited in claim 30. Xie et al. (US 2021/0265348 A1) teaches a method including forming a first source/drain contact (902) and a first epitaxial source/drain region (302), but does not teach forming a stop material in a nanostructure recess. Xie et al. (US 2023/0065715 A1, hereinafter referenced as ‘Xi-715’) teaches a method including forming a nanostructure recess (fig. 6) and forming a source/drain contact (1710) and a first epitaxial source/drain region (710) each directly contacting a top surface of a stop material (fig. 17: 1710 and 710 each directly contact a top surface of layer 210). However, Xie-715 fails to teach forming the stop material in the nanostructure recess. Therefore, neither Xie not X-715, alone or in combination, teach the features of claim 15. Furthermore, Frougier (US 10,192,867 B1) teaches an isolation dielectric (810) a first source/drain (S1/D1) and a second source/drain (S2/D2), but fails to teach the isolation dielectric directly contacts and extends continually across upper surfaces of the first and second epitaxial source/drain regions. Frougier et al. (US 2020/0287046 A1) teaches an isolation dielectric (402) directly contacting and extending continually across an upper surface of a first source/drain region (304), but fails to teach the isolation dielectric directly contacting and extending continually across a lower surface of a second source/drain region, as required by claim 30. Claims 16-20 and 31-34 depend on claims 15 and 30, and are allowed for implicitly including the allowable subject matter above. In light of these limitations in the claims (see the Applicant’s fig. 17A & ¶ 0067), the previously applied references do not anticipate or obviate the claimed methods as in the context of the claims. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant’s arguments, see pages 7-8, filed 5/26/2026, with respect to the 35 USC § 102 and 35 USC § 103 rejections of claims 21-29 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN TURNER/Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Show 1 earlier event
Jun 26, 2023
Response after Non-Final Action
Oct 16, 2025
Non-Final Rejection mailed — §103
Feb 16, 2026
Response Filed
Mar 25, 2026
Final Rejection mailed — §103
May 26, 2026
Response after Non-Final Action
Jun 09, 2026
Request for Continued Examination
Jun 11, 2026
Response after Non-Final Action
Sep 10, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751271
GATE ALL AROUND BACKSIDE POWER RAIL WITH DIFFUSION BREAK
3y 7m to grant Granted Sep 29, 2026
Patent 12745453
INTEGRATED CIRCUIT DRIVER DEVICE, LAYOUT, AND METHOD
3y 4m to grant Granted Sep 22, 2026
Patent 12727226
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
3y 6m to grant Granted Sep 01, 2026
Patent 12721105
INTEGRATED DICING DIE BONDING SHEET AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
3y 2m to grant Granted Aug 25, 2026
Patent 12713784
DISPLAY DEVICE
4y 8m to grant Granted Aug 18, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
88%
With Interview (+4.4%)
2y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 769 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month