DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments with respect to claims 19, 26 and 33 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The portion of the amended portion teaches in another figure of Teo. See explanation as in the rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-25 are rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. (US PGpub: 2020/0303417 A1), herein after Teo, in view of Teo.
Regarding claim 19, Teo teaches, in FIG. 10A-10E and FIG. 1A-1C, a method for forming a semiconductor memory structure, comprising:
forming a gate structure (1070B) over a substrate (1080B);
forming a ferroelectric layer (1050B) over the gate structure, and coupled to sidewalls of the gate structure (FIG. 1A where extended portion of ferroelectric layer coupled to gate structure 171A. FIG. 1B or 10B shows the portion as marked);
forming an intervening structure (1040B) over the ferroelectric layer.
forming a channel layer (1020B) over the intervening structure; and
forming a source structure (1010B) and a drain structure (1030B) over the channel layer.
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Teo does not explicitly teach wherein a thickness of the intervening structure is less than a thickness of the ferroelectric layer and less than a thickness of the channel layer.
However, it is possible to optimize the thickness of intervening structure to make it thinner than thickness of ferroelectric layer and channel layer as in paragraph [0111] of Teo. Too high of 1040B damages 2D material. So, the goal is to reduce or keep the intervening structure 1040B height lower. Also, in Paragraph [0067], ferroelectric thickness can range from 5nm-50nm
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Teo’s method for forming a semiconductor memory structure with other teaching from Teo in order to reduce high damages 2D material, to protect 2D material from wrinkling and to reduce contact resistance so that it improve performance of the device.
Regarding claim 20, Teo teaches the method of claim 19, wherein the intervening structure comprises a single- layered structure, a bi-layered structure or a tri-layered structure (see FIG. 10B). Also, evidenced in US 20210066627 A1 Cheng et al. in Paragraph [0020].
Regarding claim 21, Teo teaches the method of claim 19, wherein the intervening structure comprises a first layer (top portion of 1040B) in contact with the channel layer and a second layer (Bottom portion of 1040B) in contact with the ferroelectric layer (1050B).
Regarding claim 22, Teo teaches the method of claim 21, wherein the first layer is in contact with the second layer (top portion of 1040B and Bottom portion of 1040B).
Regarding claim 23, Teo teaches the method of claim 22, wherein the first layer and the second layer comprise different materials. Also, evidenced in US 2021/0066627 A1 Cheng et al. in Paragraph [0020].
Regarding claim 24, Teo teaches the method of claim 21, wherein the first layer and the second layer are separated from each other by a third layer. Also, evidenced in US 20210066627 A1 Cheng et al. in Paragraph [0020].
Regarding claim 25, Teo teaches the method of claim 24, wherein the first layer and the third layer comprise different materials. Also, evidenced in US 20210066627 A1 Cheng et al. in Paragraph [0020].
Claims 26-38 are rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. (US PGpub: 2020/0303417 A1), herein after Teo, in view of Teo and in further view of SHARMA et al. (US PGpub: 2020/0006572 A1), herein after SHARMA.
Regarding claim 26, Teo teaches, in FIG. 10A-10E and FIG. 1A-1C, a method for forming a semiconductor memory structure, comprising:
forming a gate structure (1070B) over a substrate (1080B);
forming a ferroelectric layer (1050B) over the gate structure, and coupled to sidewalls of the gate structure (FIG. 1A where extended portion of ferroelectric layer coupled to gate structure 171A. FIG. 1B or 10B shows the portion as marked);
forming an intervening structure (1040B) over the ferroelectric layer.
forming a channel layer (1020B) over the intervening structure;
and
forming a source structure (1010B) and a drain structure (1030B) over the channel layer.
Teo does not explicitly teach forming a dielectric layer over the channel layer;
forming openings in the dielectric layer, wherein portions of the channel layer are exposed through the openings and herein a thickness of the intervening structure is less than a thickness of the ferroelectric layer and less than a thickness of the channel layer.
However, it is possible to optimize the thickness of intervening structure to make it thinner than thickness of ferroelectric layer and channel layer as in paragraph [0111] of Teo. Too high of 1040B damages 2D material. So, the goal is to reduce or keep the intervening structure 1040B height lower. Also, in Paragraph [0067], ferroelectric thickness can range from 5nm-50nm
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Teo’s method for forming a semiconductor memory structure with other teaching from Teo in order to reduce high damages 2D material, to protect 2D material from wrinkling and to reduce contact resistance so that it improve performance of the device.
Teo does not explicitly teach forming a dielectric layer over the channel layer;
forming openings in the dielectric layer, wherein portions of the channel layer are exposed through the openings.
However, SHARMA teaches forming a dielectric layer (364) over the channel layer (356); forming openings (FIG. 3B) in the dielectric layer (364), wherein portions of the channel layer are exposed through the openings (FIG. 3B).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Teo’s modifies method for forming a semiconductor memory structure with other teaching from SHARMA in order to improve performance of such transistors by improving channel mobility for BEOL-compatible channel materials.
Regarding claim 27, Teo teaches the method of claim 26, wherein a bottom of the source structure and a bottom of the drain structure are in contact with the channel layer (see FIG. 10B).
Regarding claim 28, Teo teaches the method of claim 26, wherein the intervening structure comprises a first layer in contact with the channel layer and a second layer in contact with the ferroelectric layer. (see FIG. 10B)
Regarding claim 29, Teo teaches the method of claim 28, wherein the first layer is in contact with the second layer, and the first layer and the second layer comprise different materials. Also, evidenced in US 2021/0066627 A1 Cheng et al. in Paragraph [0020].
Regarding claim 30, Teo teaches the method of claim 28, wherein the first layer and the second layer are separated from each other by a third layer. Also, evidenced in US 2021/0066627 A1 Cheng et al. in Paragraph [0020].
Regarding claim 31, Teo teaches the method of claim 30, wherein the first layer and the third layer comprise different materials. Also, evidenced in US 2021/0066627 A1 Cheng et al. in Paragraph [0020].
Regarding claim 32, Teo teaches the method of claim 31, wherein the first layer and the second layer comprise a same material. Also, evidenced in US 2021/0066627 A1 Cheng et al. in Paragraph [0020]. This is just choice of different materials.
Regarding claim 33, Teo teaches, in FIG. 10A-10E and FIG. 1A-1C, a method for forming a semiconductor memory structure, comprising:
forming a gate structure (1070B) over a substrate (1080B);
forming a ferroelectric layer (1050B) over the gate structure, and coupled to sidewalls of the gate structure (FIG. 1A where extended portion of ferroelectric layer coupled to gate structure 171A. FIG. 1B or 10B shows the portion as marked);
forming an intervening structure (1040B) over the ferroelectric layer.
forming a channel layer (1020B) over the intervening structure;
and
forming a source structure (1010B) and a drain structure (1030B).
forming openings in the dielectric layer, wherein portions of the intervening structure are exposed through the openings; and forming a source structure and a drain structure in the openings, wherein a thickness of the intervening structure is less than a thickness of the ferroelectric layer and less than a thickness of the channel layer.
Teo does not explicitly teach forming openings in the dielectric layer, wherein portions of the intervening structure are exposed through the openings; and forming a source structure and a drain structure in the openings, wherein a thickness of the intervening structure is less than a thickness of the ferroelectric layer and less than a thickness of the channel layer.
However, it is possible to optimize the thickness of intervening structure to make it thinner than thickness of ferroelectric layer and channel layer as in paragraph [0111] of Teo. Too high of 1040B damages 2D material. So, the goal is to reduce or keep the intervening structure 1040B height lower. Also, in Paragraph [0067], ferroelectric thickness can range from 5nm-50nm
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Teo’s method for forming a semiconductor memory structure with other teaching from Teo in order to reduce high damages 2D material, to protect 2D material from wrinkling and to reduce contact resistance so that it improve performance of the device.
Teo does not explicitly teach forming a dielectric layer over the channel layer;
forming openings in the dielectric layer, wherein portions of the channel layer are exposed through the openings.
However, SHARMA teaches forming a dielectric layer (364) over the channel layer (356); forming openings (FIG. 3B) in the dielectric layer (364), wherein portions of the channel layer are exposed through the openings (FIG. 3B).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Teo’s modifies method for forming a semiconductor memory structure with other teaching from SHARMA in order to improve performance of such transistors by improving channel mobility for BEOL-compatible channel materials.
Regarding claim 34, Teo teaches the method of claim 33, wherein a bottom of the source structure and a bottom of the drain structure are in contact with the intervening structure (see FIG. 10B).
Regarding claim 35, Teo teaches the method of claim 33, wherein a sidewall of the source structure and a sidewall of the drain structure are in contact with the channel layer (see FIG. 10B).
Regarding claim 36, Teo teaches the method of claim 33, wherein the intervening structure comprises a first layer in contact with the channel layer and a second layer in contact with the ferroelectric layer (FIG. 10B considering dielectric layer is multi layered). Also, evidenced in US 2021/0066627 A1 Cheng et al. in Paragraph [0020]. This is just choice of different materials.
Regarding claim 37, Teo teaches the method of claim 36, wherein the first layer is in contact with the second layer, and the first layer and the second layer comprise different materials (FIG. 10B considering dielectric layer is multi layered). Also, evidenced in US 2021/0066627 A1 Cheng et al. in Paragraph [0020]. This is just choice of different materials.
Regarding claim 38, Teo teaches the method of claim 36, wherein the first layer and the second layer are separated from each other by a third layer, and the first layer and the third layer comprise different materials (FIG. 10B considering dielectric layer is multi layered). Also, evidenced in US 2021/0066627 A1 Cheng et al. in Paragraph [0020]. This is just choice of different materials.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897