Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of group I in the reply filed on 08/04/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek et al., U.S. Patent 10,403,562.
Baek et al. shows the invention as claimed including a method of making a semiconductor device, comprising:
Providing an electrical component 125;
Depositing a first encapsulant 131 over the electrical component to form a module (see, for example, figs. 11a-11b);
Disposing the module adjacent to a semiconductor die 120 (see fig. 11C); and
Depositing a second encapsulant 132 over the semiconductor die and module (see, for example, figs. 9-12 and col. 8-line 31 to col. 15-line 36).
With respect to dependent claim 12, note that Baek et al. discloses forming the module to include a redistribution layer 142 (see col. 8-line 36 to col. 9-line 13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al., U.S. Patent 10,403,562 in view of Admitted prior art.
Baek et al. shows the invention as claimed including a method of making a semiconductor device, comprising:
Providing a plurality of electrical components 125;
Depositing a first encapsulant 131 over the plurality of electric components to form a module (see, for example, figs. 11a-11b);
Disposing the module adjacent to a semiconductor die 120 (see fig. 11C);
Depositing a second encapsulant 132 over the semiconductor die and module (also see fig. 11C); and
Forming a build-up interconnect structure (for example, 190 or 192) (see figs. 11a-11c and col. 14-line 29 to col. 15-line 36).
Baek et al. does not expressly disclose forming the build-up interconnect over the second encapsulant, module and semiconductor die. Admitted prior art discloses flipping the device followed by forming build up metallization over a semiconductor die and encapsulant (see figs. 1B-1D and paragraphs 0006-0007 of specification). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Baek et al. so as to form the buildup interconnect over the second encapsulant module and semiconductor die because forming the build-up interconnect over the semiconductor die and encapsulant is shown to be part of the conventional packaging process in order to complete the packaging devices.
With respect to dependent claims 2 and 8, note that providing the plurality of electrical components includes: providing a passive component (125A-125E). Regarding providing a second semiconductor die, the examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have an additional semiconductor die depending upon the particular application of the packaged device. Furthermore, duplication of parts has been held to have been obvious.
Concerning dependent claim 6, note that Baek et al. discloses forming the module to include a redistribution layer 142 (see col. 8-line 36 to col. 9-line 13).
Claim(s) 4 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al., U.S. Patent 10,403,562 in view of Admitted prior art as applied to claims 1, 2, 6, and 8 above, and further in view of Shin et al., US 2012/0038034.
Baek et al. and Admitted prior art are applied as above but do not expressly disclose disposing the electrical components over a leadframe prior to depositing the first encapsulant. Shin et al. discloses disposing the electrical components over a leadframe prior to depositing an encapsulant (see abstract that discloses forming encapsulant over a leadframe and semiconductor die). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the process of Baek et al. modified by the admitted prior art so as to comprise disposing the electrical components over a leadframe prior to depositing the first encapsulant because in such a way both the leadframe and semiconductor die can be adequately protected.
Claim(s) 5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al., U.S. Patent 10,403,562 in view of Admitted prior art as applied to claims 1-2, 6, and 8 above, and further in view of Davis et al., U.S. Patent 11,749,534.
Baek et al. and the Admitted prior art are applied as above but do not expressly disclose forming the build-up interconnect structure to include a wettable flank. Davis et al. discloses a packaging structure including a wettable flank (see col. 7-lines 17-36). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the process of Bask et al. modified by the Admitted prior art so as to include forming a build-up interconnect including a wettable flank because, for example, this allows for more visibility for quality checking during optical inspection.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al., U.S. Patent 10,403,562.
Baek et al. is applied as above but does not expressly disclose forming a build-up interconnect over the module prior to depositing the second encapsulant. However, Baek et al. discloses the formation of a build up interconnect 190 after depositing the second encapsulant 132 (see, for example, figs. 11a-11c and their description). However, a prima facie case of obviousness exists because the particular order of processing steps is obvious absent a showing of new or unexpected results (see In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946)). Moreover, an upside down apparatus or device has been held to have been obvious.
Allowable Subject Matter
Claims 3 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, either singly or in combination, particularly Baek et al., U.S. Patent 10,403,562, fails to anticipate or render obvious, the following limitations in combination with the claimed limitations: forming a first conductive layer; forming a second conductive layer; and disposing the electrical components over the first conductive layer and second conductive layer prior to depositing the first encapsulant, as required by dependent claims 3 and 9.
Claims 26-37 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, particularly Baek et al., U.S. Patent 10,403,562, fails to anticipate or render obvious, the following limitations in combination with the claimed limitations: forming a first conductive layer on the carrier; forming a second conductive layer on the first conductive layer; patterning the second conductive layer; patterning the first conductive layer using the second conductive layer as a mask; and etching the first conductive layer after depositing the first encapsulant to create conductive vias recessed within the first encapsulant, as required by independent claim 26.
Additionally, the prior art, particularly Baek et al., U.S. Patent 10,403,562, fails to anticipate or render obvious, the following limitations in combination with the claimed limitations: forming a first conductive layer on the carrier; forming a second conductive layer on the first conductive layer; patterning the second conductive layer; patterning the first conductive layer using the second conductive layer as a mask; disposing an electrical component on the second conductive layer after patterning the first conductive layer; and depositing a first encapsulant over the electrical component, first conductive layer, and second conductive layer to form a module, as required by independent claim 31.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2014/0264905 discloses forming modules and placing them on a substrate as does US 2014/0091482.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
April 16, 2026
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