Prosecution Insights
Last updated: August 17, 2026
Application No. 18/315,614

CONDUCTIVE ELEMENT, DISPLAY DEVICE, AND METHOD OF FABRICATING DISPLAY DEVICE

Final Rejection §103
Filed
May 11, 2023
Priority
Aug 03, 2022 — RE 10-2022-0096970
Examiner
LEE, EUGENE
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
748 granted / 914 resolved
+13.8% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
41 currently pending
Career history
947
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
59.9%
+19.9% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
13.3%
-26.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 914 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 thru 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. US 2009/0267049 A1 in view of Sung US 2017/0317228 A1. Cho discloses (see, for example, FIG. 1A) a conductive element 100 comprising a first semiconductor layer 110b, second semiconductor layer 110c, active layer 110a, element insulating layer 130, and conductive pattern layer 120. In paragraph [0061], Cho discloses the conductive pattern layer 120 includes gold, silver, etc. Cho does not disclose a cladding layer doped with a conductive dopant, the cladding layer around the active layer. However, Sung discloses (see, for example, paragraph [0063] and FIG. 5(b) a conductive element comprising a cladding layer doped with a conductive dopant above and/or below the active layer 50b. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a cladding layer doped with a conductive dopant, the cladding layer around the active layer in order to improve carrier confinement to the active region while maximizing light production. Regarding claim 2, see, for example, FIG. 1B wherein Cho discloses the conductive pattern layer 120 surrounds the element insulating layer 130 in a cross-sectional direction of the conductive element 100, and the cross-sectional direction is different from a direction from the first end portion toward the second end portion. Regarding claim 3, see, for example, paragraph [0061] and FIG. 1A wherein Cho discloses the conductive pattern layer 120 includes gold, silver, etc. and is electrically insulated from the first semiconductor layer 110b, the second semiconductor layer 110c, and the active layer 110a by the element insulating layer 130. Regarding claim 4, see, for example, FIG. 1A wherein Cho discloses the conductive pattern layer 120 exposes a first portion of the element insulating layer 130 adjacent to the first end portion and a second portion of the element insulating layer 130 adjacent to the second end portion. Claim(s) 5, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. US 2009/0267049 A1 in view of Sung US 2017/0317228 A1 as applied to claims 1-4 above. In paragraph [0062], Cho discloses the conductive pattern layer 120 having generally no maximum thickness, but does not specifically disclose the conductive pattern layer having a thickness in a range of about 200 nm to about 350 nm. However, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the conductive pattern layer having a thickness in a range of about 200 nm to about 350 nm in order to ensure coupling between the conductive layer and active region for enhanced light emission rate and efficiency, and since it has been held that discovering the optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980). Regarding claim 6, Cho discloses (see, for example, FIG. 1a) the second length of the conductive element 120 being shorter than the first length of the element isolating layer 130, but does not specifically disclose the conductive element having a first length in a direction from the first end portion toward the second end portion, the conductive pattern layer having a second length in the direction from the first end portion toward the second end portion, and a ratio of the first length to the second length being in a range of about 1.3 to about 1.6. However, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have disclose the conductive element having a first length in a direction from the first end portion toward the second end portion, the conductive pattern layer having a second length in the direction from the first end portion toward the second end portion, and a ratio of the first length to the second length being in a range of about 1.3 to about 1.6 in order to improve light emission, and since it has been held that discovering the optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980). Allowable Subject Matter Claims 7 thru 15, and 17 thru 20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a display device comprising: a chip-on-film including a first portion electrically connected to the conductive element and a second portion electrically connected to a flexible circuit component, wherein the conductive element comprises: a first semiconductor layer adjacent to a first end portion of the conductive element; a second semiconductor layer adjacent to a second end portion of the conductive element; an active layer disposed between the first semiconductor layer and the second semiconductor layer; an element insulating layer covering the active layer and exposing the first end portion and the second end portion; and a conductive pattern layer disposed on the element insulating layer, the conductive pattern layer electrically connecting the pad line to the chip-on-film, wherein the conductive element extends in a direction parallel to an upper surface of the base layer, the direction from the first semiconductor layer to the second semiconductor layer. Regarding claim 19, the references of record, either singularly or in combination, do not teach or suggest at least a display device comprising: a first electrode and a second electrode disposed on a base layer; a conductive element disposed on the first electrode and the second electrode; a first connection electrode electrically connected to a first end portion of the conductive element; and a second connection electrode electrically connected to a second end portion of the conductive element, wherein the conductive element comprises: a first semiconductor layer adjacent to the first end portion; a second semiconductor layer adjacent to the second end portion; an active layer disposed between the first semiconductor layer and the second semiconductor layer; an element insulating layer covering the active layer and exposing the first end portion and the second end portion; and a conductive pattern layer disposed on the element insulating layer, wherein the conductive element extends in a direction parallel to an upper surface of the base layer, the direction from the first semiconductor layer to the second semiconductor layer. Regarding claim 20, the references of record, either singularly or in combination, do not teach or suggest at least an electronic device comprising: a pad line disposed on a base layer; a plurality of conductive elements electrically connected to the pad line; a chip-on-film including a first portion electrically connected to the plurality of conductive elements and a second portion electrically connected to a flexible circuit component; and a non-conductive coupling layer coupling the chip-on-film to some of components disposed on the base layer, wherein at least one of the plurality of conductive elements extends in a direction parallel to an upper surface of the base layer, the direction from a first semiconductor layer of the at least one of the plurality of conductive elements to a second semiconductor layer of the at least one of the plurality of conductive elements. Response to Arguments Applicant’s arguments with respect to claim(s) 1-15, and 17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. INFORMATION ON HOW TO CONTACT THE USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Eugene Lee June 22, 2026 /EUGENE LEE/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

May 11, 2023
Application Filed
Feb 23, 2026
Non-Final Rejection mailed — §103
Apr 16, 2026
Examiner Interview Summary
Apr 16, 2026
Applicant Interview (Telephonic)
May 18, 2026
Response Filed
Jul 02, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
88%
With Interview (+5.7%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 914 resolved cases by this examiner. Grant probability derived from career allowance rate.

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