DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species A in the reply filed on 19 November 2025 is acknowledged. The traversal is on the ground(s) that the species do not present a serious search burden, and have not been shown to be mutually exclusive. This is not found persuasive because each species requires a unique set of characteristics as presented in the instant application, affecting the focus of a search. Further, each has been presented individually, with the inventive features occupying the same location in the display circuit layout, making the species mutually exclusive.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 11 May 2023 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 20170330928 A1, hereinafter “Choi”), in view of Bae et al (US 20190237494 A1, hereinafter “Bae”).
Regarding Claim 1 – Choi discloses a display device comprising: a substrate (110 [0046] and Fig. 8); a semiconductor layer disposed on the substrate (130a-g [0074] and Fig. 3); a gate conductive layer disposed on the semiconductor layer (125a-g [0086] and Fig. 3); and a first data conductive layer (171-175 [0094] and Fig. 3) disposed on the gate conductive layer, wherein the gate conductive layer includes: a first scan line (121 [0052] and Fig. 3) and a light emitting control line (123 [0052] and Fig. 3) extending along a first direction, and a first gate electrode (125a [0077] and Fig. 3) disposed between the first scan line and the light emitting control line in a plan view, the first data conductive layer includes a first connecting member (127 [0093] and Fig. 3) overlapping the first gate electrode, the first connecting member includes a recessed opening (RO in annotated Fig. 6) and a second opening (represented by HO in annotated Fig. 6), and a part of the second opening is disposed between the first gate electrode and the light emitting control line in a plan view (Part in annotated Fig. 3).
Choi fails to explicitly disclose the second opening is a hole opening with a continuous border.
However, Bae discloses a hole opening with a continuous border in the first connecting member, where the opening extends beyond the edge of the underlying gate electrode (Bae [0139-141] and Fig. 10).
Bae discloses a display device very similar to Choi. Bae teaches an opening in the second capacitor electrode that extends beyond the edge of the first capacitor electrode for the benefit of reducing the sensitivity of the capacitor to process variation (Bae [0005-0009]). Therefore, it would have been obvious prior to the effective filing date of the claimed invention to consider combining the teachings of Choi and Bae to implement a hole opening in the second capacitor electrode (first connecting member) extending beyond the edge of the first capacitor electrode (first gate electrode) for the benefit of reducing the sensitivity of the capacitor to process variation.
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Regarding Claim 2 – Choi modified by Bae discloses all the limitations of claim 1.
The combination of Choi and Bae further discloses the recessed opening and the hole opening of the first connecting member are adjacent to each other in a second direction perpendicular to the first direction (RO and HO adjacent in second direction in annotated Choi Fig. 6).
Regarding Claim 3 – Choi modified by Bae discloses all the limitations of claim 1.
The combination of Choi and Bae further discloses a width of the hole opening of the first connecting member in the first direction and a width of the recessed opening of the first connecting member in the first direction are substantially same as each other (Shown the same width in Choi Fig. 3 and annotated Choi Fig. 6 [0071]).
Regarding Claim 4 – Choi modified by Bae discloses all the limitations of claim 1.
The combination of Choi and Bae further discloses the first data conductive layer further includes a second connecting member (174 Choi [0093]), and the second connecting member is in contact (CNT8 Choi [0102] and Fig. 6) with the first gate electrode in the recessed opening of the first connecting member.
Regarding Claim 5 – Choi modified by Bae discloses all the limitations of claim 4.
The combination of Choi and Bae further discloses a part of the second connecting member is in contact (CNT9 Choi [0102] and Fig. 6) with the semiconductor layer (177c Choi [0102] and Fig. 3), and the second connecting member electrically connects the first gate electrode and the semiconductor layer (through CNT8 and CNT9 Choi [0102] and Fig. 6).
Regarding Claim 6 – Choi modified by Bae discloses all the limitations of claim 2.
The combination of Choi and Bae further discloses the first connecting member includes a protrusion protruding in the second direction (P extends in both 1st and 2nd directions in annotated Choi Fig. 6), and the protrusion of the first connecting member is in contact with the semiconductor layer (CNT3 Choi [0118]).
Regarding Claim 7 – Choi modified by Bae discloses all the limitations of claim 1.
The combination of Choi and Bae further discloses a second data conductive layer disposed on the first data conductive layer (127 and 172 may be in different layers Choi [0121] and Fig. 10), and the second data conductive layer further includes a driving voltage line (172 Choi [0049]) extending along a second direction perpendicular to the first direction (Choi Fig. 10).
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Regarding Claim 9 – Choi modified by Bae discloses all the limitations of claim 7.
The combination of Choi and Bae further discloses a part of the driving voltage line is in contact with the first connection member (172 in contact with 127 on an edge in Choi Fig. 6 [0100] and via a contact in Choi Fig. 10 [0121]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 20170330928 A1, hereinafter “Choi”) , in view of Bae et al (US 20190237494 A1, hereinafter “Bae”), and further in view of Lee et al (US 20210359056 A1, hereinafter “Lee”).
Regarding Claim 8 – Choi modified by Bae discloses all the limitations of claim 7.
The combination of Choi and Bae fails to disclose the driving voltage line overlaps a recessed opening and a hole opening of the first connecting member.
However, Lee discloses the driving voltage line (172 Lee [0112]) overlaps the first connecting member where the recessed opening and hole opening would be (Annotated Lee Fig. 2).
Lee discloses an analogous display circuit to Choi. Lee teaches the driving voltage line may overlap the first connecting member in the second direction where the recessed opening and hole opening are in Choi for the benefit of connecting the driving voltage to the connecting member (storage electrode 1153 [0112] and Fig. 2) while allowing space for a data line (171 [0111] and Fig. 2) and pixel connection electrode (9175 [0113] and Fig. 2) in the same layer. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Choi and Lee to place the driving voltage line overlapping the openings of the first connecting member to allow space for a data line and pixel connection electrode in the same layer.
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Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 20170330928 A1, hereinafter “Choi”) , in view of Bae et al (US 20190237494 A1, hereinafter “Bae”), and further in view of Tanikame (US 20090046041 A1, hereinafter “Tanikame”).
Regarding Claim 10 – Choi modified by Bae discloses all the limitations of claim 1.
The combination of Choi and Bae fails to disclose the first data conductive layer further includes a first scan auxiliary line extending along the first direction, and the first scan auxiliary line is electrically connected to the first scan line.
However, Tanikame discloses the first data conductive layer further includes a first scan auxiliary line (WS_AUX in annotated Tanikame Fig. 8) extending along the first direction, and the first scan auxiliary line is electrically connected to the first scan line (by contacts 301 and 303, and wiring pattern 302 Tanikame [0129]).
Tanikame discloses a similar OLED circuit layout to Choi. Tanikame teaches connecting the scan line signal to a write transistor by way of a scan auxiliary line placed parallel to the scan line ([0129]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Choi and Tanikame to use an auxiliary scan line parallel to, and electrically connected to, the scan line to enable connection to a write transistor.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 7:30a-5p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898