DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group II (claims 8-14) in the reply filed on 12/8/25 is acknowledged. Applicant included additional claims 21-33, and stated these claims are included in Group II.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8, and 21 thru 29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Min et al. US 2013/0175616 A1. Min discloses (see, for example, FIG. 4) a method, comprising: doping a substrate with a first dopant type to form a first doped region 44/44’ of a semiconductor device; doping the substrate with a second dopant type to form a second doped region 50/50’/57’ of the semiconductor device adjacent to the first doped region 44/44’; forming, on the second doped region 50/50’/57’, a buffer layer 54 of the semiconductor device; forming, over the first doped region 44/44’, over the second doped region 50/50’/57’, and over the buffer layer 54, a gate oxide layer 56 of the semiconductor device; and forming, over the gate oxide layer 56, a gate structure 58 of the semiconductor device.
Regarding claim 21, see, for example, FIG. 4 wherein Min discloses a method, comprising: forming a first doped region 44/44’, comprising a first dopant type, in a substrate; forming a second doped region 50/50’/57’, comprising a second dopant type, in the substrate and adjacent to the first doped region 44/44’; forming a first source/drain region 48, comprising the second dopant type, in the substrate and on the first doped region 44/44’; forming a second source/drain region 52, comprising the second dopant type, in the substrate and on the second doped region 50/50’/57’; forming a buffer layer 54 over a portion of the second doped region 50/50’/57’; forming a gate oxide layer 56 over a portion of the first doped region 44/44’, over the buffer layer 54, and over an extension region 54’ of the second doped region 50/50’/57’; and forming a gate structure 58 over the gate oxide layer 56.
Regarding claim 22, see, for example, FIG. 4 wherein Min discloses a dopant concentration of the second dopant type in the second doped region 50/50’/57’ being lesser relative to a dopant concentration of the second dopant type in the N+ first source/drain region 48.
Regarding claim 23, see, for example, FIG. 4 wherein Min discloses the buffer layer 54 being in contact with the gate oxide layer 56 on a first side of the buffer layer 54; and wherein the buffer layer 54 being in contact with the portion of the second doped region 50/50’/57’ on a second side of the buffer layer 54 opposing the first side.
Regarding claim 24, see, for example, FIG. 4 wherein Min discloses the buffer layer 54 being in contact with the extension region 54’ of the second doped region 50/50’/57’ on a third side of the buffer layer 54.
Regarding claim 25, see, for example, FIG. 4 wherein Min discloses the extension region 54’ of the second doped region 50/50’/57’ being between the first doped region 44/44’ and the buffer layer 54 under the gate oxide layer 56.
Regarding claim 26, see, for example, FIG. 4 wherein Min discloses the extension region 54’ of the second doped region 50/50’/57’ being in contact with the gate oxide layer 56.
Regarding claim 27 and the limitation “wherein the second source/drain region is configured to operate at a greater operational voltage relative to an operational voltage of the gate structure.”, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F. 2d 1647 (1987).
Regarding claim 28, see, for example, FIG. 4 wherein Min discloses (see, for example, FIG. 4) a method, comprising: forming, in a substrate, a first doped region 44/44’ and a second doped region 50/50’/57’ adjacent to the first doped region 44/44’; forming a buffer layer 54 over at least a portion of the second doped region 50/50’/57’: forming a gate oxide layer 56 over the first doped region 44/44’, over the second doped region 50/50’/57’, and over the buffer layer 54; and forming a gate structure 58 on the gate oxide layer 56.
Regarding claim 29, see, for example, paragraph [0031] wherein Min discloses the buffer layer 54 being .1 to 1 micrometer (i.e. 100 nanometers to 1000 nanometers), which is a thickness in a range of approximately 10 nanometers to approximately 100 nanometers.
Claim(s) 8, 21, 23 thru 28, 30, 31, and 33 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitamura et al. US 5,844,275. Kitamura discloses (see, for example, FIG. 1) a method, comprising: doping a substrate with a first dopant type to form a first doped region 2 of a semiconductor device; doping the substrate with a second dopant type to form a second doped region 4 of the semiconductor device adjacent to the first doped region 2; forming, on the second doped region 4, a buffer layer 5 of the semiconductor device; forming, over the first doped region 2, over the second doped region 4, and over the buffer layer 5, a gate oxide layer 6 of the semiconductor device; and forming, over the gate oxide layer 6, a gate structure 7 of the semiconductor device.
Regarding claim 21, see, for example, FIG. 1 wherein Kitamura discloses a method, comprising: forming a first doped region 2, comprising a first dopant type, in a substrate; forming a second doped region 4, comprising a second dopant type, in the substrate and adjacent to the first doped region 2; forming a first source/drain region 9, comprising the second dopant type, in the substrate and on the first doped region 2; forming a second source/drain region 11, comprising the second dopant type, in the substrate and on the second doped region 4; forming a buffer layer 5 over a portion of the second doped region 4; forming a gate oxide layer 6 over a portion of the first doped region 2, over the buffer layer 5, and over an extension region (i.e. region on the left side of the buffer layer 5) of the second doped region 4; and forming a gate structure 7 over the gate oxide layer 6.
Regarding claim 23, see, for example, FIG. 1 wherein Kitamura discloses the buffer layer 5 being in contact with the gate oxide layer 6 on a first side of the buffer layer 5; and wherein the buffer layer 5 being in contact with the portion of the second doped region 4 on a second side of the buffer layer 5 opposing the first side.
Regarding claim 24, see, for example, FIG. 1 wherein Kitamura discloses the buffer layer 5 being in contact with the extension region of the second doped region 4 on a third side of the buffer layer 5.
Regarding claim 25, see, for example, FIG. 1 wherein Kitamura discloses the extension region of the second doped region 4 being between the first doped region 2 and the buffer layer 5 under the gate oxide layer 6.
Regarding claim 26, see, for example, FIG. 1 wherein Kitamura discloses the extension region of the second doped region 4 being in contact with the gate oxide layer 6.
Regarding claim 27 and the limitation “wherein the second source/drain region is configured to operate at a greater operational voltage relative to an operational voltage of the gate structure.”, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F. 2d 1647 (1987).
Regarding claim 28, see, for example, FIG. 1 wherein Kitamura discloses a method, comprising: forming, in a substrate, a first doped region 2 and a second doped region 4 adjacent to the first doped region 2; forming a buffer layer 5 over at least a portion of the second doped region 4: forming a gate oxide layer 6 over the first doped region 2, over the second doped region 4, and over the buffer layer 5; and forming a gate structure 7 on the gate oxide layer 6.
Regarding claim 30, see, for example, column 5, line 14 wherein Kitamura discloses the buffer layer comprising an oxide, which is formed in silicon.
Regarding claim 31, see, for example, column 6, line 35 wherein Kitamura discloses the gate oxide layer 6 being 20 nm (i.e. 200 angstroms).
Regarding claim 33, see, for example, column 5, line 10 wherein Kitamura discloses the trench 3 (i.e. buffer layer 5) being 1 um deep (i.e. 1000 nm), and in column 6, line 35 wherein Kitamura discloses the gate oxide layer 6 being 20 nm (i.e. 200 angstroms).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 thru 12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. US 2013/0175616 A1 as applied to claims 8, 21-29 above, and further in view of Abadeer et al. US 6,876,035 B2. Min does not disclose forming the buffer layer comprises: forming a masking layer over the first doped region and over the second doped region; forming a pattern in the masking layer; and forming the buffer layer based on the pattern in the masking layer. However, Abadeer discloses (see, for example, FIG. 6-8, and column 5, lines 6-10) forming a masking layer 60/51 and patterned to form the trench 61 to form the buffer layer 40. It would have been obvious to one of ordinary skill in the art to form the buffer layer comprises: forming a masking layer over the first doped region and over the second doped region; forming a pattern in the masking layer; and forming the buffer layer based on the pattern in the masking layer in order to precisely form the buffer layer within the silicon substrate.
Regarding claim 10, see, for example, FIG. 7 wherein Abadeer discloses how portions of the semiconductor substrate are exposed through the pattern 60/51, and then forming the buffer layer 40.
Regarding claim 11, see, for example, FIG. 3 wherein Min discloses the second portion of the second doped region 50/50’/57’corresponds to an extension region 54’ of the second doped region 50/50’/57’; wherein the buffer layer 54 is in contact with a first side of the extension region 54’; and wherein the first doped region 44/44’ is in contact with a second side of the extension region 54’ opposing the first side.
Regarding claim 12, see, for example, FIG. 8 wherein Abadeer discloses the buffer layer 40 based on the pattern 51.
Regarding claim 14, see, for example, FIG. 6 wherein Abadeer discloses performing etch operations to remove the masking layer 60/51, and FIG. 4 wherein Abadeer discloses a top surface of the buffer layer 41 being coplanar with a top surface of the first doped region 202.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. US 2013/0175616 A1 as applied to claims 8, 21-29 above, and further in view of Morton et al. US 6,548,874 B1. Min does not disclose a spacer layer on sidewalls of the gate structure after forming the gate structure. However, Morton discloses (see, for example, FIG. 2A) a method comprising forming a spacer layer 110 on the sidewalls of the gate structure 40 after forming the gate structure. It would have been obvious to one of ordinary skill in the art to form a spacer layer on sidewalls of the gate structure after forming the gate structure in order to protect the sidewalls of the gate structure.
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a method, comprising: forming, on the second doped region, a buffer layer of the semiconductor device; forming, over the first doped region, over the second doped region, and over the buffer layer, a gate oxide layer of the semiconductor device; and forming, over the gate oxide layer, a gate structure of the semiconductor device, further comprising: performing one or more etch operations, based on the gate structure, to remove a first portion of the gate oxide layer and to remove a first portion of the buffer layer, wherein a second portion of the gate oxide layer remains under the gate structure, and wherein a second portion of the buffer layer remains under the gate structure.
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Eugene Lee
January 16, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815