DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 5/26/2026 is acknowledged. Claims 1-16 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a transistor stack” in line 3. It is unclear whether this is the same or different transistor stack defined in the preamble (line 2) of the claim. For the purpose of examination, it is interpreted to be the same.
Claim 1 recites “a first p-dipole from the first p-dipole dopant source layer” in lines 5-6. There is no antecedent bases for the first p-dipole dopant source layer in the claim. For the purpose of examination, it is interpreted that the limitation “forming a first n-dipole dopant source layer…” in line 4 is “forming a first p-dipole dopant source layer…” to be consistent with other claims.
Allowable Subject Matter
Claims 1-8 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 9-16, 25-28 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art of record does not disclose or fairly suggest a method of forming a gate stack of a transistor that comprises: “performing a first thermal drive-in process that drives a first p-dipole dopant from the first p-dipole dopant source layer into the first high-k dielectric layer;” and “forming a second high-k dielectric layer of a second gate stack of the transistor stack, wherein the second high-k dielectric layer is formed over the first gate stack;” and “forming a second p-dipole dopant source layer over the second high-k dielectric layer; performing a second thermal drive-in process that drives a second p-dipole dopant from the second p-dipole dopant source layer into the second high-k dielectric layer, wherein a drive- in temperature of the second thermal drive-in process is less than 600⁰C” along with other limitations of the claim.
Regarding claim 9, the prior art of record does not disclose or fairly suggest a method of forming a gate stack of a transistor that comprises: “wherein the dipole engineering process includes: forming a p-dipole dopant source layer over the gate dielectric, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the gate dielectric, wherein a drive-in temperature of the thermal drive-in process is less than 600°C, and removing the p-dipole dopant source layer, wherein the dipole engineering process is a first dipole engineering process, the thermal drive-in process is a first thermal drive-in process, the drive-in temperature is a first drive-in temperature, the gate dielectric is a first gate dielectric, the gate electrode is a first gate electrode, the gate stack is a first gate stack, the p-dipole dopant source layer is a first p-dipole dopant source layer, and the p-dipole dopant is a first p-dipole dopant; and wherein the forming the first transistor includes forming a second gate stack, wherein the second gate stack includes a second gate dielectric and a second gate electrode, and performing a second dipole engineering process, wherein the second dipole engineering process includes: forming a second p-dipole dopant source layer over the second gate dielectric of the second gate stack of the first transistor, performing a second thermal drive-in process that drives a second p-dipole dopant from the second p-dipole dopant source layer into the second gate dielectric, wherein a second drive-in temperature of the second thermal drive-in process is less than 600°C, and removing the second p-dipole dopant source layer” along with other limitations of the claim.
Regarding claim 12, the prior art of record does not disclose or fairly suggest a method of forming a gate stack of a transistor that comprises: “performing a dipole engineering process, wherein the dipole engineering process includes: forming a p-dipole dopant source layer over the gate dielectric, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the gate dielectric, wherein a drive-in temperature of the thermal drive-in process is less than 600°C, and removing the p-dipole dopant source layer, wherein the dipole engineering process is a first dipole engineering process, the thermal drive-in process is a first thermal drive-in process, the drive-in temperature is a first drive-in temperature, the gate dielectric is a first gate dielectric, the gate electrode is a first gate electrode, the gate stack is a first gate stack, the p-dipole dopant source layer is a first p-dipole dopant source layer, and the p-dipole dopant is a first p-dipole dopant; and wherein the forming the first transistor includes forming a second gate stack of the first transistor and performing a second dipole engineering process, wherein the second gate stack includes a second gate dielectric and a second gate electrode, and further wherein the second dipole engineering process includes: forming a second p-dipole dopant source layer over the second gate dielectric of the second gate stack of the first transistor, performing a second thermal drive-in process that drives a second p-dipole dopant from the second p-dipole dopant source layer into the second gate dielectric, wherein a second drive-in temperature of the second thermal drive-in process is at least 600°C, and removing the second p-dipole dopant source layer” along with other limitations of the claim.
The closest prior art are Chung et al. (CN 113675197 A) (for the purpose of compact prosecution, the US Application US 2022/0037497 A1 is used hereinafter as an English translation of the Chinese application), and Pao et al. (US 2021/0391439 A1).
Chung teaches a method (1100 in Figs. 85-98C of Chung) comprising: forming a first transistor (lower transistor 260a) of a transistor stack (260a-260b); bonding (step 1126 in Fig. 85) the first transistor of the transistor stack to a precursor (204b in Fig. 96A-C) for fabricating a second transistor (260b) of the transistor stack; and forming the second transistor (260b) over the first transistor, wherein the forming the second transistor includes processing the precursor (as shown in Figs. 96A-97C), forming a gate stack (254b in Fig. 97A) of the second transistor, wherein the gate stack includes a gate dielectric (256) and a gate electrode (258). But the transistor stack of Chung is a p-type transistor on a n-type transistor, not the same p-type.
Pao teaches a method (100 in Fig. 1 of Pao) for forming a gate stack (metal gate 236 in Fig. 15) of a transistor (420), wherein the transistor forms a portion of a transistor stack (transistor stack is from substrate 202 to gate 236), the method comprising: forming a high-k dielectric layer (222 in Fig. 5); forming a dipole dopant source layer (224/230) over the high-k dielectric layer; performing a thermal drive-in process (anneal process 300 in Fig. 13) that drives a dipole dopant (lanthanum, yttrium or aluminum, as described in [0034]) from the dipole dopant source layer into the high-k dielectric layer (as described in [0034]); and after removing the dipole dopant source layer (step 120 of method 100 in Fig. 1), forming at least one electrically conductive gate layer (work function layer and metal fill layer of the metal gate stack 236, as described in [0038] of Pao) over the high-k dielectric layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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