DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-16, in the reply filed on 10/22/2025 is acknowledged. Claims 17-20 have been canceled. Claims 21-24 are added.
Specification
The amendment to the specification submitted on 10/22/2025 is acknowledged. Paragraph [0051] is replaced. No new matter has been introduced. The amendment is therefore accepted and entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Pao et al. (US 2021/0391439 A1) in view of Savant et al. (US 2021/0391220 A1).
Regarding claim 1, Pao teaches a method (100 in Fig. 1 of Pao) for forming a gate stack (metal gate 236 in Fig. 15) of a transistor (420), wherein the transistor forms a portion of a transistor stack (transistor stack is from substrate 202 to gate 236), the method comprising:
forming a high-k dielectric layer (222 in Fig. 5);
forming a dipole dopant source layer (230) over the high-k dielectric layer;
performing a thermal drive-in process (anneal process 300 in Fig. 13) that drives a dipole dopant (lanthanum, yttrium or aluminum, as described in [0034]) from the dipole dopant source layer into the high-k dielectric layer (as described in [0034]); and
after removing the dipole dopant source layer (step 120 of method 100 in Fig. 1), forming at least one electrically conductive gate layer (work function layer and metal fill layer of the metal gate stack 236, as described in [0038] of Pao) over the high-k dielectric layer.
But Pao does not teach that the dipole dopant is a p-dipole dopant, and that wherein a drive-in temperature of the thermal drive-in process is less than 600°C.
However Pao discloses that the temperature range of the anneal process 300 is between 500°C to 900°C (see [0034] of Pao). This range overlaps the claim range of “less than 600°C”.
Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the temperature range of the anneal process 300 to be less than 600°C in order to minimize the thermal damage to the device. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
But Pao does not teach that the dipole dopant is a p-dipole dopant.
Savant teaches that for pFET (112P1-112P3 in Fig. 1C of Savant), the high-k gate dielectric layer can doped with Ti, TiO2… to improve the p-type performance of pFET (see [0040] of Savant).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have doped p-type dopant into the gate dielectric of Pao, as disclosed by Savant, in order to improve the p-type performance.
Regarding claim 2, Pao in view of Savant teaches all limitations of the method of claim 1, but does not explicitly teach wherein the drive-in temperature of the thermal drive-in process is about 300°C to about 500°C.
However Pao discloses that the temperature range of the anneal process 300 is between 500°C to 900°C (see [0034] of Pao) which touches the claimed range of “about 300°C to about 500°C”.
Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the temperature range from about 300°C to about 500°C, since it has been held that in the case where the claimed ranges “do not overlap with the prior art but are merely close”, a prima facie case of obviousness exists (see Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985); see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP §2144.05.I for more details).
Regarding claim 3, Pao in view of Savant teaches all limitations of the method of claim 1, and also teaches wherein the p-dipole dopant is titanium (as taught by Savant in claim 1 above).
Regarding claim 4, Pao in view of Savant teaches all limitations of the method of claim 1, and also teaches wherein the p-dipole dopant source layer includes titanium and oxygen (as described in [0062] of Savant), nitrogen, carbon, or a combination thereof.
Regarding claim 5, Pao in view of Savant teaches all limitations of the method of claim 1, and also teaches wherein: the p-dipole dopant source layer is a titanium oxide layer (as described in [0062] of Savant); and the high-k dielectric layer is a zirconium-based oxide layer (as described in [0028] of Pao).
Regarding claim 6, Pao in view of Savant teaches all limitations of the method of claim 1, and also teaches wherein: the p-dipole dopant source layer is a titanium oxide layer (as described in [0062] of Savant); and the high-k dielectric layer is a hafnium-based oxide layer (as described in [0028] of Pao).
Regarding claim 7, Pao in view of Savant teaches all limitations of the method of claim 1, and further comprising forming an interfacial layer (220 in Fig. 4 of Pao) before forming the high-k dielectric layer, wherein the interfacial layer and the high-k dielectric layer form a gate dielectric of the gate stack (as shown in Fig. 14 of Pao).
Regarding claim 8, Pao in view of Savant teaches all limitations of the method of claim 7, and also teaches the method further comprising tuning parameters of the thermal drive-in process to provide the gate dielectric with a desired p-dipole dopant profile along a thickness of the gate dielectric, wherein a peak of the desired p-dipole dopant profile is located at an interface between the high-k dielectric layer and the interfacial layer ± 0.5 nm, and further wherein the peak of the desired p-dipole dopant profile corresponds with a location in the gate dielectric having a maximum p-dipole dopant concentration (In Savant’s method, the dopant is diffused through the high-k gate dielectric layer so that the peak of the dopant is located at the interface of the interfacial oxide layer and the high-k gate dielectric layer. This forms a dipole layer at the interface of the interfacial oxide layer and the high-k gate dielectric layer, see Fig. 1O of Savant).
Claims 9, 14-16, and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (CN 113675197 A) (for the purpose of compact prosecution, the US Application US 2022/0037497 A1 is used hereinafter as an English translation of the Chinese application) in view of Pao and Savant.
Regarding claim 9, Chung teaches a method (1100 in Figs. 85-98C of Chung) comprising:
forming a first transistor (lower transistor 260a) of a transistor stack (260a-260b);
bonding (step 1126 in Fig. 85) the first transistor of the transistor stack to a precursor (204b in Fig. 96A-C) for fabricating a second transistor (260b) of the transistor stack; and
forming the second transistor (260b) over the first transistor, wherein the forming the second transistor includes processing the precursor (as shown in Figs. 96A-97C), forming a gate stack (254b in Fig. 97A) of the second transistor, wherein the gate stack includes a gate dielectric (256) and a gate electrode (258).
But Chung does not teach that the forming the second transistor includes: performing a dipole engineering process, wherein the dipole engineering process includes: forming a p-dipole dopant source layer over the gate dielectric, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the gate dielectric, wherein a drive-in temperature of the thermal drive-in process is less than 600°C, and removing the p-dipole dopant source layer.
Pao teaches a method (100 in Fig. 1 of Pao) for forming a gate stack (metal gate 236 in Fig. 15) of a transistor (420 in Fig. 15), wherein the transistor forms a portion of a transistor stack (transistor stack is from substrate 202 to gate 236), the method comprising: forming a high-k dielectric layer (222 in Fig. 5, as described in [0028] of Pao); forming a dipole dopant source layer (dipole layer 230 in Fig. 12) over the high-k dielectric layer; performing a thermal drive-in process (anneal process 300 in Fig. 13) in the range of 500°C to 900°C to drive a dipole dopant from the dipole dopant source layer into the high-k dielectric layer (as described in [0034]); removing the dipole dopant source layer (step 120 of method 100 in Fig. 1); and forming a gate structure (work function layer and metal fill layer of the metal gate stack 236, as described in [0038] of Pao) over the high-k dielectric layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have diffused appropriate dipole dopant into the transistors, as disclosed by Pao, so that the threshold voltage can be fine-tuned to match the device’s needs.
As incorporated, since the claimed ranges of “less than 600°C” overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
But Chung in view of Pao does not teach that the dipole dopant is a p-dipole dopant.
Savant teaches that for pFET (112P1-112P3 in Fig. 1C of Savant), the high-k gate dielectric layer can doped with Ti, TiO2… to improve the p-type performance of pFET while the gate dielectric layer for the nFET can be doped with n-type dopants such as lanthanum, erbium, strontium, magnesium… (see [0040] of Savant).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have doped p-type dopant into the gate dielectric of Pao, as disclosed by Savant, in order to improve the p-type performance.
Regarding claim 14, Chung-Pao-Savant teaches all limitations of the method of claim 9, and also teaches wherein:
the dipole engineering process is a first dipole engineering process (as taught in claim 9 above), the thermal drive-in process is a first thermal drive-in process (as taught in claim 9 above), the gate dielectric is a first gate dielectric (as taught in claim 9 above), the gate electrode is a first gate electrode (as taught in claim 9 above), and the gate stack is a first gate stack (as taught in claim 9 above); and
the forming the first transistor includes forming a second gate stack (254a in Fig. 94A of Chung) of the first transistor and performing a second dipole engineering process (Pao’s dopant diffusing process to the bottom NFET as applied in claim 9 above), wherein the second gate stack includes a second gate dielectric (256 of 254a) and a second gate electrode (258 of 254a), and further wherein the second dipole engineering process includes:
forming an n-dipole dopant source layer (224 of Pao for the n-type dipole dopant) over the second gate dielectric of the second gate stack of the first transistor, performing a second thermal drive-in process (anneal process 300 in Fig. 13 of Pao) that drives an n-dipole dopant (the dipole dopant for the n-type) from the n-dipole dopant source layer into the second gate dielectric, and removing the n-dipole dopant source layer (step 120 of method 100 in Fig. 1 of Pao).
Regarding claim 15, Chung-Pao-Savant teaches all limitations of the method of claim 14, and also teaches wherein: the p-dipole dopant is titanium (as combined in claim 9 above); and a second drive-in temperature of the second thermal drive-in process is less than about 600°C (as combined in claim 9 above) and the n-dipole dopant is strontium, erbium, magnesium, or a combination thereof (as taught in claim 9 above).
Regarding claim 16, Chung-Pao-Savant teaches all limitations of the method of claim 14, and also teaches wherein: the p-dipole dopant is titanium (as taught in claim 9 above); and a second drive-in temperature of the second thermal drive-in process is at least 600°C (as taught in claim 9 above) and the n-dipole dopant is lanthanum (as taught in claim 9 above).
Regarding claim 21, Chung teaches a method (1100 in Figs. 85-98C of Chung) comprising:
forming a first device (lower transistor 260a in Fig. 94A) of a device stack (260a-b), wherein the first device includes a first semiconductor layer (nanowire channel 208 in Fig. 94A) that extends between a first source/drain (228S in Fig. 93A) and a second source/drain (228D), wherein the first device further includes a first gate stack (254a) disposed on the first semiconductor layer, wherein the first gate stack includes a first gate dielectric (256 of 254a) and a first gate electrode (258 of 254a); and
after forming the first device of the device stack, forming a second device (260b in Fig. 97A) of the device stack on the first device of the device stack, wherein the second device includes a second semiconductor layer (one of the upper nanowire channel 208 in Fig. 97A) that extends between a third source/drain (248S) and a fourth source/drain (248D), wherein the second device further includes a second gate stack (254b) disposed on the second semiconductor layer, wherein the second gate stack includes a second gate dielectric (256 of 254b) and a second gate electrode (258 of 254b), wherein the forming of the second device of the device stack includes performing a gate replacement process (as described in [0150]), wherein the gate replacement process includes:
removing a dummy gate (as described in [0150] lines 20-22 of Chung) to form a gate opening (opening formed by the removal of dummy gate), wherein the gate opening exposes the second semiconductor layer,
forming the second gate dielectric (256 of 254b in Fig. 97A) around the second semiconductor layer, wherein the second gate dielectric partially fills the gate opening.
forming the second gate electrode (258 of 254b in Fig. 98A) over the second gate dielectric, wherein the second gate electrode fills a remainder of the gate opening and the second gate electrode is formed around the second semiconductor layer (as shown in Fig. 98A).
But Chung does not teach that the gate replacement process including: forming a p-dipole dopant source layer over the second gate dielectric, wherein the p-dipole dopant source layer partially fills the gate opening and the p-dipole dopant source layer is formed around the second semiconductor layer, driving a p-dipole dopant from the p-dipole dopant source layer into the second gate dielectric, wherein a drive-in temperature is less than 600°C, and after removing the p-dipole dopant source layer.
Pao teaches a method (100 in Fig. 1 of Pao) for forming a gate stack (metal gate 236 in Fig. 15) of a transistor (420 in Fig. 15), wherein the transistor forms a portion of a transistor stack (transistor stack is from substrate 202 to gate 236), the method comprising: forming a high-k dielectric layer (222 in Fig. 5, as described in [0028] of Pao); forming a dipole dopant source layer (dipole layer 230 in Fig. 12) over the high-k dielectric layer; performing a thermal drive-in process (anneal process 300 in Fig. 13) in the range of 500°C to 900°C to drive a dipole dopant from the dipole dopant source layer into the high-k dielectric layer (as described in [0034]); removing the dipole dopant source layer (step 120 of method 100 in Fig. 1); and forming a gate structure (work function layer and metal fill layer of the metal gate stack 236, as described in [0038] of Pao) over the high-k dielectric layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have diffused appropriate dipole dopant into the transistors, as disclosed by Pao, so that the threshold voltage can be fine-tuned to match the device’s needs.
As incorporated, since the claimed ranges of “less than 600°C” overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
But Chung in view of Pao does not teach that the dipole dopant is a p-dipole dopant.
Savant teaches that for pFET (112P1-112P3 in Fig. 1C of Savant), the high-k gate dielectric layer can doped with Ti, TiO2… to improve the p-type performance of pFET while the gate dielectric layer for the nFET can be doped with n-type dopants such as lanthanum, erbium, strontium, magnesium… (see [0040] of Savant).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have doped p-type dopant into the gate dielectric of Pao, as disclosed by Savant, in order to improve the p-type performance.
Regarding claim 22, Chung-Pao-Savant teaches all limitations of the method of claim 21, and also teaches wherein the gate replacement process further includes performing a planarization process (as implied by the levelness of the top surfaces of the gates and the ILD in Fig. 15 of Pao) to remove the second gate dielectric and the second gate electrode from over a top of an interlayer dielectric layer (the interfacial layer is not shown in Chung, but described in [0046]. This layer is 220 in Pao).
Regarding claim 23, Chung-Pao-Savant teaches all limitations of the method of claim 21, and also teaches wherein: the forming the p-dipole dopant source layer over the second gate dielectric includes forming a titanium oxide layer (as taught by Savant in claim 21 above); and the driving the p-dipole dopant from the p-dipole dopant source layer into the second gate dielectric includes driving titanium into the second gate dielectric (as taught in claim 21 above).
Regarding claim 24, Chung-Pao-Savant teaches all limitations of the method of claim 21, and also teaches wherein: the second gate dielectric includes a high-k dielectric layer (2222 in Fig. 14 of Pao) and an interfacial layer (the interfacial layer is not shown in Chung, but described in [0046]. This layer is 220 in Pao); and the method further includes tuning parameters of the driving to provide the second gate dielectric with a desired p-dipole dopant profile along a thickness of the second gate dielectric, wherein a peak of the desired p-dipole dopant profile is located at an interface between the high- k dielectric layer and the interfacial layer ± 0.5 nm, and further wherein the peak of the desired p-dipole dopant profile corresponds with a location in the second gate dielectric having a maximum p-dipole dopant concentration (In Savant’s method, the dopant is diffused through the high-k gate dielectric layer so that the peak of the dopant is located at the interface of the interfacial oxide layer and the high-k gate dielectric layer. This forms a dipole layer at the interface of the interfacial oxide layer and the high-k gate dielectric layer, see Fig. 1O of Savant).
Allowable Subject Matter
Claims 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, the prior art of record does not disclose or fairly suggest a method “wherein: … the forming the first transistor includes forming a second gate stack, wherein the second gate stack includes a second gate dielectric and a second gate electrode, and performing a second dipole engineering process, wherein the second dipole engineering process includes: forming a second p-dipole dopant source layer over the second gate dielectric of the second gate stack of the first transistor, performing a second thermal drive-in process that drives a second p-dipole dopant from the second p-dipole dopant source layer into the second gate dielectric, wherein a second drive-in temperature of the second thermal drive-in process is less than 600°C, and removing the second p-dipole dopant source layer” along with other limitations of claims 9 and 10.
Regarding claim 12, the prior art of record does not disclose or fairly suggest a method “wherein: … the forming the first transistor includes forming a second gate stack of the first transistor and performing a second dipole engineering process, wherein the second gate stack includes a second gate dielectric and a second gate electrode, and further wherein the second dipole engineering process includes: forming a second p-dipole dopant source layer over the second gate dielectric of the second gate stack of the first transistor, performing a second thermal drive-in process that drives a second p-dipole dopant from the second p-dipole dopant source layer into the second gate dielectric, wherein a second drive-in temperature of the second thermal drive-in process is at least 600 C, and removing the second p-dipole dopant source layer” along with other limitations of claims 9 and 12.
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898