Prosecution Insights
Last updated: August 17, 2026
Application No. 18/316,439

THIN FILM TRANSISTOR STRUCTURE

Non-Final OA §102§103§112
Filed
May 12, 2023
Examiner
CHEN, JACK S J
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
438 granted / 572 resolved
+8.6% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
44 currently pending
Career history
617
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
31.8%
-8.2% vs TC avg
§102
32.5%
-7.5% vs TC avg
§112
27.3%
-12.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species 2 (Fig. 2), and E2, F1, G2, H2, I2 and J3 with claims 18-28, 30-32, 34-35 and 37-40 indicated by Applicant to read thereon in the reply filed on 4/21/2026 is acknowledged. While Examiner acknowledges that Applicant indicated that claims 35 and 37 read on the elected species 2, claims are drawn to non-elected species and are hereby withdrawn from further consideration therefor. Claims 35 and 37 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/21/2026. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 18-28, 30-32, 34 and 38-40 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Re claim 18, the phrase “forming a gate electrode over a substrate” was not described in the original specification (e.g., elected species fig. 2). Re claim 38, the phrase “forming a bottom gate electrode over a substrate” was not described in the original specification (e.g., elected species fig. 2). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 18-19, 32, 34 and 38 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin et al., US Patent No. 7,989,899 B2. Re claim 18. Yin et al. disclose a method comprising: forming a gate electrode G1/G2 over a substrate sub1 (e.g., fig. 2); forming a dielectric structure GI1/GI2’ (e.g., fig. 2) over the gate electrode; and forming a semiconductor channel C1/C2 (e.g., fig. 2) over the dielectric structure; wherein forming the dielectric structure GI1/GI2’ comprises embedding a first high-k dielectric layer within a gate dielectric (e.g., high-k dielectric layer/silicon nitride layer structure etc, col. 2, lines 4-15, 57-67 etc.); and the first high-k dielectric layer has a higher dielectric constant than the gate dielectric (e.g., high-k dielectric layer/silicon nitride layer), see figs. 1-11 and cols. 1-16 for more details. Re claim 19. The method of claim 18, wherein embedding the first high-k dielectric layer within the gate dielectric comprises: depositing a first layer of the gate dielectric (e.g., silicon nitride); depositing the first high-k dielectric layer (e.g., a lower portion of high-k dielectric etc.) over the first layer of the gate dielectric; and depositing a second layer of the gate dielectric (e.g., an upper portion of the high-k dielectric etc.) over the first high-k dielectric layer. Re claim 32. The method of claim 18, wherein the semiconductor channel comprises a metal oxide semiconductor (e.g., col 1, lines 65-66). Re claim 34. The method of claim 18, wherein the dielectric structure (GI1/GI2) is formed over the gate electrode G1/G2. Re claim 38. Yin et al. disclose a method comprising: forming a bottom gate electrode G1/G2 (e.g., fig. 2) over a substrate Sub1; forming a gate dielectric structure GI1/GI2 (e.g., fig. 2) over the bottom gate electrode, wherein forming the gate dielectric structure GI1/GI2 (e.g., high-k dielectric layer/silicon nitride layer structure; first high-k/second high-k/third high-k structure etc, col. 2, lines 4-15, 57-67 etc.) comprises: depositing a first layer of a gate dielectric (e.g., silicon nitride layer or first high-k); depositing a first high-k dielectric layer (e.g., a lower portion of the high-k or second high-k) over the first layer of the gate dielectric; and depositing a second layer of the gate dielectric (e.g., an upper portion of the high-k or third high -k) over the first high-k dielectric layer; depositing a semiconductor layer C1/C2 over the gate dielectric structure; and forming source and drain electrodes S1/S2/D1/D2 (e.g., fig. 2) over the semiconductor layer, wherein the bottom gate electrode, the gate dielectric structure, the semiconductor layer, and the source and drain electrodes form a transistor (e.g., fig. 2), see figs. 1-11 and cols. 1-16 for more details. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 20-26, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al., US Patent No. 7,989,899 B2. Yin et al. disclosed above; however, Yin et al. does not explicitly state the instant claims’ thickness as shown in claims 20-26, and 39. The thickness range and/or characteristics of claims 20-26 and 39 are considered to involve routine optimization while has been held to be within the level of ordinary skill in the art. As noted in In re Aller, the selection of reaction parameters such as thickness, temperature and concentration etc. would have been obvious: “Normally, it is to be expected that a change in temperature, or in concentration, or in both, would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed Acritical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934). Therefore, one of ordinary skill in the requisite art before the invention was made would have used any thickness range and/or characteristics suitable to the method in process of Yin et al. in order to optimize the performance of the process etc. Claims 27-28, 30-31 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al., US Patent No. 7,989,899 B2 in view of Chen et al., US Pub. No. 2005/0224897 A1. Yin et al. disclosed above, and in particular the high-k element can be considered to have four sublayers; however, Yin et al. does not explicitly show the high-k dielectric comprises a mixture of two metal oxides and/or the high-k has a distinct composition. Chen et al. teaches a similar device, which comprises dielectric structure 14A/14B/16 (e.g., fig. 1C) containing a mixture of two metal oxides (paragraph 18) and/or the high-k has a distinct composition 14B/16, see figs. 1-2 and pages 1-5. Therefore, the subject matter as a whole would have been obvious to one having ordinary skill in the art before the invention was made to use dielectric structure as taught by Chen et al. in the method of Yin et al. in order to reduce voltage threshold shifts etc. The thickness range and/or characteristics of claim 31 is considered to involve routine optimization while has been held to be within the level of ordinary skill in the art. As noted in In re Aller, the selection of reaction parameters such as thickness, temperature and concentration etc. would have been obvious: “Normally, it is to be expected that a change in temperature, or in concentration, or in both, would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed Acritical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934). Therefore, one of ordinary skill in the requisite art before the invention was made would have used any thickness range and/or characteristics suitable to the method in process of Yin et al. taken with Chen et al. in order to optimize the performance of the process etc. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACK S CHEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

May 12, 2023
Application Filed
Feb 26, 2026
Response after Non-Final Action
Aug 05, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
82%
With Interview (+5.2%)
2y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allowance rate.

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