DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The amendment filed on February 10th, 2026 has been acknowledged. By this amendment, claims 1, 13, and 18 have been amended. Accordingly, claims 1-20 are pending in the present application in which claims 1, 13, and 18 are in independent form. Applicant’s amendments to the title and the specification have been accepted. The drawings filed on February 10th, 2026 has been accepted.
New Grounds of Rejection
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 13, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (U.S. Pub. 2017/0263579) in view of Lin et al. (U.S. Pub. 2016/0013148).
In re claim 1, Hu ‘579 discloses a semiconductor package 200, comprising: an interposer comprising: a plurality of first redistribution layers comprising first electrical interconnect structures 30 having a first line width and a first line spacing embedded in a first dielectric material D30 (see paragraph [0014] and fig. 2), and wherein a second dielectric material D20 contacts the first dielectric material D30 (see paragraphs [0013], [0014] and fig. 2); and a plurality of second redistribution layers comprising second electrical interconnect structures 20 having a second line width and a second line spacing embedded in the second dielectric material D20 (see paragraph [0013] and fig. 2), wherein the second line width is greater than the first line width, and wherein the second line spacing is greater than the first line spacing (see paragraph [0015] and fig. 2).
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Hu ‘579 is silent to wherein the first dielectric material has a greater elasticity than a second dielectric material.
However, Lin discloses in a same field of endeavor, a semiconductor package, including, inter-alia, a semiconductor package, including, inter-alia, an interposer comprising a first redistribution layer comprising a first dielectric material 170, wherein the first dielectric material 170 has a greater elasticity than a second dielectric layer 174, and wherein the second dielectric material 174 contacts the first dielectric material 170 (see paragraph [0089] and fig. 7).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Lin into the semiconductor package of Hu ‘579 in order to enable wherein the first dielectric material has a greater elasticity than a second dielectric material in Hu ‘579 to be formed because in doing a more reliable semiconductor package with a build-up interconnect structure having increased strength and adhesion as well as reduced warpage can be obtain (see paragraph [0012] of Lin). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 13, Hu ‘579 discloses a semiconductor package 200, comprising: an interposer (upper portion of RDL2) comprising: a slab geometry comprising a first surface (upper surface) and a second surface (bottom surface); a plurality of first redistribution layers comprising first electrical interconnect structures 30 formed in a first dielectric material D30 proximate to the first surface (see paragraph [0014] and fig. 2); a plurality of second redistribution layers (lower portion of RLD2) comprising second electrical interconnect structures 20 formed in a second dielectric material D20 proximate to the second surface (see paragraph [0013] and fig. 2), and wherein the plurality of second redistribution layers further comprises a surface layer RDL1 comprising the first dielectric material D10 formed as an outmost layer of the plurality of second redistribution layers proximate to the second surface such that the surface layer RDL1 contacts electrical bonding pad structure (1L,2L) (see paragraphs [0012], [0013] and fig. 2) and partially surrounds the second electrical interconnect structures 20 (see paragraphs [0012], [0013] and fig. 2).
Hu ‘579 is silent to wherein the first dielectric material has greater elasticity than the second dielectric material.
However, Lin discloses in a same field of endeavor, a semiconductor package, including, inter-alia, a semiconductor package, including, inter-alia, an interposer comprising a first redistribution layer comprising a first dielectric material 170, wherein the first dielectric material 170 has a greater elasticity than a second dielectric layer 174, and wherein the second dielectric material 174 contacts the first dielectric material 170 (see paragraph [0089] and fig. 7).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Lin into the semiconductor package of Hu ‘579 in order to enable wherein the first dielectric material has greater elasticity than the second dielectric material in Hu ‘579 to be formed because in doing a more reliable semiconductor package with a build-up interconnect structure having increased strength and adhesion as well as reduced warpage can be obtain (see paragraph [0012] of Lin). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 18, Hu ‘579 discloses a method of forming an interposer, comprising: forming a plurality of first redistribution layers over a first carrier substrate (temporary carrier) (see paragraph [0020] and fig. 3A), the plurality of first redistribution layers comprising first electrical interconnect structures 10 having a first line width and a first line spacing embedded in a first dielectric material D10 (see paragraph 90020] and fig. 3B); and forming a plurality of second redistribution layers over the plurality of first redistribution layers, the plurality of second redistribution layers comprising second electrical interconnect structures 20 having a second line width and a second line spacing embedded in a second dielectric material D20 (see paragraph [0020] and figs. 3C, 3F, and 3G), wherein the second line width is greater than the first line width, and wherein the second line spacing is greater than the first line spacing (see paragraph [0020] and figs. 3C, 3F, and 3G).
Hu ‘579 is silent to wherein the first dielectric material has greater elasticity than the second dielectric material.
However, Lin discloses in a same field of endeavor, a semiconductor package, including, inter-alia, a semiconductor package, including, inter-alia, an interposer comprising a first redistribution layer comprising a first dielectric material 170, wherein the first dielectric material 170 has a greater elasticity than a second dielectric layer 174, and wherein the second dielectric material 174 contacts the first dielectric material 170 (see paragraph [0089] and fig. 7).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Lin into the semiconductor package of Hu ‘579 in order to enable wherein the first dielectric material has a greater elasticity than the second dielectric material in Hu ‘579 to be formed because in doing a more reliable semiconductor package with a build-up interconnect structure having increased strength and adhesion as well as reduced warpage can be obtain (see paragraph [0012] of Lin). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (U.S. Pub. 2017/0263579) in view of Lin et al. (U.S. Pub. 2016/0013148), as applied to claim 1 above, and further in view of Cho et al. (U.S. Pub. 2022/0108935).
In re claim 2, as applied to claim 1 above, Hu ‘579 and Lin are silent to wherein the first line width is between 1 micron and 5 microns; and the first line spacing is between 1 micron and 5 microns.
However, Cho discloses in a same field of endeavor, a semiconductor package, including, inter-alia, an interposer comprising: a plurality of first redistribution layers comprising first electrical interconnect structures 222a, 222b having a first line width and a first line spacing embedded in a first dielectric material 221, wherein the first line width is between 5 microns and 10 microns; and the first line spacing is between 5 microns and 10 microns (see paragraph [0065] and fig. 3B).
Therefore, it is respectfully submitted it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Cho into the semiconductor package of Hu ‘579 in order to optimize the first line width of the first electrical interconnect structures of Hu ‘579 to be about 5 microns and the first line spacing of the first electrical interconnect structures of Hu to be about 5 microns during routine experimentation since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges in achieving an optimum value of result effective variables involve only ordinary skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In re Boesch, 617 F.2nd 272, 205 USPQ 215 (CCPA 1980).
In re claim 3, as applied to claim 2 above, Hu ‘579 and Lin are silent to wherein: the second line width is between 8 microns and 50 microns; and the second line spacing with between 8 microns and 50 microns.
However, Cho discloses in a same field of endeavor, a semiconductor package, including, inter-alia, an interposer comprising a plurality of second redistribution layers comprising second electrical interconnect structures 212 having a second line width and a second line spacing embedded in a second dielectric material wherein: the second line width is between 7 microns and 20 microns; and the second line spacing with between 10 microns and 20 microns (see paragraph [0066]).
Therefore, it is respectfully submitted it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Cho into the semiconductor package of Hu ‘579 in order to optimize the second line width of the second electrical interconnect structures of Hu ‘579 to be about 20 microns and the second line spacing of the second electrical interconnect structures of Hu ‘579 to be about 20 microns during routine experimentation since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges in achieving an optimum value of result effective variables involve only ordinary skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In re Boesch, 617 F.2nd 272, 205 USPQ 215 (CCPA 1980).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (U.S. Pub. 2020/0035591) in view of Lin et al. (U.S. Pub. 2016/0013148), as applied to claim 1 above, and further in view of Furuichi et al. (U.S. Pub. 2017/0256482).
In re claim 4, as applied to claim 1 above, Hu ‘579 is silent to wherein: the first electrical interconnect structures comprise a first thickness that is between 1 micron to 5 microns; and the second electrical interconnect structures comprise a second thickness that is between 5 microns and 18 microns.
However, Furuichi discloses in a same field of endeavor, a semiconductor package, including, inter-alia, wherein the first electrical interconnect structures (41, 43) comprise a first thickness that is between 2 microns; and the second electrical interconnect structures 45 comprise a second thickness that 10 microns (see paragraph [0126]).
Therefore, it is respectfully submitted it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Furuichi into the semiconductor package of Hu ‘579 in order to optimize the first thickness of the first electrical interconnect structure of Hu ‘579 to be about 2 microns and the second thickness of the second electrical interconnect structure of Hu ‘579 to be about 10 microns during routine experimentation since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges in achieving an optimum value of result effective variables involve only ordinary skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In re Boesch, 617 F.2nd 272, 205 USPQ 215 (CCPA 1980).
Claim(s) 5-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (U.S. Pub. 2017/0263579) in view of Lin et al. (U.S. Pub. 2016/0013148), as applied to claim 1 above, and further in view of Muramatsu et al. (U.S. Pub. 2006/0272853).
In re claim 5, as applied to claim 1, Hu ‘579 and Lin disclose wherein: the first dielectric material comprises a first polymer (see paragraph [0083] of Lin) but are silent to wherein the second dielectric material comprises an inorganic particulate material dispersed in a second polymer.
However, Muramatsu discloses in a same field of endeavor, a semiconductor package, including, inter-alia, a second dielectric material comprises an inorganic particulate material dispersed in a second polymer wherein the second polymer comprises an epoxy resin; and the inorganic particulate material comprises a silica powder for adjustment of the dielectric constant or dielectric breakdown voltage (see paragraph [0129]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Muramatsu into the semiconductor package of Hu ‘579 in order to enable wherein the second dielectric material comprises an inorganic particulate material dispersed in a second polymer in Hu ‘579 to be formed in order to adjust of the dielectric constant or dielectric breakdown voltage (see paragraph [0129] of Muramatsu).
In re claim 6, as applied to claim 5 above, Hu ‘579 in combination with Lin and Muramatsu discloses wherein the plurality of first redistribution layers comprises two to six layers of the first electrical interconnect structures 30 embedded in the first dielectric material D30 (see paragraph [0014] and fig. 2 of Hu ‘579).
In re claim 7, as applied to claim 5 above, Hu ‘579 in combination with Lin and Muramatsu discloses wherein the plurality of second redistribution layers comprises four to eight layers of the second electrical interconnect structures 20 embedded in the second dielectric material D20 (see paragraph [0013] and fig. 2 of Hu ‘579).
In re claim 8, as applied to claim 5 above, Hu ‘579 in combination with Lin and Muramatsu discloses wherein the first polymer comprises one of polyimide (PI), benzocyclobutene (BCB), or polybenzo-bisoxazole (PBO) (see paragraphs [0070], [0083] of Lin).
In re claim 9, as applied to claim 5 above, Hu ‘579 in combination with Lin and Muramatsu discloses wherein the second polymer comprises an epoxy resin; and the inorganic particulate material comprises a silica powder (see paragraph [0129] of Muramatsu).
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (U.S. Pub. 2017/0263579) in view of Lin et al. (U.S. Pub. 2016/0013148) and Muramatsu et al. (U.S. Pub. 2006/0272853), as applied to claim 5 above, and further in view of Hu (U.S. Pub. 2020/0035591).
In re claim 10, as applied to claim 5 above, Hu ‘579, Lin and Muramatsu are silent to wherein the semiconductor package further comprising a semiconductor die electrically connected to the interposer, wherein the first electrical interconnect structures are electrically connected to the second electrical interconnect structures such that the interposer comprises a slab geometry having a first surface and a second surface that is parallel to the first surface, wherein the first surface comprises electrical micro-bump structures electrically connected to the first electrical interconnect structures of the of the plurality of first redistribution layers, wherein the second surface comprises electrical bonding pad structures electrically connected to the second electrical interconnect structures of the plurality of second redistribution layers, and wherein the semiconductor die is electrically connected to the electrical micro-bump structures.
However, Hu ‘591 discloses in a same field of endeavor, a semiconductor package, including, inter-alia, a semiconductor die 10 electrically connected to the interposer IP1, wherein the first electrical interconnect structures FP are electrically connected to the second electrical interconnect structures CP such that the interposer IP1 comprises a slab geometry having a first surface and a second surface that is parallel to the first surface, wherein the first surface comprises electrical micro-bump structures 12 electrically connected to the first electrical interconnect structures FP of the of the plurality of first redistribution layers 110, wherein the second surface comprises electrical bonding pad structures BP2 electrically connected to the second electrical interconnect structures CP of the plurality of second redistribution layers 140, and wherein the semiconductor die 10 is electrically connected to the electrical micro-bump structures 12 (see paragraphs [0022], [0030], [0031], [0032] and figs. 2-4).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Hu ’591 into the semiconductor package of Hu ‘579 in order to enable a semiconductor die electrically connected to the interposer, wherein the first electrical interconnect structures are electrically connected to the second electrical interconnect structures such that the interposer comprises a slab geometry having a first surface and a second surface that is parallel to the first surface, wherein the first surface comprises electrical micro-bump structures electrically connected to the first electrical interconnect structures of the of the plurality of first redistribution layers, wherein the second surface comprises electrical bonding pad structures electrically connected to the second electrical interconnect structures of the plurality of second redistribution layers, and wherein the semiconductor die is electrically connected to the electrical micro-bump structures in Hu ‘579 to be formed in order to minimize a noise between operations and to improve a signal performance (see paragraph [0009] of Hu ‘591).
In re claim 11, as applied to claim 10 above, Hu ‘579 in combination with Lin, Muramatsu, and Hu ‘591 discloses wherein the semiconductor package further comprising a protective layer 130 comprising the second dielectric material formed over the first surface such that the protective layer 130 is formed over the plurality of first redistribution layers 110 and partially surrounds the electrical micro-bump structures 12 (see paragraphs [0023], [0032] and figs. 3-4 of Hu ‘591).
In re claim 12, as applied to claim 10 above, Hu ‘579 in combination with Lin, Muramatsu, and Hu ‘591 discloses wherein the plurality of second redistribution layers further comprises a surface layer RDL1 comprising the first dielectric material D10 formed proximate to the second surface of the interposer such that the surface layer RDL1 partially surrounds the electrical bonding pad structures (1L,2L) (see paragraphs [0012], [0013] and fig. 2 of Hu ‘579).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (U.S. Pub. 2017/0263579) in view of Lin et al. (U.S. Pub. 2016/0013148), as applied to claim 13 above, and further in view of Muramatsu et al. (U.S. Pub. 2006/0272853) and Cho et al. (U.S. Pub. 2022/0108935).
In re claim 14, as applied to claim 13 above, Hu ‘579 in combination with Lin discloses wherein the first dielectric material comprises a first polymer that is one of polyimide (PI), benzocyclobutene (BCB), or polybenzo-bisoxazole (PBO) (see paragraphs [0070], [0083] of Lin) but are silent to wherein the second dielectric material comprises an inorganic particulate material dispersed in an epoxy resin and wherein the plurality of first redistribution layers comprise a first line width is between 1 micron and 5 microns and a first line spacing is between 1 micron and 5 microns; the plurality of second redistribution layers comprise a second line width is between 8 microns and 50 microns and a second line spacing that is between 8 microns and 50 microns.
However, Muramatsu discloses in a same field of endeavor, a semiconductor package, including, inter-alia, a second dielectric material comprises an inorganic particulate material dispersed in a second polymer wherein the second polymer comprises an epoxy resin; and the inorganic particulate material comprises a silica powder for adjustment of the dielectric constant or dielectric breakdown voltage (see paragraph [0129]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Muramatsu into the semiconductor package of Hu ‘579 in order to enable wherein the second dielectric material comprises an inorganic particulate material dispersed in an epoxy resin in Hu ‘579 to be formed in order to adjust of the dielectric constant or dielectric breakdown voltage (see paragraph [0129] of Muramatsu).
Hu ‘579, Lin, and Muramatsu are silent to wherein the plurality of first redistribution layers comprise a first line width is between 1 micron and 5 microns and a first line spacing is between 1 micron and 5 microns; the plurality of second redistribution layers comprise a second line width is between 8 microns and 50 microns and a second line spacing that is between 8 microns and 50 microns
However, Cho discloses in a same field of endeavor, a semiconductor package, including, inter-alia, an interposer comprising: a plurality of first redistribution layers comprising the first line width is between 5 microns and 10 microns; and the first line spacing is between 5 microns and 10 microns (see paragraph [0065] and fig. 3B) and a plurality of second redistribution layers comprising the second line width is between 7 microns and 20 microns; and the second line spacing with between 10 microns and 20 microns (see paragraph [0066]).
Therefore, it is respectfully submitted it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Cho into the semiconductor package of Hu ‘579 in order to optimize the first line width of the plurality of first redistribution layers of Hu ‘579 to be about 5 microns and the first line spacing of the plurality of first redistribution layers of Hu ‘579 to be about 5 microns and the second line width of the plurality of second redistribution layers of Hu ‘579 to be about 20 microns and the second line spacing of the plurality of second redistribution layers of Hu ‘579 to be about 20 microns during routine experimentation since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges in achieving an optimum value of result effective variables involve only ordinary skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In re Boesch, 617 F.2nd 272, 205 USPQ 215 (CCPA 1980).
Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (U.S. Pub. 2017/0263579) in view of Lin et al. (U.S. Pub. 2016/0013148), Muramatsu et al. (U.S. Pub. 2006/0272853), and Cho et al. (U.S. Pub. 2022/0108935), as applied to claim 14 above, and further in view of Hu (U.S. Pub. 2020/0035591).
In re claim 15, as applied to claim 14 above, Hu ‘579, Lin, Muramatsu, and Cho are silent to wherein the semiconductor package further comprising a semiconductor die, wherein: the first surface comprises electrical micro-bump structures electrically connected to the first electrical interconnect structures of the of the plurality of first redistribution layers; the second surface comprises electrical bonding pad structures electrically connected to the second electrical interconnect structures of the plurality of second redistribution layers; and the semiconductor die is electrically connected to the electrical micro-bump structures.
However, Hu ‘591 discloses in a same field of endeavor, a semiconductor package, including, inter-alia, a semiconductor die 10, wherein: the first surface comprises electrical micro-bump structures 12 electrically connected to the first electrical interconnect structures FP of the of the plurality of first redistribution layers 110 (see paragraph [0019] and figs. 1A-E and 2-4); the second surface comprises electrical bonding pad structures BP2 electrically connected to the second electrical interconnect structures CP of the plurality of second redistribution layers 140 (see paragraph [0025] and figs. 1A-E and 2-4); and the semiconductor die 10 is electrically connected to the electrical micro-bump structures 12 (see paragraph [0032] and figs. 1A-E and 2-4).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Hu ’591 into the semiconductor package of Hu ‘579 in order to enable a semiconductor die, wherein: the first surface comprises electrical micro-bump structures electrically connected to the first electrical interconnect structures of the of the plurality of first redistribution layers; the second surface comprises electrical bonding pad structures electrically connected to the second electrical interconnect structures of the plurality of second redistribution layers; and the semiconductor die is electrically connected to the electrical micro-bump structures in Hu ‘579 to be formed in order to minimize a noise between operations and to improve a signal performance (see paragraph [0009] of Hu ‘591).
In re claim 16, as applied to claim 15 above, Hu ‘579 in combination with Lin, Muramatsu, Cho, and Hu ‘591 discloses wherein the semiconductor package further comprising a protective layer 230 comprising the second dielectric material formed over the first surface such that the protective layer is formed over the plurality of first redistribution layers 110 and partially surrounds the electrical micro-bump structures 12 (see paragraphs [0032], [0034] and figs. 1A-E and 2-4 of Hu ‘591).
In re claim 17, as applied to claim 15 above, Hu ‘579 in combination with Lin, Muramatsu, Cho, and Hu ‘591 discloses wherein the semiconductor package further comprising a package substrate 150 electrically connected to the electrical bonding pad BP2 structures of the interposer IP1 (see paragraph [0030] and figs. 1A-E and 2-4 of Hu ‘591).
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (U.S. Pub. 2017/0263579) in view of Lin et al. (U.S. Pub. 2016/0013148), as applied to claim 18 above, and further in view of Hu (U.S. Pub. 2020/0035591) and Muramatsu et al. (U.S. Pub. 2006/0272853).
In re claim 19, as applied to claim 18 above, Hu ‘579 and Lin are silent to wherein the method further comprising forming a plurality of electrical bonding pad structures that are electrically connected to the second electrical interconnect structures of the plurality of second redistribution layers; attaching a second carrier substrate over the plurality of electrical bonding pad structures and removing the first carrier substrate; and forming electrical micro-bump structures that are electrically connected to the first electrical interconnect structures of the plurality of first redistribution layers, wherein forming the plurality of first redistribution layers further comprises embedding the first electrical interconnect structures in one of polyimide (PI), benzocyclobutene (BCB), or polybenzo-bisoxazole (PBO), and wherein forming the plurality of second redistribution layers further comprises embedding the second electrical interconnect structures in an inorganic particulate material dispersed in an epoxy resin.
However, Hu ‘591 disclsoes in a same field of endeavor, a semiconductor package, including, inter-alia, the steps of forming a plurality of electrical bonding pad structures BP2 that are electrically connected to the second electrical interconnect structures CP of the plurality of second redistribution layers 140 (see paragraph [0030] and figs. 2-4); attaching a second carrier substrate 150 over the plurality of electrical bonding pad structures BP2 and removing the first carrier substrate 50 (see paragraph [0030] and figs. 2E and 2-4); and forming electrical micro-bump structures 12 that are electrically connected to the first electrical interconnect structures FP of the plurality of first redistribution layers 110 (see paragraph [0032] and figs. 2-4), wherein forming the plurality of first redistribution layers 110 further comprises embedding the first electrical interconnect structures FP in one of polyimide (PI), benzocyclobutene (BCB), or polybenzo-bisoxazole (PBO) (see paragraph [0019] and figs.1A-E and 2-4), and wherein forming the plurality of second redistribution layers 140 further comprises embedding the second electrical interconnect structures CP in a dielectric layer CD (see paragraph [0025] and fig. 1D).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Hu ’591 into the semiconductor package of Hu ‘579 in order to enable the steps of forming a plurality of electrical bonding pad structures that are electrically connected to the second electrical interconnect structures of the plurality of second redistribution layers; attaching a second carrier substrate over the plurality of electrical bonding pad structures and removing the first carrier substrate; and forming electrical micro-bump structures that are electrically connected to the first electrical interconnect structures of the plurality of first redistribution layers, wherein forming the plurality of first redistribution layers further comprises embedding the first electrical interconnect structures in one of polyimide (PI), benzocyclobutene (BCB), or polybenzo-bisoxazole (PBO), and wherein forming the plurality of second redistribution layers further comprises embedding the second electrical interconnect structures in a dielectric layer in Hu ‘579 to be formed in order to minimize a noise between operations and to improve a signal performance (see paragraph [0009] of Hu ‘591).
Hu ‘579, Lin, and Hu ‘591 are silent to wherein the dielectric layer is an inorganic particulate material dispersed in an epoxy resin.
However, Muramatsu discloses in a same field of endeavor, a semiconductor package, including, inter-alia, a second dielectric material comprises an inorganic particulate material dispersed in a second polymer wherein the second polymer comprises an epoxy resin; and the inorganic particulate material comprises a silica powder for adjustment of the dielectric constant or dielectric breakdown voltage (see paragraph [0129]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Muramatsu into the semiconductor package of Hu in order to enable wherein the dielectric layer comprises an inorganic particulate material dispersed in an epoxy resin in Hu ‘579 to be formed in order to adjust of the dielectric constant or dielectric breakdown voltage (see paragraph [0129] of Muramatsu).
In re claim 20, as applied to claim 19 above, Hu ‘579 in combination with Lin, Hu ‘591, and Muramatsu discloses wherein the method further comprising: forming a protective layer 230, comprising the second dielectric material, over the plurality of first redistribution layers 110 such that the protective layer 230 partially surrounds the electrical micro-bump structures 12 (see paragraph [0034] and figs. 1A-E and 2-4); and forming a surface layer, comprising the first dielectric material, over the plurality of second redistribution layers 140 such that the surface layer partially surrounds the plurality of electrical bonding pad structures BP2 (see paragraphs [0025], [0030] and figs. 1A-E and 2-4 of Hu ‘591).
Response to Applicant’s Amendment and Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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