DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 11/30/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-8, 10-11, 13-15, and 21-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gaul et al. (U.S. Publication No. 2023/0093343 A1; hereinafter Gaul)
With respect to claim 1, Gaul discloses a method for forming a semiconductor device structure, comprising: forming a fin structure [170/207] over a substrate [110]; forming a nitrogen-containing protective layer [190] (converts to [195] after processing) over a top and sidewalls of the fin structure (See Figure 8 and ¶[0058]); forming a dummy gate electrode [150] over the nitrogen-containing protective layer; forming a spacer element [160] over a sidewall of the dummy gate electrode; forming a dielectric layer [250] surrounding the dummy gate electrode (see Figure 12); removing the dummy gate electrode to form a trench [260] exposing the nitrogen-containing protective layer (See Figure 14); partially removing the nitrogen-containing protective layer to expose the fin structure (See Figure 14; [197] is remnant of processing [190]); and forming a metal gate stack [280] wrapped around the fin structure (see Figure 16 and ¶[0099]).
With respect to claim 5, Gaul discloses wherein the fin structure comprises a plurality of sacrificial layers [207] and a plurality of semiconductor layers [180] laid out alternately (see Figure 8).
With respect to claim 6, Gaul discloses removing the sacrificial layers after the partial removal of the nitrogen-containing protective layer and before the formation of the metal gate stack (See Figure 14), wherein remaining portions of the semiconductor layers form a plurality of semiconductor nanostructures (See ¶[0075-0076]), and the metal gate stack is wrapped around each of the semiconductor nanostructures after the formation of the metal gate stack (See Figure 16).
With respect to claim 7, Gaul discloses wherein the spacer element has a higher atomic concentration of carbon than that of the nitrogen-containing protective layer (see ¶[0042] and ¶[0058]; SiCN spacer vs hafnium silicon oxynitride (HfSiON) nitrogen-containing protective layer).
With respect to claim 8, Gaul discloses wherein the spacer element has an atomic concentration of nitrogen that is equal to or lower than that of the nitrogen-containing protective layer (see ¶[0042] and ¶[0058]; SiON spacer vs hafnium silicon oxynitride (HfSiON) nitrogen-containing protective layer).
With respect to claim 10, Gaul discloses wherein the metal gate stack is formed to be in direct contact with the nitrogen-containing protective layer and the spacer element (See Figure 16).
With respect to claim 11, Gaul discloses a method for forming a semiconductor device structure, comprising: forming a fin structure [170/207] over a substrate [110]; forming a protective layer [190] over a top and sidewalls of the fin structure (See Figure 8 and ¶[0058]); forming a dummy gate electrode [150] over the protective layer, wherein the fin structure is covered by the protective layer and is prevented from being etched during the formation of the dummy gate electrode (See Figure 8); forming a spacer element [160] over a sidewall of the dummy gate electrode; removing the dummy gate electrode to form a trench [260] exposing the protective layer and an interior sidewall of the spacer element (See Figure 14); partially removing the protective layer to expose the fin structure (See Figure 14; [197] is remnant of processing [190]); and forming a metal gate stack [280] wrapped around the fin structure (see Figure 16 and ¶[0099]).
With respect to claim 13, Gaul discloses wherein the protective layer comprises nitrogen, carbon, or a combination thereof (See ¶[0058]).
With respect to claim 14, Gaul discloses wherein the fin structure comprises a plurality of sacrificial layers [207] and a plurality of semiconductor layers [180] laid out alternately, and the method further comprises: removing the sacrificial layers after the partial removal of the protective layer and before the formation of the metal gate stack (See Figure 14), wherein remaining portions of the semiconductor layers form a plurality of semiconductor nanostructures (See ¶[0075-0076]), and the metal gate stack is wrapped around each of the semiconductor nanostructures after the formation of the metal gate stack (See Figure 16).
With respect to claim 15, Gaul discloses wherein the protective layer is formed to be in direct contact with a topmost semiconductor nanostructure of the semiconductor nanostructures (See Figure 16).
With respect to claim 21, Gaul discloses a method for forming a semiconductor device structure, comprising: forming a semiconductor protruding structure [170/207]; forming a protective layer [190] over the semiconductor protruding structure, wherein the protective layer contains nitrogen (See Figure 8 and ¶[0058]; HfSiON); forming a dummy gate electrode [150] over the protective layer (see Figure 5; [190] is positioned below [150]); forming a spacer element [160] over a sidewall of the dummy gate electrode, wherein the spacer element has an atomic concentration of nitrogen that is equal to or lower than that of the protective layer (see ¶[0042] and ¶[0058]; SiCN spacer vs hafnium silicon oxynitride (HfSiON) nitrogen-containing protective layer); removing the dummy gate electrode (see Figure 13); partially removing the protective layer to partially expose the semiconductor protruding structure (See Figure 14; [197] is remnant of processing [190]); and forming a metal gate stack [280] over the semiconductor protruding structure (See Figure 16 and ¶[0099]).
With respect to claim 22, Gaul discloses wherein the spacer element has a higher atomic concentration of carbon than that of the protective layer (see ¶[0042] and ¶[0058]; SiCN spacer vs hafnium silicon oxynitride (HfSiON) nitrogen-containing protective layer).
With respect to claim 23, Gaul discloses wherein the protective layer is formed to have a portion gradually becomes thicker along a direction toward the metal gate stack (see Figure 14).
With respect to claim 24, Gaul discloses forming an epitaxial structure [220/230] beside the semiconductor protruding structure, wherein a first interface between the epitaxial structure and the semiconductor protruding structure connects a second interface between the epitaxial structure and the protective layer (see Figure 11).
With respect to claim 25, Gaul discloses wherein the protective layer is formed to have a curved top surface (see Figure 8, protective layer curves around edges).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gaul in view of Chen et al. (U.S. Publication No. 2022/0352313 A1; hereinafter Chen)
With respect to claim 2, Gaul fails to disclose partially removing the spacer element so that the trench becomes wider.
In the same field of endeavor, Chen teaches removing the spacer element so that the trench becomes wider (See Chen Figures 15B-C). Widening of the trench to reduce or prevent formation of voids or seams when forming replacement gate structures (see Chen ¶[0062]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 3, the combination of Gaul and Chen discloses wherein the partial removal of the spacer element and the partial removal of the nitrogen-containing protective layer are performed simultaneously (see Gaul Figures 13-14).
With respect to claim 4, the combination of Gaul and Chen discloses wherein the partial removal of the spacer element and the partial removal of the nitrogen-containing protective layer are performed using an etching process, and the etching process comprises a plurality of dry etching operations and a plurality of wet etching operations (See Gaul ¶[0090])
With respect to claim 12, Gaul fails to disclose partially removing the spacer element from the interior sidewall of the spacer element while the protective layer is partially removed.
In the same field of endeavor, Chen teaches partially removing the spacer element from the interior sidewall of the spacer element while the protective layer is partially removed. (See Chen Figures 15B-C). Widening of the trench to reduce or prevent formation of voids or seams when forming replacement gate structures (see Chen ¶[0062]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gaul.
With respect to claim 9, Gaul fails to explicitly disclose wherein the fin structure is covered by the nitrogen-containing protective layer during the formation of the dummy gate electrode (i.e., simultaneously processed), however does disclose the formation of the dummy gate electrode to finalize the overall dummy gate structure of the device (See Figure 5). It has been held that “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results” See In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that absent any unexpected or new results, none of which are disclosed by the Applicant, the fin structure covering both the dummy electrode and the fins simultaneously can be considered functionally equivalent to during the formation of the dummy gate electrode as the limitations of the claim do not require simultaneous processing but rather within the processing of the dummy gate electrode.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818