DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of claims 1-14, 21-26 in the reply filed on 09/30/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/11/24 was filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-10, 21-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., U.S. Patent No. 12057449.
Regarding claim 1, Chen discloses:
A method of manufacturing a semiconductor device, comprising:
forming an isolation structure (shallow trench isolation 120) in a substrate 106 (Fig. 1A);
forming a first active region on a first side of the isolation structure (Fig. 1A, 107a, 108a, fins are active col 3 lines 20-23);
forming a first plurality of primary polysilicon structures over the first active region 112A-112B (Fig. 1A), the structures each having a first contacted polysilicon pitch (CPP) (note that every polysilicon layer has a contacted pitch, col 9 lines 10-28);
forming a second polysilicon structure (112C-112F; Fig. 1A, see col 9 lines 10-28 describing multiple polysilicon gate structures formed) over the isolation structure, the secondary polysilicon structure being parallel to the primary polysilicon structures.
Regarding claim 2, Chen discloses forming a secondary polysilicon structure having a second contacted polysilicon pitch (it is inherent that every polysilicon layer has a pitch).
Regarding claim 4, Chen discloses spacing the second plurality of secondary polysilicon structures whereby the first contacted polysilicon pitch and the second contacted polysilicon pitch are equal (Fig. 1A: the pitch spacing between 112A-112B is the same as the pitch spacing between 112C-112F).
Regarding claims 5-7, Chen discloses removing one of the second plurality of secondary polysilicon structure to form an opening, and filling the opening with a conductive material/metal/polysilicon/insulation (Fig. 1C, removed structures 112D-112E to form a hole 104 and filled the hole and the polysilicon studs to be removed can be called as primary polysilicon structures or secondary polysilicon structures and the openings formed after removing process can be called as primary opening, secondary openings, or third openings; Fig. 1C, Fig. 10B).
Regarding claim 8, Chen discloses removing a first secondary polysilicon structure to form an opening, wherein the opening is formed between a second polysilicon structure and a third secondary polysilicon structure, filling the opening with conductive material 122, establish an electrical contact to the conductive material (Fig. 7H, Fig. 10B).
Regarding claim 9, Chen discloses forming the polysilicon structure comprises patterning and etching the polysilicon structure to form secondary polysilicon structures (Figs. 3A-3B).
Regarding claim 10, Chen discloses (lines 10-28, Col. 9):
removing the first plurality of primary polysilicon structure to form a plurality of primary openings (112A-112BD; Figs. 3A-3D),
removing the second plurality of secondary polysilicon structures to form a plurality of secondary openings (112CE-112F), and
filling the plurality of primary openings and the plurality of secondary openings with a conductive structure (Figs. 3A-3D).
Regarding claim 21, Chen discloses a method:
forming an isolation structure (shallow trench isolation 120) in a substrate 106 (Fig. 1A);
forming an active region in the substrate (Fig. 1A, 107a, 108a, fins are active col 3 lines 20-23),
forming a first plurality of polysilicon structures over the active region (112A-112B; Fig. 1A),
forming a second plurality of polysilicon structures over the isolation structure (112C-112F; Fig. 1A, see col 9 lines 10-28 describing multiple polysilicon gate structures formed),
removing each of the first plurality of polysilicon structures to form a first plurality of openings, wherein at least one of the first plurality of openings exposes the active region (112A-112BD; Figs. 3A-3D; when the polysilicon material is removed there would be a void/hole until some materials are filled, and since it was on the active layer, there would be some exposure, before the new gates were formed), and
forming a plurality of gate structures, wherein each gate structure of the plurality of gate structures is in a corresponding opening of the first plurality of openings (Figs. 3A-3D).
Regarding claim 22, Chen discloses that maintaining the second polysilicon structure during removing the first (Figs. 1B-1E).
Regarding claim 23, Chen discloses removing the second plurality of polysilicon structures to form a plurality of second openings, wherein at least one of the plurality of second openings exposes the isolation structure (Figs. 3A-3D, Col. 9, lines 10-28).
Regarding claims 24-25, Chen discloses removing the second polysilicon structure simultaneously with removing the first and filling the opening with dielectric (Figs. 1(s)-3(s)).
Regarding claim 26, Chen discloses forming a dielectric layer over the structures and forming a pliurality of contacts extending through the dielectric wherein each of the contact connected to a gate of the plurality of gate structures (Figs. 1K-1M).
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cucci et al., U.S. Pub. No. 2022/0173211.
Regarding claim 1, Cucci discloses:
A method of manufacturing a semiconductor device, comprising:
forming an isolation structure 22 in a substrate 12 (Fig. 4);
forming a first active region on a first side of the isolation structure (Fig. 4);
forming a first plurality of primary polysilicon structure 26b (Fig. 5, the gate studs on one side of the layer 24, paragraph 33), the structures each having a first contacted polysilicon pitch (CPP) (note that all polysilicon studs have a contacted pitch);
forming a second polysilicon structure (the gate 30 or the polysilicon structure 26b that would also be on the right side of the layer 24) over the isolation structure, the secondary polysilicon structure being parallel to the primary polysilicon structures.
Regarding claim 2, Cucci discloses forming a secondary polysilicon structure having a second contacted polysilicon pitch (it is inherent that all polysilicon studs have a pitch).
Regarding claim 3, Cucci discloses wherein forming the second plurality of secondary polysilicon structures further comprises spacing the second plurality of secondary polysilicon structures whereby the first contacted polysilicon pitch and the second contacted polysilicon pitch are different (Fig. 8, the first polysilicon pitch (on right side of layer 24) and the second polysilicon pitch (on left side of layer 24) are different (Figs. 5-6).
Allowable Subject Matter
Claims 11-14 are allowed. The following is an examiner’s statement of reason for allowance: None of the references of record teaches or suggests the claimed having a method of forming a semiconductor device, among other limitations cited in claim 11, removing the first plurality of primary polysilicon structures to form a first plurality of openings, removing the second plurality of secondary polysilicon structures to form a second plurality of openings, filling the primary and secondary openings with a conductive material, removing the conductive material from the second plurality of opening to form a third plurality of openings and filling the third openings with a dielectric material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818