DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 13 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 13 and 23, the term "metal-like" renders the claim(s) indefinite because the claim(s) include(s) elements not actually disclosed (those encompassed by "like"), thereby rendering the scope of the claim(s) unascertainable. See MPEP § 2173.05(d).
As understood by the Examiner, metal has many properties, including electrical and thermal conductivity, opacity, and density among others. Materials such as heavily doped polysilicon may have conductive properties similar to metal, and materials such as glass may have physical properties similar to metal. Therefore, the meaning of metal-like is unclear, rendering the scope of claim 23 indefinite.
For the purposes of compact prosecution, the Examiner has interpreted claims 13 and 23 to mean:
13. (Original) The IC of claim 11, further comprising:
first through seventh metal defined (MD) segments extending in the second direction and overlying each of the first through fourth active areas…
23. The IC driver of claim 21, wherein each of the cascode arrangement of p-type transistors and the cascode arrangement of n-type transistors further comprises:
a first metal defined segment between the third via and the source node; and
a second metal defined segment between the fourth via and the drain node.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 9-10, 21 and 23-35 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (PG Pub. No. US 2020/0105739 A1).
Regarding claim 1, Yang teaches an integrated circuit (IC) driver (fig. 6) comprising:
a cascode arrangement (¶ 0045 & figs. 3B, 6: 100p, including transistors MP2 and MP4 in cascode configuraion) of first-type transistors (Mp2 and MP4 are p-type transistors) coupled in series with a cascode arrangement (fig. 6: 100p coupled in series with 100n) of second-type transistors (n-type transistors Mn2, Mn4), the second type being different from the first type (n-type different conductivity than p-type),
wherein each of the cascode arrangement (figs. 1, 2B & 3B: 100, analogous to 100p and 100n of fig. 6) of first-type transistors and the cascode arrangement of second-type transistors comprises:
an active area (¶ 0022 & figs. 1A, 9A: 50) extending in a first direction (fig. 1: 50 extends in X-direction);
a plurality of gate structures (¶ 0023: 41, including 41A-41D) extending in a second direction perpendicular to the first direction and overlying the active area at locations corresponding to the transistors of the cascode arrangement (figs. 1A, 9C: 41 extend in Y-direction);
first through fourth metal segments (left, right portions of 90, 91, and 94) extending in the first direction in a first metal layer of the IC (figs. 1A, 9D: 90/91/94 extend in X-direction);
first and second vias (¶ 0026: 1st and 2nd VG) configured to electrically couple respective first and second gate structures of the plurality of gate structures to the first and second metal segments, respectively (figs. 1A, 5A: vias VG connect 41A and 41D to left/right portions of 90);
a third via (¶ 0028: 1st VD) configured to electrically couple a source terminal of the cascode arrangement to the third metal segment (¶ 0027, figs. 1A, 5A: 1st VD connects source terminal to 91); and
a fourth via (¶ 0028: 2nd VD) configured to electrically couple a drain terminal of the cascode arrangement to the fourth metal segment (¶ 0028, figs. 1A, 5A: 2nd VD connects drain terminal to 94),
wherein the third and fourth metal segments are aligned along the first direction (fig. 1A: 91 and 94 aligned along X-direction).
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Regarding claim 3, Yang teaches the IC driver of claim 1, wherein the source terminal of each of the cascode arrangement of first-type transistors and the cascode arrangement of second-type transistors is a first source terminal of the corresponding first-type or second-type transistor cascode arrangement (¶ 0027 & fig. 1A: 80 connected to source region of either 100p or 100n), and each of the cascode arrangement of first-type transistors and the cascode arrangement of second-type transistors further comprises:
a fifth metal segment (¶ 0033: 92) aligned with the third and fourth metal segments along the first direction (fig. 6: 92 aligned with 91 and 94); and
a fifth via (3rd VD) configured to electrically couple a second source terminal of the cascode arrangement to the fifth metal segment (figs. 2A, 2B and/or 6: 3rd VD electrically couples a source terminal of 100p or 100n to 92).
Regarding claim 4, Yang teaches the IC driver of claim 1, wherein each of the cascode arrangement of first-type transistors and the cascode arrangement of second-type transistors further comprises:
a fifth via (¶ 0026: 3rd VG) configured to couple a third gate structure (additional gate structure such as 41B or 41C) of the plurality of gate structures to the first metal segment (fig. 1A: 41C electrically coupled to left portion of 90),
wherein the locations at which the first and third gate structures (1st gate=antecedent?) of the plurality of gate structures overlie the active area correspond to parallel configurations of the corresponding transistors of the cascode arrangement (fig. 1A: 41D, 41C overlie active region of 100p or 100n).
Regarding claim 5, Yang teaches the IC driver of claim 1, wherein the cascode arrangement of first- type transistors and the cascode arrangement of second-type transistors further comprises:
a fifth metal segment aligned with the first metal segment along the first direction (see annotated fig. 6 below: third portion of 90); and
a fifth via (VG) configured to couple a third gate structure (41B) of the plurality of gate structures to the fifth metal segment (fig. 6: VG couples 41B to third portion of 90).
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Regarding claim 6, Yang teaches the IC driver of claim 1, wherein, for each of the cascode arrangement of first-type transistors and the cascode arrangement of second-type transistors (100p, 100n):
the active area is a first active area of the corresponding cascode arrangement (figs. 1A, 6: active area of Mp2 or Mn4),
the locations corresponding to the transistors of the cascode arrangement are first locations corresponding to first transistors of the cascode arrangement (Mp2 or Mn4),
the cascode arrangement further comprises a second active area extending in the first direction (figs. 1A, 6: active area of Mp4 or Mn2), and
the plurality of gate structures overlies the second active area at second locations corresponding to second transistors of the cascode arrangement configured in parallel with the first transistors of the cascode arrangement (figs. 1A, 6: 41A-41D overlie active regions of Mn1-4 and MP1-4, which are arranged in parallel).
Regarding claim 7, Yang teaches the IC driver of claim 6, wherein each of the cascode arrangement of first-type transistors and the cascode arrangement of second-type transistors (100, 100p/100n) further comprises:
fifth and sixth metal segments (figs. 1A, 6: 92, 95 and/or 99 of 100p or 100n) aligned along the first direction in the first metal layer (fig. 1A: 92, 94 and 99 aligned along X-direction and formed from metal of 91/94);
a fifth via (additional VD) configured to electrically couple the source terminal of the cascode arrangement to the fifth metal segment (¶ 0027 & figs. 1A, 6: source terminal of 100p or 100n coupled supply voltage trough VD); and
a sixth via (additional VD) configured to electrically couple the drain terminal of the cascode arrangement to the sixth metal segment (¶ 0028 & figs. 1A, 6: drain terminal of 100p or 100n coupled supply voltage trough VD).
Regarding claim 9, Yang teaches the IC driver of claim 1, wherein, for at least one of the cascode arrangement of first-type transistors or the cascode arrangement of second-type transistors, the third and fourth metal segments are separated by a distance corresponding to a cut-metal operation of a manufacturing process corresponding to the IC (¶ 0053, fig. 1A: 91 and 94 comprise cut portions of a metal routing line).
Regarding claim 10, Yang teaches the IC driver of claim 1, wherein the first-type and second-type transistors comprise p-type and n-type metal oxide semiconductor (PMOS and NMOS) transistors, respectively (¶ 0045: 100p comprises p-type transistors Mp2 & Mp4, 100n comprises n-type transistors MN2 and MN4),
the source terminal of the cascode arrangement of first-type transistors is electrically coupled to a power supply node of the IC driver (fig. 6: source terminal of Mp2 connected to supply voltage),
the source terminal of the cascode arrangement of second-type transistors is electrically coupled to a reference node of the IC driver (fig. 6: source terminal of Mn2 connected to ground), and
each of the drain terminal of the cascode arrangement of first-type transistors and the drain terminal of the cascode arrangement of second-type transistors is electrically coupled to an output node of the IC driver (fig. 6: drain terminals of Mp4 and Mn4 connected to Vout).
Regarding claim 21, Yang teaches an integrated circuit (IC) driver (¶ 0045 & fig. 6: 600) comprising:
a power supply node (fig. 6: top node of Mp2 connected to supply voltage);
a reference node (bottom node of Mn2 connected to ground);
an output node (¶ 0048 & fig. 6: Vout);
a cascode arrangement of p-type transistors (¶ 0038, figs. 3A-3B, 6: circuit 100p, including p-type transistors Mp2 and Mp4) coupled between the power supply node and the output node (fig. 6: 100p coupled between supply voltage and Vout); and
a cascode arrangement of n-type transistors (¶ 0037, figs. 2A-2B, 6: circuit 100n, including n-type transistors Mn2 and Mn4) coupled between the output node and the reference node (fig. 6: 100n coupled between Vout and ground),
wherein each of the cascode arrangement of p-type transistors and the cascode arrangement of n-type transistors (100/100p/100n) comprises:
an active area (¶ 0022 & figs. 1A, 9A: 50) extending in a first direction and comprising a source node and a drain node (¶¶ 0027-0028, fig. 1A: 50 extends in X-direction and comprises source and drain nodes);
a plurality of gate structures (¶ 0023: group of gate strips 41) extending in a second direction perpendicular to the first direction and overlying the active area at locations corresponding to the transistors of the cascode arrangement (fig. 1A: 41 extend in Y-direction and overlies 50 at locations corresponding to Mp2/Mp4 and Mn2/Mn4);
first and second metal segments (¶ 0026: portions of metal routing 90) extending in the first direction in a first metal layer of the IC (fig. 1A: portions of metal routing 90 extend in X-direction);
first and second vias (¶ 0026: VG) configured to electrically couple first and second gate structures of the plurality of gate structures to the respective first and second metal segments (fig. 1A: VG electrically couples each 41 to respective portions of 90);
a third metal segment (¶ 0036, fig. 1A: 94) extending in the first direction in the first metal layer of the IC (¶ 0053, fig. 1A: 94 comprises a metal segment extending in X-direction) and electrically coupled either to the power supply node in the cascode arrangement of p-type transistors (¶ 0035: for 100p, 94 coupled to high supply voltage of 80) or to the reference node in the cascode arrangement of n-type transistors;
a fourth metal segment (¶ 0036, fig. 1A: 99) extending in the first direction in the first metal layer of the IC (¶ 0053, fig. 1A: 99 comprises a metal segment extending in X-direction) and aligned with the third metal segment in the first direction (fig. 1A: 99 aligned with 94 in X-direction);
a third via (¶ 0028: VD) configured to electrically couple the source node to the third metal segment (figs. 1A, 6: VD electrically couples 94 of 100p to high supply voltage); and
a fourth via (additional VD) configured to electrically couple the drain node to the fourth metal segment (¶ 0048, figs. 1A, 6: VD electrically couples drain of Mn4 to Vout).
Regarding claim 23, Yang teaches the IC driver of claim 21, wherein each of the cascode arrangement of p- type transistors and the cascode arrangement of n-type transistors further comprises:
a first metal-like defined segment between the third via and the source node (figs. 1A, 6: at least one segment arranged between VD and 80); and
a second metal-like defined segment between the fourth via and the drain node (figs. 1A, 6: at least one segment arranged between VD and 94).
Regarding claim 24, Yang teaches the IC driver of claim 21, wherein each of the cascode arrangement of p-type transistors and the cascode arrangement of n-type transistors comprises a total of two transistors (fig. 6: 100p comprises Mp2 and Mp4, 100n comprises Mn2 and Mn4).
Regarding claim 25, Yang teaches the IC driver of claim 21, wherein the first metal segment is configured to receive a first gate control signal (fig. 1A: first segment of 90 connected to first gate of 41), and
the second metal segment is configured to receive a second gate control signal (fig. 1A: second segment of 90 connected to second gate of 41).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang as applied to claims 2 and 7 above, and further in view of Ozeki (PG Pub. No. US 2021/0356786 A1).
Regarding claim 2, Yang teaches the IC driver of claim 1, comprising a cascode arrangement of first-type transistors (100p) and a cascode arrangement of second-type transistors (100n) each including third and fourth metal segments (91, 94).
Yang does not teach wherein each of the cascode arrangement of first-type transistors and the cascode arrangement of second-type transistors further comprises:
a fifth metal segment extending in the first direction between the third and fourth metal segments,
wherein the fifth metal segment is configured to electrically float.
Ozeki teaches a circuit including electrically floating metal segments (¶ 0101: FM) arranged between active metal segment (¶ 0109 & fig. 9: FM arranged between SE and DE, similar to 91 and 94 of Yang).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the IC driver of Yang with a floating metal segment, as a means to dissipate heat generated in a channel region (Ozeki, ¶ 0113), avoiding transistor abnormalities in the cascode circuit arrangement of Yang.
Regarding claim 8, Yang teaches the IC driver of claim 7, comprising a cascode arrangement of first-type transistors (100/100p) and a cascode arrangement of second-type transistors (100/100n).
Yang does not teach wherein each of the cascode arrangement of first-type transistors and the cascode arrangement of second-type transistors further comprises:
a seventh metal segment extending in the first direction between the third and fourth metal segments; and
an eighth metal segment extending in the first direction between fifth and sixth metal segments,
wherein each of the seventh metal segment and the eighth metal segment is configured to electrically float.
Ozeki teaches a circuit including electrically floating metal segments (¶ 0101: FM) arranged between active metal segment (¶ 0109 & fig. 9: FM arranged between SE and DE, similar to 91, 92, 94 and 99 of Yang).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the IC driver of Yang with seventh and eight floating metal segments, as a means to dissipate heat generated in a channel region (Ozeki, ¶ 0113), avoiding transistor abnormalities in the cascode arrangements of Yang.
Allowable Subject Matter
Claims 11-12 and 14-15 are allowed.
The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitations stating:
“first through sixth gate structures extending in a second direction perpendicular to the first direction and overlying each of the first through fourth active areas at locations corresponding to the transistors of the cascode arrangement”,
“first and second vias configured to electrically couple the first and second gate structures to the first metal segment”,
“third and fourth vias configured to electrically couple the third and fourth gate structures to the second metal segment”, and
“fifth and sixth vias configured to electrically couple the fifth and sixth gate structures to the third metal segment” as recited in claim 11.
Yang teaches a circuit including cascode arrangements (figs. 1A, 6) with gate structures (41A-44D), segments (91-95) overlying the gate structures and active regions (active device regions of 50), and vias connecting the gate structures to the metal segments (fig. 1A). However, Yang fails to explicitly teach the particular combination of elements as required by independent claim 11, such as twelfth through sixteenth vias configured to electrically couple a drain terminal of the cascode arrangement to a second aligned metal segment of each of the first through fifth pluralities of aligned metal segments, and seventeenth through twenty-first vias configured to electrically couple a second source terminal of the cascode arrangement to a third aligned metal segment of each of the first through fifth pluralities of aligned metal segments.
Kim et al. (PG Pub. No. US 2021/0343699 A1) teaches a circuit (figs. 9A-9C among others) including first through sixth gate structures (GL), first through third metal segments (M1/VDD, M1/VSS), first through fifth pluralities of alignment metal segments (M1S), and pluralities of vias (CNT, V0) electrically coupling gates to metal segments. However, Kim fails to teach vias coupling the first through sixth gate structures to respective first through third metal segments, or electrically coupling source and drain terminals to respective aligned metal segments, in the manner required by independent claim 11.
Claims 12 and 14-15 depend on claim 11, and are allowed for implicitly including the allowable subject matter above.
Claim 13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim (claim 11) and any intervening claims.
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating:
“a fifth metal segment extending in the first direction between the first and second metal segments and electrically isolated from each of the first through fourth metal segments” as recited in claim 22.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818