DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Claim Rejections - 35 USC § 103 3
A. Claims 1, 4, 21, 24, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0164813 (“Wang”) in view of US 2019/0148225 (“Chen”). 4
B. Claims 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Chen, as applied to claim 24 above, and further in view of US 2006/0009034 (“Lai”). 11
C. Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Chen and Lai. 14
IV. Allowable Subject Matter 20
V. Double Patenting 21
A. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 of U.S. Patent No. 11,652,149 in view of Chen. 22
VI. Pertinent Prior Art 25
Conclusion 25
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-7, 17-20, the cancellation of claims drawn to non-elected Invention II, and the addition of new claims 21-29 drawn to Invention I, in the reply filed on 11/05/2025 is acknowledged.
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1, 4, 21, 24, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0164813 (“Wang”) in view of US 2019/0148225 (“Chen”).
Claim 1 reads,
1. (Currently amended) A method, comprising:
[1a] receiving a workpiece comprising:
[1b] a gate structure,
[1c] gate spacers disposed along sidewalls of the gate structure,
[1d] a first source/drain feature adjacent the gate structure,
[1e] a capping layer continuously disposed over the gate structure, the gate spacers and the first source/drain feature,
[1f] a first dielectric layer over the capping layer,
[1g] a first source/drain contact extending through the first dielectric layer and the capping layer to contact the first source/drain feature,
[1h] a first etch stop layer (ESL) over the first dielectric layer and a top surface of the first source/drain contact, and
[1i] a second dielectric layer over the first ESL;
[2] forming a gate contact opening through the second dielectric layer, the first ESL, the first dielectric layer, and the capping layer to expose the gate structure;
[3a] after the forming of the gate contact opening, forming a first common rail opening adjoining the gate contact opening,
[3b] wherein the top surface of the first source/drain contact remains covered by a portion of the first ESL;
[4] performing a dry etch process to form a second common rail opening such that the top surface of the first source/drain feature contact is exposed in the second common rail opening; and
[5] after the performing of the dry etch process, forming a common rail contact in the second common rail opening.
With regard to claim 1, Wang discloses,
1. (Currently amended) A method, comprising:
[1a] receiving a workpiece [as shown in Fig. 11] comprising:
[1b] a gate structure [e.g. 806; ¶ 39; Fig. 8],
[1c] gate spacers 816/818 [¶ 39; Fig. 8] disposed along sidewalls of the gate structure,
[1d] a first source/drain feature 810, 812 [¶ 39; Fig. 8] adjacent the gate structure 806,
[1e] … [not taught] … ,
[1f] a first dielectric layer 820 … [¶ 40: Fig. 8],
[1g] a first source/drain contact 826/828, 826/829 [¶ 42; Figs. 9-10] extending through the first dielectric layer 820 … to contact the first source/drain feature 810, 812,
[1h] a first etch stop layer (ESL) 830 [¶ 43; Fig. 11] over the first dielectric layer 820 and a top surface of the first source/drain contact 826/828, and
[1i] a second dielectric layer 832 [¶ 43; Fig. 11] over the first ESL 830;
[2] forming a gate contact opening 834 [¶ 44; Fig. 12] … to expose the gate structure 806 [i.e. the MG portion of the gate structure 806];
[3a] after the forming of the gate contact opening 834, forming a common rail opening 836 adjoining the gate contact opening 834 [¶ 45; Fig. 13]
[3b] wherein the top surface of the first source/drain contact 826/828 remains covered by a portion of the first ESL 830 [¶ 45; see explanation below];
[4] performing a dry etch process to form a second common rail opening 836 such that the top surface of the first source/drain feature contact 826/828 is exposed in the second common rail opening 836 [¶ 45; see explanation below]; and
[5] after the performing of the dry etch process, forming a common rail contact 840/842 in the second common rail opening 836 [¶ 50; Fig. 14].
With regard to features [3b] and [4] of claim 1, Wang states,
[0045] The method 700 proceeds to block 714 where a contact opening is formed. With reference to FIGS. 12 and 13, and in an embodiment of block 714, a contact opening 836 is formed. The contact opening 836 may also be formed by a suitable combination of lithographic patterning and etching (e.g., wet or dry etching) processes. … In some embodiments, one or more etching processes may be used to etch through each of the dielectric layer 832 and the contact etch stop layer 830, in sequence.
(Wang: ¶ 45; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to etch the common rail contact opening 836 by using a first etching process for the dielectric layer 832, stopping on the ESL 830, because that is the purpose of an ESL and, i.e. to stop the etching, and then to use a second etching process, e.g. a dry etching process, to etch through the etch stop layer 830, because Wang explicitly suggests using (1) “one or more etching processes may be used to etch through each of the dielectric layer 832 and the contact etch stop layer 830, in sequence” (id.) and (2) e.g. dry etching (id.).
This is all of the limitations of features [3b] and [4] of claim 1 as well as all of the features of claim 1 disclosed in Wang.
With regard to features [1e]-[1g], and [2] of claim 1,
[1e] a capping layer continuously disposed over and in contact with the gate structure and the first source/drain feature,
Wang does not disclose a capping layer and does not consequently teach the limitations of feature [1e].
Chen shares at least one common inventor and a common assignee with Wang. Chen, like Wang, teaches a workpiece having a preliminary structure including all of the elements of features [1a]-[1i], as well as forming contact openings to each of the first source/drain contact 146 and the gate structure 134/138, as further required by claim 17, as follows:
1. (Original) A method, comprising:
[1a] receiving a workpiece [as shown in Figs. 1N and 2D of Chen] comprising:
[1b] a gate structure 134/138 [¶ 37],
[1c] a first source/drain feature 124 [¶ 32] adjacent the gate structure 134/138,
[1c] gate spacers 122 [¶ 29] disposed along sidewalls of the gate structure 134/138,
[1e] a capping layer 141 [¶¶ 42-43] continuously disposed over and in contact with the gate structure 134/138 and the first source/drain feature 124,
[1f] a first dielectric layer 142 [¶ 44] over the capping layer 141,
[1g] a first source/drain contact 145/146 [¶ 45] extending through the first dielectric layer 142 and the capping layer 141 to contact the first source/drain feature 124,
[1h] a first etch stop layer (ESL) 151 [¶ 55] over the first dielectric layer 142 and a top surface of the first source/drain contact 145/146, and
[1i] a second dielectric layer 152 [¶ 55] over the first ESL 151;
[2] forming a gate contact opening 155 through the second dielectric layer 152, the first ESL 151, the first dielectric layer 142, and the capping layer 141 to expose the gate structure 134/138 [¶ 56; Figs. 1O and 2E];
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to planarize the insulating layer 820 shown in Fig. 8 of Wang, and then blanket deposit the capping layer 141 and first dielectric layer 142 of Chen over the planarized surface, before forming the source/drain contacts 826/828 of Wang (at Figs. 9-10), in order to protect the gate structure 814 of Wang during the etching of the gate contact opening 834 in Wang (at Fig. 12), as taught in Chen. Therefore, Chen may be viewed as an improvement to Wang in this aspect. (See MPEP 2143.)
So modified, all of the limitations of features [1e]-[1g], and [2] of claim 1 are taught. In other words, the portion of insulating layer 820 of Wang is replaces with the capping layer 141 and first dielectric layer 142 of Chen, thereby making (1) the first source/drain contact 826/828 of Wang to extend through each of the first dielectric layer 142 and capping layer 141 of Wang/Chen, and (2) the gate contact opening to extend through each of the first dielectric layer 142 and capping layer 141 of Wang/Chen.
This is all of the features of claim 1.
With regard to claim 4, Wang/Chen further teaches,
4. (Original) The method of claim 1, wherein, before the dry etch process, a portion of the first dielectric layer 142 [of Chen used in Wang (supra)] is exposed in the first common rail opening 836 [of Wang].
Because etching the second dielectric layer 832 of Wang in the first of the two etching steps to form the common rail opening 836, as explained above, adjoins to the gate contact opening 834 that already extends though the etch stop layer 830 by having been previously etched, the common rail 836 opening exposes the first dielectric 142 of Chen used in place of the insulating layer 820 in Wang.
Claim 21 reads,
21. (New) A method, comprising:
[1a] depositing
[1a-1] a capping layer over top surfaces of a gate structure and
[1a-2] a bottom dielectric layer over a source/drain feature,
[1b] the gate structure being disposed over a channel region of an active region,
[1c] the source/drain feature being disposed over a source/drain region of the active region,
[1d] the channel region being adjacent the source/drain region;
[2] depositing a first dielectric layer over the capping layer;
[3] forming a source/drain contact through the first dielectric layer, the capping layer, and the bottom dielectric layer to electrically couple to the source/drain feature;
[4] after the forming of the source/drain contact, depositing an etch stop layer (ESL) over the source/drain contact and the first dielectric layer;
[5] depositing a second dielectric layer over the ESL;
[6] forming a gate contact opening through the second dielectric layer, the ESL, the first dielectric layer, and the capping layer to expose the gate structure;
[7] after the forming of the gate contact opening, forming a first common rail opening adjoining the gate contact opening, wherein a top surface of the source/drain contact remains covered by a portion of the ESL;
[8] performing a dry etch process to form a second common rail opening such that the top surface of the source/drain contact is exposed in the second common rail opening; and
[9] after the performing of the dry etch process, forming a common rail contact in the second common rail opening.
With regard to claims 21 and 28, Wang modified according the Chen as explained under claim 1, teaches,
21. (New) A method, comprising:
[1a] depositing
[1a-1] a capping layer [141 of Chen] over top surfaces of a gate structure 806 [of Wang] and
[1a-2] a bottom dielectric layer [820 of Wang or 128 of Chen (supra)] over a source/drain feature [810, 812 of Wang or 124 of Chen (supra)],
[1b] the gate structure 806 [of Wang] being disposed over a channel region of an active region [not separately labeled in Fig. 8 of Wang but is the region between the source and drain regions 810, 812 directly beneath the gate structure 806 in the “active region” (Wang: ¶ 39)],
[1c] the source/drain feature 810, 812 being disposed over a source/drain region of the active region [as shown in Fig. 8 of Wang],
[1d] the channel region being adjacent the source/drain region [as shown in Fig. 8 of Wang];
[2] depositing a first dielectric layer [142 of Chen] over the capping layer [141 of Chen] [supra];
[3] forming a source/drain contact 826/828 [Wang: Figs. 9-10] through the first dielectric layer [142 of Chen], the capping layer [141 of Chen], and the bottom dielectric layer [820 of Wang or 128 of Chen (supra)] to electrically couple to the source/drain feature 810, 812 [of Wang];
[4] after the forming of the source/drain contact 826/828, depositing an etch stop layer (ESL) 830 over the source/drain contact 826/828 and the first dielectric layer [142 of Chen] [Wang: Fig. 11];
[5] depositing a second dielectric layer 832 over the ESL 830 [Wang: Fig. 11];
[6] forming a gate contact opening 834 [Wang: Fig. 12] through the second dielectric layer 832, the ESL 830, the first dielectric layer [142 of Chen], and the capping layer [141 of Chen] to expose the gate structure 806 [of Wang];
[7a] after the forming of the gate contact opening 834, forming a first common rail opening 836 adjoining the gate contact opening 834,
[7b] wherein a top surface of the source/drain contact 826/828 remains covered by a portion of the ESL 830 [as explained above under claim 1];
[8] performing a dry etch process to form a second common rail opening 836 such that the top surface of the source/drain contact 826/828 is exposed in the second common rail opening 836 [as explained above under claim 1]; and
[9] after the performing of the dry etch process, forming a common rail contact 840/842 in the second common rail opening 836 [Wang: Fig. 14].
28. (New) The method of claim 21,
[1] wherein a bottom surface of the first dielectric layer [142 of Chen] interfaces a top surface of the capping layer [141 of Chen],
[2] wherein a bottom surface of the ESL 830 [of Wang] interfaces a top surface of the first dielectric layer [142 of Chen],
[3] wherein a bottom surface of the second dielectric layer 832 [of Wang] interfaces a top surface of the ESL 830 [of Wang].
This is all of the features of claims 21 and 28.
With regard to claim 24, Wang modified according to Chen, further discloses,
24. (New) The method of claim 21, wherein the forming of the common rail contact 840/842 comprises:
[1] depositing a glue layer [i.e. “glue or barrier layer 840” (Wang: ¶ 50)] over the second common rail opening 836 to contact the second dielectric layer 832, the ESL 830, the first dielectric layer [142 of Chen], the capping layer [141 of Chen], and the source/drain contact 826/828;
[2] depositing a metal fill layer 842 over the glue layer 840 [Wang: Fig. 14]; and
[3] planarizing the glue layer 840, the metal fill layer 842 and the second dielectric layer such that top surfaces of the glue layer, the metal fill layer 842 and the second dielectric layer 832 are coplanar [Wang: Fig. 14; “After deposition of the metal layer 842, and in an embodiment of block 716, a chemical mechanical planarization (CMP) process may be performed to remove excess material and planarize the top surface of the device 800.” (¶ 50)].
Inasmuch as (1) the common rail opening 836 in Wang extends through the second dielectric layer and the first ESL 830 and (2) the gate contact opening 834 of Wang/Chen—that merges with the common rail opening 836—extends through the first dielectric layer 142 and the capping layer 141 of Wang/Chen (supra), the deposition of the glue layer 840 of Wang would contact each of the claimed layers.
B. Claims 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Chen, as applied to claim 24 above, and further in view of US 2006/0009034 (“Lai”).
Claims 25 and 27 read,
25. (New) The method of claim 24, wherein the depositing of the glue layer comprises:
[1] depositing a titanium layer using physical vapor deposition (PVD); and
[2] depositing a titanium nitride layer over the titanium layer using chemical vapor deposition (CVD).
27. (New) The method of claim 24, wherein the depositing of the metal fill layer comprises:
[1] depositing a nucleation layer using pulsed chemical vapor deposition (CVD) or atomic layer deposition (ALD); and
[2] depositing a bulk layer over the nucleation layer using CVD.
The prior art of Wang in view of Chen, as explained above, teaches each of the features of claims 21 and 24.
Wang teaches depositing either Ti or TiN as the “glue or barrier layer 840” before forming the bulk layer which may be W (Wang, ¶ 50). Wang does not provide the details of the deposition process of each of the layers and does not teach the combination of both Ti and TiN or the nucleation layer.
Lai, like Wang, forms tungsten contacts 562/564/566 to underlying semiconductor device structures. Lai teaches the contacts 562/564/566 are made as follows:
[0070] The source and drain regions 522, 524 may be connected to a tungsten plug 560. Each tungsten plug 560 includes a titanium liner 562, a tungsten nucleation layer 564, and a bulk tungsten fill 566. The titanium liner 562 may be a bi-layer stack comprising PVD titanium followed by CVD titanium nitride. ... The tungsten nucleation layer 564 is formed by using a soak process and an ALD process or a soak process and a pulsed-CVD process as described above. The tungsten bulk fill 566 may be deposited using a post soak process and any conventional deposition techniques, including ALD, CVD and PVD.
(Lai: ¶ 70; emphasis added)
Therefore, Lai teaches each of the limitations of claims 25 and 27.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the tungsten contact plugs of Wang to include each of the components of Lai, i.e. PVD-Ti, followed by CVD-TiN followed by ALD or pulsed CVD nucleation layer followed by CVD bulk tungsten fill, because Lai teaches that these processes are suitable for forming a tungsten contact. The benefit would be to have both a glue layer of Ti and a barrier layer of TiN, versus Wang’s “glue or barrier layer 840” (Wang: ¶ 50) as well as a nucleation layer to aid deposition of the bulk tungsten fill 842. As such, Lai may be seen as an improvement to Wang in this aspect. (See MPEP 2143.)
This is all of the features of claims 25 and 27.
Claim 26 reads,
26. (New) The method of claim 25,
[1] wherein the titanium layer comprises a thickness between about 40 Å and about 60 Å,
[2] wherein the titanium nitride layer comprises a thickness between about 10 Å and about 30 Å.
Lai teaches an actual example in which the thickness of the PVD-Ti is 20 Å and the CVD-TiN is 80 Å (Lai: ¶ 74). Wang teaches that the thickness of the “glue or barrier layer 840” can be from 1 nm to 4 nm (Wang: ¶ 50), i.e. 10 Å to 40 Å.
The claimed ranges for the thickness of each of the Ti and TiN layers are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. See In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art).
“[U]nexpected results [relied upon to rebut a prima facie case of obviousness].., must be shown to be unexpected compared with the closest prior art.” In re Baxter Travenol Labs, 952 F.2d 388, 392 (Fed. Cir. 1991)(citation omitted). Such evidence must be commensurate in scope with the degree of patent protection desired. In re Grasselli, 713 F.2d 731,743 (Fed. Cir. 1983). In addition, the difference in results relied upon to establish nonobviousness must be shown to be truly unexpected by one of ordinary skill in the art. Pfizer Inc. v. Apotex Inc., 480 F.3d 1348, 1371 (Fed. Cir. 2007). Thus, it is not enough to merely show that there is a difference—even a significant difference. Rather, the difference in results must be shown to be unexpected by one of ordinary skill in the art. In re Harris, 409 F.3d 1339, 1344 (Fed. Cir. 2005).
C. Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Chen and Lai.
Claim 17 reads,
17. (Original) A method, comprising:
[1a] receiving a workpiece comprising:
[1b] a gate structure,
[1c] a first source/drain feature adjacent the gate structure,
[1d] a capping layer continuously disposed over and in contact with the gate structure and the first source/drain feature,
[1e] a first dielectric layer over the capping layer,
[1f] a first source/drain contact extending through the first dielectric layer and the capping layer to contact the first source/drain feature,
[1g] a first etch stop layer (ESL) over the first dielectric layer and a top surface of the first source/drain contact, and
[1h] a second dielectric layer over the first ESL;
[2] forming a gate contact opening through the second dielectric layer, the first ESL, the first dielectric layer, and the capping layer to expose the gate structure;
[3] after the forming of the gate contact opening, forming a common rail opening adjoining the gate contact opening to expose the first source/drain contact;
[4] depositing a titanium layer over the common rail opening using physical vapor deposition (PVD);
[5] depositing a titanium nitride layer over the titanium layer using chemical vapor deposition (CVD);
[6] depositing a nucleation layer over the titanium layer using pulsed CVD or atomic layer deposition (ALD); and
[7] depositing a bulk layer over the nucleation layer using CVD.
With regard to claim 17, Wang discloses, generally in Figs. 7-15,
17. (Original) A method, comprising:
[1a] receiving a workpiece [as shown in Fig. 2] comprising:
[1b] a gate structure [e.g. 806 (¶ 39)],
[1c] a first source/drain feature 810, 812 [¶ 39; Fig. 8] adjacent the gate structure 806,
[1d] … [not taught] … ,
[1e] a first dielectric layer 820 … [¶ 40: Fig. 8],
[1f] a first source/drain contact 826/828, 826/829 [¶ 42; Figs. 9-10] extending through the first dielectric layer 820 … to contact the first source/drain feature 810, 812,
[1g] a first etch stop layer (ESL) 830 [¶ 43; Fig. 11] over the first dielectric layer 820 and a top surface of the first source/drain contact 826/828, 826/829, and
[1h] a second dielectric layer 832 [¶ 43; Fig. 11] over the first ESL 830;
[2] forming a gate contact opening 834 [¶ 44; Fig. 12] … to expose the gate structure 806 [i.e. the MG portion of the gate structure 806];
[3] after the forming of the gate contact opening 834, forming a common rail opening 836 adjoining the gate contact opening 834 to expose the first source/drain contact 826/828 [¶ 45; Fig. 13];
[4] depositing a titanium layer 840 [¶ 50; Figs. 14-15] over the common rail opening 836 …;
[5]-[6] … [not taught] …
[7] depositing a bulk layer 842 … [e.g. W; ¶ 50; Figs. 14-15].
With regard to features [1d]-[1f], and [2] of claim 1,
[1d] a capping layer continuously disposed over and in contact with the gate structure and the first source/drain feature,
Wang does not disclose a capping layer and does not consequently teach the limitations of feature [1d].
Chen shares at least one common inventor and a common assignee with Wang. Chen, like Wang, teaches a workpiece having a preliminary structure including all of the elements of features [1a]-[1h], as well as forming contact openings to each of the first source/drain contact 146 and the gate structure 134/138, as further required by claim 17, as follows:
17. (Original) A method, comprising:
[1a] receiving a workpiece [as shown in Figs. 1N and 2D of Chen] comprising:
[1b] a gate structure 134/138 [¶ 37],
[1c] a first source/drain feature 124 [¶ 32] adjacent the gate structure 134/138,
[1d] a capping layer 141 [¶¶ 42-43] continuously disposed over and in contact with the gate structure 134/138 and the first source/drain feature 124,
[1e] a first dielectric layer 142 [¶ 44] over the capping layer 141,
[1f] a first source/drain contact 145/146 [¶ 45] extending through the first dielectric layer 142 and the capping layer 141 to contact the first source/drain feature 124,
[1g] a first etch stop layer (ESL) 151 [¶ 55] over the first dielectric layer 142 and a top surface of the first source/drain contact 145/146, and
[1h] a second dielectric layer 152 [¶ 55] over the first ESL 151;
[2] forming a gate contact opening 155 through the second dielectric layer 152, the first ESL 151, the first dielectric layer 142, and the capping layer 141 to expose the gate structure 134/138 [¶ 56; Figs. 1O and 2E];
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to planarize the insulating layer 820 shown in Fig. 8 of Wang, and then blanket deposit the capping layer 141 and first dielectric layer 142 of Chen over the planarized surface, before forming the source/drain contacts 826/828 of Wang (at Figs. 9-10), in order to protect the gate structure 814 of Wang during the etching of the gate contact opening 834 in Wang (at Fig. 12), as taught in Chen. Therefore, Chen may be viewed as an improvement to Wang in this aspect. (See MPEP 2143.)
So modified, all of the limitations of features [1d]-[1f], and [2] of claim 17 are taught. In other words, the portion of insulating layer 820 of Wang is replaces with the capping layer 141 and first dielectric layer 142 of Chen, thereby making (1) the first source/drain contact 826/828 of Wang to extend through each of the first dielectric layer 142 and capping layer 141 of Wang/Chen, and (2) the gate contact opening to extend through each of the first dielectric layer 142 and capping layer 141 of Wang/Chen.
With regard to features [4]-[8] of claim 17,
[4] depositing a titanium layer over the common rail opening using physical vapor deposition (PVD);
[5] depositing a titanium nitride layer over the titanium layer using chemical vapor deposition (CVD);
[6] depositing a nucleation layer over the titanium layer using pulsed CVD or atomic layer deposition (ALD); and
[7] depositing a bulk layer over the nucleation layer using CVD.
Wang teaches depositing either Ti or TiN as the “glue or barrier layer 840” before forming the bulk layer which may be W (Wang, ¶ 50). Wang does not provide the details of the deposition process of each of the layers and does not teach the combination of both Ti and TiN or the nucleation layer.
Lai, like Wang, forms tungsten contacts 562/564/566 to underlying semiconductor device structures. Lai teaches the contacts 562/564/566 are made as follows:
[0070] The source and drain regions 522, 524 may be connected to a tungsten plug 560. Each tungsten plug 560 includes a titanium liner 562, a tungsten nucleation layer 564, and a bulk tungsten fill 566. The titanium liner 562 may be a bi-layer stack comprising PVD titanium followed by CVD titanium nitride. ... The tungsten nucleation layer 564 is formed by using a soak process and an ALD process or a soak process and a pulsed-CVD process as described above. The tungsten bulk fill 566 may be deposited using a post soak process and any conventional deposition techniques, including ALD, CVD and PVD.
(Lai: ¶ 70; emphasis added)
Therefore, Lai teaches each of the limitations of features [4]-[8] of claim 17.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the tungsten contact plugs of Wang to include each of the components of Lai, i.e. PVD-Ti, followed by CVD-TiN followed by ALD or pulsed CVD nucleation layer followed by CVD bulk tungsten fill, because Lai teaches that these processes are suitable for forming a tungsten contact. The benefit would be to have both a glue layer of Ti and a barrier layer of TiN, versus Wang’s “glue or barrier layer 840” (Wang: ¶ 50) as well as a nucleation layer to aid deposition of the bulk tungsten fill 842. As such, Lai may be seen as an improvement to Wang in this aspect. (See MPEP 2143.)
This is all of the features of claim 17.
Claim 18 reads,
18. (Original) The method of claim 17, wherein a total thickness of the titanium layer and the titanium nitride layer is between about 0.3 nm and about 1.7 nm.
Wang further teaches that the thickness of the “glue or barrier layer 840” is from 1 nm to 4 nm (Wang: ¶ 50). Although Wang modified according to Lai to include both Ti and TiN, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the bi-layer of Ti/TiN to be from 1 nm to 4 nm because Wang desires this thickness.
As such, the claimed range for the “total thickness of the titanium layer and the titanium nitride layer” overlaps the range in Wang.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
Claim 19 reads,
19. (Original) The method of claim 17, wherein, after the depositing of the titanium layer, the titanium layer is in contact with the second dielectric layer, the first ESL, the first dielectric layer, and the capping layer.
Inasmuch as (1) the common rail opening 836 in Wang extends through the second dielectric layer and the first ESL 830 and (2) the gate contact opening 834 of Wang/Chen—that merges with the common rail opening 836—extends through the first dielectric layer 142 and the capping layer 141 of Wang/Chen (supra), the deposition of the Ti layer of Lai would contact each of the claimed layers.
Claim 20 reads,
20. (Original) The method of claim 17, wherein the depositing of the nucleation layer and the depositing of the bulk layer comprise use of tungsten hexafluoride (WF6) or tungsten hexachloride (WCl6).
Wang does not disclose from what W precursor that bulk W fill is deposited.
Lai further teaches that the bulk W fill is deposited, after the nucleation process using WF6 (Lai: “Example 7” at ¶¶ 196-219, especially ¶¶ 214-215).
As such, inasmuch as it is obvious to use the processes and components of Lai as that tungsten contacts in Wang (supra), it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, in addition to the above, to use WF6 as the W precursor for the bulk fill because Lai teaches that it is suitable for CVD of bulk W fill. As such, the selection of WF6 amounts to obvious material choice. (See MPEP 2144.07.)
IV. Allowable Subject Matter
Claims 2, 3, 5-7, 22, 23, and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2, 3, 5-7, 22, 23, and 29 read,
2. (Original) The method of claim 1, wherein the performing of the dry etch process comprises use of a nitrogen plasma, a hydrogen plasma or a combination thereof.
3. (Original) The method of claim 1, wherein the performing of the dry etch process forms rounded corners around top edges of the second common rail opening.
5. (Original) The method of claim 4, wherein the performing of the dry etch process forms a middle rounded corner around an edge of the portion of the first dielectric layer.
6. (Original) The method of claim 1, further comprising: before the performing of the dry etch process, cleaning the workpiece with a wet clean process.
7. (Original) The method of claim 6, wherein the wet clean process comprises use of 2-anilino-4-methyl-1,3-thiazole-5-carboxylic acid or isopropyl alcohol (IPA).
22. (New) The method of claim 21, wherein the performing of the dry etch process forms rounded corners around top edges of the second common rail opening.
23. (New) The method of claim 21, wherein the performing of the dry etch process comprises use of a nitrogen plasma, a hydrogen plasma or a combination thereof.
29. (New) The method of claim 28,
[1] wherein the active region extends lengthwise along a direction,
[2] wherein, along the direction, the common rail contact comprises a first width at the top surface of the ESL and a second width at a top surface of the second dielectric layer,
[3] wherein the first width is between about 48 nm and about 54 nm,
[4] wherein the second width is between about 43 nm and about 78 nm.
The prior art does not reasonably teach or suggest—in the context of each of the claims—the limitations recited therein.
V. Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
A. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 of U.S. Patent No. 11,652,149 in view of Chen.
Claim 1 reads,
1. (Currently amended) A method, comprising:
[1a] receiving a workpiece comprising:
[1b] a gate structure,
[1c] gate spacers disposed along sidewalls of the gate structure,
[1d] a first source/drain feature adjacent the gate structure,
[1e] a capping layer continuously disposed over the gate structure, the gate spacers and the first source/drain feature,
[1f] a first dielectric layer over the capping layer,
[1g] a first source/drain contact extending through the first dielectric layer and the capping layer to contact the first source/drain feature,
[1h] a first etch stop layer (ESL) over the first dielectric layer and a top surface of the first source/drain contact, and
[1i] a second dielectric layer over the first ESL;
[2] forming a gate contact opening through the second dielectric layer, the first ESL, the first dielectric layer, and the capping layer to expose the gate structure;
[3a] after the forming of the gate contact opening, forming a first common rail opening adjoining the gate contact opening,
[3b] wherein the top surface of the first source/drain contact remains covered by a portion of the first ESL;
[4] performing a dry etch process to form a second common rail opening such that the top surface of the first source/drain feature contact is exposed in the second common rail opening; and
[5] after the performing of the dry etch process, forming a common rail contact in the second common rail opening.
Claim 9 of the ‘149 patent reads, noting that the enumerated features equate to or broader than those recited in instant claim 1, above:
9. A method, comprising:
[1a] receiving a workpiece comprising:
[1b] a gate structure,
[1d] a first source/drain feature adjacent the gate structure,
[1f] a first dielectric layer over the gate structure and the first source/drain feature,
[1g] a first source/drain contact disposed over the first source/drain feature,
[1h] a first etch stop layer (ESL) over the first dielectric layer, and
[1i] a second dielectric layer over the first ESL;
[2] forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer … to expose the gate structure;
[3] after the forming of the gate contact opening, forming a common rail opening adjoining the gate contact opening, wherein the first source/drain contact is exposed in the common rail opening, the forming of the common rail opening comprising:
forming a patterned photoresist layer over the second dielectric layer, the patterned photoresist layer comprising an opening direct over the first source/drain contact and the gate contact opening;
etching the first ESL and the second dielectric layer using a first dry etch process and the patterned photoresist layer as an etch mask, wherein the first source/drain contact remains covered by a portion of the first ESL; and
after the etching, cleaning the common rail opening using a first wet clean process;
[4] after the cleaning, performing a second dry etch process to remove the portion of the first ESL and to expose the first source/drain contact; and
[5] after the forming the common rail opening, forming a common rail contact in the common rail opening.
Thus the only limitations lacking in claim 9 of the ‘149 patent are features [1c] and [1e] of instant claim 1.
With regard to feature [1c] of instant claim 1,
[1c] gate spacers disposed along sidewalls of the gate structure,
Chen teaches gate spacers 122 adjacent the gate structure (Chen: ¶ 29).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include gate spacers 122 disposed along sidewalls of the gate structure of claim 9 of the ‘149 patent in order to protect the sidewalls of the gate structure, as taught in Chen.
With regard to feature [1e] of instant claim 1,
[1e] a capping layer continuously disposed over the gate structure, the gate spacers and the first source/drain feature,
As explained above in rejecting claim 1 over Wang in view of Chen, the inclusion of the capping layer 141 of Chen is obvious in order to protect the gate structure during the etching of the gate contact. That explanation is incorporated here.
This is all of the features of claim 1.
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2020/0105519 (“Lin”) is cited for teaching a method of making a common rail contact. See Figs. 2-11 and associated text.
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814