Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-5 are pending and have been examined.
Priority
Acknowledgment is made of applicant's claim for foreign benefit based on JP2022-119053 filed on 07/26/2022.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(2):
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ebihara et al. (US 20230253492 A1 – hereinafter Ebihara).
Regarding Claim 1, Ebihara teaches a semiconductor device (see the entire document; Figs. 9-10; specifically, [0039]-[0155], and as cited below), comprising:
a semiconductor substrate (30 = {31, 32} – Fig. 10 – [0039] – “the MOSFET 100 is formed using an epitaxial substrate 30 comprised of a monocrystalline substrate 31 and an epitaxial layer 32”) in which an element having a gate electrode (313 – [0143] – “a gate electrode 313”) is provided;
a first main electrode (51 – [0046] – “a source electrode 51”) arranged on a first surface (top surface) of the semiconductor substrate (30);
a second main electrode (8 – [0047] – “A back surface electrode 8 functioning as a drain electrode”) arranged on a second surface (bottom surface) opposite to the first surface (top surface) in a substrate thickness direction (that is, in the y-direction);
a gate pad (52p – [0047] – “a gate pad 52p”) arranged on the first surface (top surface) of the semiconductor substrate (30) at a position different from a position of the first main electrode (51 and 52p are positioned differently as seen in Fig. 1); and
a gate resistor having an adjustable resistance value ([0155] – “gate resistor made by the gate electrode 313, which in turn suppresses self-oscillation during switching between the ON and OFF states. The resistance of such a parasitic gate resistor is controllable” – controllable=adjustable),
wherein the gate resistor is arranged on the first surface of the semiconductor substrate (Fig. 10), and is connected to a position between the gate electrode (313) and the gate pad (52p).
Regarding Claim 5, Ebihara teaches the semiconductor device according to claim 1, wherein the gate resistor is made of metal (Claim 27: “wherein the source electrode and the gate portion are made of metal containing at least one selected from the group consisting of Al, Cu, Mo, Ni, and Ti, or an Al alloy”).
Allowable Subject Matter
Claims 2-4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 2: The semiconductor device according to claim 1, wherein the gate resistor is made of silicon, and is configured to have a ladder structure, and the gate resistor includes: a plurality of connecting parts provided in parallel between the gate electrode and the gate pad; and a plurality of adjuster pads provided respectively in the plurality of connecting parts to adjust the resistance value.
Claims 3-4 depend from claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898