Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-14 and new claims 21-26 in the reply filed on April 29, 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomson et al (US 20230088578) in view of Goktepeli (US 9755029).
[claim 1] A method, comprising: forming a gate structure over a semiconductor substrate (figure 10, paragraphs 0083-0086, element 1004 shows forming a gate structure over the fins [which is over a substrate] as best seen in figure 1a where the fins are formed on a multilayer substrate, where the gate structure is element 108 [as shown in figure 1a]),
forming a source/drain epitaxial structure adjacent a side of the gate structure (figures 1a and 10, paragraphs 0024, and 0083-0086, where element 103a/b, 107a/b is the epitaxial formation of source/drains which are adjacent to the gate structures of element 108 in figure 1a);
forming a first isolation structure in the gate structure, wherein the first isolation structure spaces apart a first portion of the gate structure from a second portion of the gate structure from a top view (figures 9a-9b, 10, paragraphs 0083-0086 and 0076, where element 102 and 105 [as shown below in figure 1] is the first isolation structure which spaces apart a first portion [left-hand side] and a second portion [right-hand side]);
forming a front-side metallization layer over a frontside of the first isolation structure, wherein the front-side metallization layer comprises a front-side metal feature overlapping the first isolation structure (figures 1a and 10, paragraphs 0083-0086, where step 1018 shows a step of forming “front side contacts and interconnect” which is a metal layer on the front side [top side] of the device and is shown in figure 1a as element 111)
depositing a dielectric layer over a backside of the first isolation structure (figures 1a-1c, paragraph 0035 where element 104 is seen to be formed beneath the isolation structure [as shown in figure 1 below] which contains the middle element 108 [as a dielectric] and the adjacent elements 102 to separate the outside elements 108 [as gate structure]);
However, Thomson et al does not specifically disclose
[claim 1] and forming a conductive via in the dielectric layer and the first isolation structure, wherein the conductive via is in contact with the front-side metal feature
However, Goktepeli does teach
[claim 1] and forming a conductive via in the dielectric layer and the first isolation structure, wherein the conductive via is in contact with the front-side metal feature (figures 4 and 5a, col 8 lines 39-52, where element 570 is formed in the dielectric layer on the bottom [backside dielectric] and goes through the dielectric layer surrounding the gate electrode [element 506] which is in the same location as the first isolation layer of Thomson et al and connects to a front-side metallization layer above and overlapping the isolation layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Thomson et al to incorporate the teachings of Goktepeli to connect the front side metallization layer to a lower portion of the device to ensure contact with outside circuitry and maximize density by running the contact via through the isolation dielectric layer.
Regarding claims 6 and 10
Additionally, Thomson et al as modified does not specifically teach
[claim 6] The method of claim 1, wherein a height of the conductive via is greater than a height of the gate structure.
[claim 10] The method of claim 1, wherein a first portion of the conductive via in the dielectric layer is formed of a same material composition as a second portion of the conductive via in the first isolation structure.
However, Goktepeli further discloses
[claim 6] The method of claim 1, wherein a height of the conductive via is greater than a height of the gate structure (figure 5a, col 8 lines 39-52, where the conductive via [element 570 extending vertically] extends over the gate structure [labeled “gate”]).
[claim 10] The method of claim 1, wherein a first portion of the conductive via in the dielectric layer is formed of a same material composition as a second portion of the conductive via in the first isolation structure (figure 5a, col 8 lines 39-52, where the conductive via [element 570] is made of one continuous material [same material] in both the dielectric portion and isolation portion as it extends to the front-side metallization layer [element 570 above]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Thomson et al to incorporate the teachings of Goktepeli to extend the conductive via over the gate structure in order to adequately connect the transistors to outside circuitry by creating an interconnect that extends outside the transistor region.
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Figure 1: From Figure 9B of Thomson et al (US 20230088578).
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomson et al (US 20230088578) and Goktepeli (US 9755029) and in further view of Verma et al (US 20210125921).
Thomson et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 3] The method further comprising: forming a contact plug on a backside of the source/drain epitaxial structure; and forming a conductive line in the dielectric layer, wherein the conductive line is in contact with a backside of the contact plug.
[claim 4] The method of claim 3, wherein a portion of the conductive via is at a same level height as the conductive line.
However, Verma et al does teach
[claim 3] The method further comprising: forming a contact plug on a backside of the source/drain epitaxial structure (figure 2, paragraphs 0026, where a contact plug [element 24_1] is formed on the backside [bottom half] of the device and under the source/drain epitaxial structure [element 14]);
and forming a conductive line in the dielectric layer, wherein the conductive line is in contact with a backside of the contact plug (figure 2, paragraphs 0026-0027, where element 18_3 is the dielectric layer on the backside [bottom side] and the conductive line [element 22_3] is in contact with the backside contact plug [element 24_1] and inside the backside dielectric layer).
[claim 4] The method of claim 3, wherein a portion of the conductive via is at a same level height as the conductive line (figure 2, paragraphs 0026-0027, where element 22_3 is the conductive line is at a same level height as element 24_4 which is the conductive via read into from Thomson et al as modified as also being inside the dielectric layer and extending to above the gate electrode [as seen in figure 5 to a equivalent front-side [top side] metallization layer of element 44_3 [metallic conductive pad above the gate portion of the device]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Thomson et al to incorporate the teachings of Verma et al to form a conductive plug beneath the source/drain region to connect the source\drain to any outside circuitry through a conductive line.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomson et al (US 20230088578) and Goktepeli (US 9755029) and in further view of Chiang et al (US 20220352150).
Thomson et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 7] The method of claim 1, further comprising: forming a second isolation structure in the gate structure, wherein the second isolation structure spaces apart the second portion of the gate structure from a third portion of the gate structure, and forming the conductive via is performed such that the second isolation structure is free of a material of the conductive via.
[claim 8] The method of claim 7, wherein a length of the second isolation structure along a direction perpendicular to a lengthwise direction of the gate structure is greater than a length of the first isolation structure along the direction from a top view.
However, Chiang et al does teach
[claim 7] The method of claim 1, further comprising: forming a second isolation structure in the gate structure, wherein the second isolation structure spaces apart the second portion of the gate structure from a third portion of the gate structure (figure 3D, paragraph 0082, element 181 is the second gate isolation structure wherein it separates the second gate portion [section 114 in figure 3D of the gate portion] from the third section [section 184 of the gate section in figure 3D]),
and forming the conductive via is performed such that the second isolation structure is free of a material of the conductive via (figure 3D, paragraph 0082, where no conductive via is formed in the second gate isolation structure [element 181] and thus the conductive via [as mentioned in Thomson et al as modified above] is not formed in any material of the second isolation structure).
[claim 8] The method of claim 7, wherein a length of the second isolation structure along a direction perpendicular to a lengthwise direction of the gate structure is greater than a length of the first isolation structure along the direction from a top view (figure 3D, paragraph 0082, where the width of the second isolation structure [element 181] is wider than the first [element 189]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Thomson et al as modified to incorporate the teachings of Chiang et al in order to add another gate isolation structure that is wider than the first to allow for multiple partitions of the gate structure to allow for a plurality of transistor devices in a smaller area, thus maximizing density and creating a width such that it minimizes any parasitic coupling between the isolated gate structures.
Regarding claim 9,
Thomson et al as modified above teaches all of the limitations of the parent claim, claim 7, but does not specifically disclose
[claim 9] The method of claim 7, wherein a width of the second isolation structure along a lengthwise direction of the gate structure is less than a width of the first isolation structure along the lengthwise direction of the gate structure from a top view.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Thomson et al as to add another gate isolation structure that is thinner than the first to allow for multiple partitions of the gate structure to allow for a plurality of transistor devices in a smaller area, thus maximizing density and creating a width such that it minimizes any parasitic coupling between the isolated gate structures.
Claim(s) 11, 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al (US 20220352150) in view of Goktepeli (US 9755029).
Chiang et al teaches
[claim 11] A method, comprising: forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a sacrificial layer and a channel layer over the sacrificial layer (figures 2a-c, paragraphs 0028-0030, where epitaxially grown stacks [elements 102 and 116 of figures 2a and 2b] comprise a sacrificial layer [element 120 in figure 2a of stack element 116] and channel layers over the sacrificial layers [element 118 of stack element 116 in figure 2a]);
patterning the epitaxial stack into a fin (figure 2c, paragraphs 0028-0030, where the epitaxial stacks [element 102 vertically aligned with element 116 and element 116] are patterned into fins);
forming a dummy gate structure over the fin (figure 2N, paragraph 0056, where element 138 is patterned and formed over the fin structures [element 116]);
replacing the dummy gate structure and the sacrificial layer with a metal gate structure surrounding the channel layer (figures 2O and 2P, paragraphs 0057 and 0061, where the dummy gate structure [element 138] and sacrificial layer are removed and replaced with a metal gate structure [element 134] is surrounding the fin structures [element 116 which in figure 2O and 2P is seen by the structure of element 118]);
forming an isolation structure in the metal gate structure, wherein the isolation structure spaces apart a first portion of the metal gate structure from a second portion of the metal gate structure from a top view (figures 2Y and 2Z, paragraph 0082, where element 179 is the first gate isolation structure in the metal gate region that separates a first portion of the gate [right-hand side of element 179] and the second portion of the metal gate structure [left-hand side of element 179]);
However, Chiang et al does not specifically disclose
[claim 11] and forming a conductive via in the isolation structure, wherein a height of the conductive via is greater than a height of the metal gate structure.
However, Goktepeli does teach
[claim 11] and forming a conductive via in the isolation structure, wherein a height of the conductive via is greater than a height of the metal gate structure (figures 4 and 5a, col 8 lines 39-52, where element 570 is formed in the dielectric layer on the bottom [backside dielectric] and goes through the dielectric layer surrounding the gate electrode [element 506] which is in the same location as the first isolation layer of Chiang et al and connects to a front-side metallization layer above and overlapping the isolation layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chiang et al to incorporate the teachings of Goktepeli to connect the front side metallization layer to a lower portion of the device to ensure contact with outside circuitry and maximize density by running the contact via through the isolation dielectric layer.
Regarding claim 13,
Chiang et al further teaches
[claim 13] The method of claim 11, further comprising: forming shallow trench isolation (STI) structures around the fin, wherein forming the isolation structure is performed such that the isolation structure extends through the STI structures (figures 2D and 2Z, paragraph 0038 where element 126 is the shallow trench isolation structure and intersects with the first gate isolation structure [element 179 of figure 2N]).
Regarding claim 14,
Chiang et al as modified does not specifically disclose
[claim 14] The method of claim 11, wherein the first portion of the metal gate structure comprises an n-type work function metal layer, and the second portion of the metal gate structure comprises a p-type work function metal layer.
However, according to MPEP 2144.05 II. ROUTINE OPTIMIZATION
A. Optimization Within Prior Art Conditions or Through Routine Experimentation
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chiang et al as modified to incorporate a work function of N-type for the first part of the gate and P-type for the second part of the gate. Specifically, paragraph 0062 states that a work-function may be produced on the gate metal as the gate metal can consist of multiple layers. A work function can be one of two types, N and P. It would have been obvious to try the two options on each of the gate portions to optimize the structure for specific use cases by allowing the N-type to be on the first gate portion [right-hand side of element 179 in figure 2Z] and the P-type to be on the second gate portion [left-hand side of element 179 in figure 2Z]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al (US 20220352150), Goktepeli (US 9755029) and in further view of Jourdain et al (US 20200152508).
Chiang et al as modified teaches all of the limitations of the parent claim, but does not specifically disclose
[claim 12] the method further comprising: removing a portion of the semiconductor substrate to expose a backside of the isolation structure prior to forming the conductive via.
However, Jourdain et al does teach
[claim 12] the method further comprising: removing a portion of the semiconductor substrate to expose a backside of the isolation structure prior to forming the conductive via (figures 1C-1J, paragraph 0046, where a portion of the semiconductor substrate is removed [element 1] to expose a backside of the isolation structure prior to forming a conductive via – where elements 5 and 12 form the hole of the backside of the device situated between the fin structures [elements 3 and 2] where the fin structures are read onto Jourdain et al from Chiang et al and the isolation structures are situated between the fin structures in Chiang et al [elements 181 and 189 situated between fins 124 of Chiang et al], thus Jourdain et al exposes a backside of the substrate [bottom half below fins structures] before forming a conductive via [element 14 of Jourdain et al in figure 1J]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chiang et al as modified to incorporate the teachings of Jourdain et al in order to form a trench in the substrate to connect a via so that the transistors surrounding the fin structures can connect to outside circuitry and be a functional device.
Claim(s) 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al (US 20220352150) in view of Thomson et al (US 20230088578).
Chiang et al teaches
[claim 21] A method, comprising: forming a fin structure over a substrate (figures 2A and 2B, paragraph 0036, where element 124 is the fin structures formed over a substrate [element 103]);
forming a gate structure extending lengthwise along a first direction and across the fin structure (figures 2Q and 2R, paragraph 0068, where element 162 is formed in a first direction [horizontally across the device] across the fin structures [element 124 from figure 2C]);
etching the gate structure such that a first portion of the gate structure is spaced apart from a second portion of the gate structure along the first direction (figure 2Y, paragraphs 0079-0080, where the trench 116 is created in the gate such that the gate structure is spaced from a second portion [left-hand side] to a first portion [right-hand side] in a first direction [x-direction/horizontal direction]);
However, Chiang et al does not specifically disclose
[claim 21] and forming a conductive via between the first portion and the second portion of the gate structure along the first direction.
However, Thomson et al does teach
[claim 21] and forming a conductive via between the first portion and the second portion of the gate structure along the first direction (figure 4a, paragraph 0060, where element 116 is an interconnect structure, equivalent to a conductive via, which extends between a fist and second portion of the gate structure [first portion is left-hand side of element 102] and the second portion [right-hand side of element 102], extending along a first direction [horizontal /x-direction]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chiang et al to incorporate the teachings of Thomson et al to put a conductive line between the gate electrodes to allow for connection of the circuit to outside circuitry to make a functioning device.
Regarding claims 22, 24-25
Chiang et al further discloses
[claim 22] The method of claim 21, wherein etching the gate structure comprises forming a first isolation structure between the first portion and the second portion of the gate structure along the first direction, the first isolation structure extending lengthwise along a second direction different from the first direction (figures 2Y and 2Z, paragraphs 0082-0083 where element 179 [first isolation structure] is formed between the first section [right-hand side] and second portion [left-hand side] along a first direction [x-direction] and extends lengthwise in a second direction [y-direction/vertical] which is different than the first direction).
[claim 24] The method of claim 21, wherein etching the gate structure is performed such that a third portion of the gate structure is spaced apart from the first portion and the second portion of the gate structure, and the second portion is between the first portion and the third portion along the first direction (figures 3C-3D, paragraphs 0087-0088, where an etching process is performed on the gate structure [elements 114] such that a third portion is created [left-hand side of element 189 of figure 3D], where the second portion [labeled element 114 in figure 3D] is situated between the first portion [right-hand portion of element 181] and third portion [left-hand side of element 189]).
[claim 25] The method of claim 24, wherein etching the gate structure further comprises forming a second isolation structure between the second portion and the third portion along the first direction, the second isolation structure extending lengthwise along a second direction different from the first direction (figures 3C and 3D, paragraph 0087-0088, where element 189 is the second gate isolation structure formed in the etched portion of the gate electrode [of figure 3C] where the second portion is situated between the first and third portion along an x-direction – where the portions of the gate structure from left to right of figure 3D are the third, second then first separated by elements 189 [separating the third and second] and element 181 [separating the second and first]).
Regarding claim 23,
Chiang et al as modified teaches all of the limitations of the parent claim, claim 22, but does not specifically disclose
[claim 23] The method of claim 22, wherein the conductive via is formed spaced apart from the first portion and the second portion of the gate structure through the first isolation structure.
However, Thomson et al does teach
[claim 23] The method of claim 22, wherein the conductive via is formed spaced apart from the first portion and the second portion of the gate structure through the first isolation structure (figure 4a, paragraph 0060, where element 116 is an interconnect structure, equivalent to a conductive via, which extends between a fist and second portion of the gate structure [first portion is left-hand side of element 102] and the second portion [right-hand side of element 102], extending along a first direction [horizontal /x-direction] and is formed spaced apart from the gate electrode [element 109] through the isolation structure [element 102]. Specifically there is a section of element 115 that is separated in the horizontal direction away from element 109 where element 102 is situated between the two).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chiang et al to incorporate the teachings of Thomson et al to put a conductive line between the gate electrodes to allow for connection of the circuit to outside circuitry to make a functioning device.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al (US 20220352150), Thomson et al (US 20230088578) and in further view of Goktepeli (US 9755029).
Chiang et al as modified teaches all of the limitations of the parent claim, claim 25, but does not specifically disclose
[claim 26] The method of claim 25, wherein a height of the conductive via is greater than a height of the second isolation structure.
However, Goktepeli does teach
[claim 26] The method of claim 25, wherein a height of the conductive via is greater than a height of the second isolation structure (figure 5a, col 8 lines 39-52, where the conductive via [element 570 extending vertically] extends over the gate structure [labeled “gate”] where from Chiang et al as modified the gate and isolation structure have a similar height and the conductive via extends above both in Goktepeli).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Thomson et al to incorporate the teachings of Goktepeli to extend the conductive via over the gate structure in order to adequately connect the transistors to outside circuitry by creating an interconnect that extends outside the transistor region.
Allowable Subject Matter
Claims 2 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al (US 20230138012), Haran et al (US 20230093657), Liaw (US 11581414), Chuang et al (US 20230018869), Guler et al (US 20220416040), Choi et al (US 20220254650), Chiu et al (US 20220122993) as transistor devices with gate isolation structures situated between continuous gate structures.
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/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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