DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Gillis et al (US Publication 20100237472) in view of Ma et al (US Patent 6509622).
Regarding claim 1, Gillis teaches a semiconductor structure comprising:
an integrated circuit die comprising:
a substrate having an electrical device (Fig. 3, device including 30, 32, 34, 14);
an interconnect structure on the substrate, wherein the interconnect structure comprises dielectric layers and conductive features, wherein the conductive features are electrically coupled to the electrical device (Fig. 3, interconnect structure including 47, 52, 57, 62, 72, 77, 82, 87, 92);
a protective ring at least partially embedded in the substrate, wherein the protective ring comprises a first material different from a second material of a seal ring (Fig. 4A-C, protective ring including substrate embedded 46, 51, 56, 61, 66, 71, 76, 81, 86, and 91,para 21, Cu), and
wherein the protective ring comprises [[a]] the first material different from a third material of the substrate (Fig. 4A, 46 and 10, para 21 Cu, para 14, semiconductor material as listed); and
an encapsulant encircling the integrated circuit die in the top down view (Fig 4C, 50).
Gillis does not teach a seal ring in the dielectric layers of the interconnect structure, wherein the seal ring encircles the electrical device in a top down view, such that the seal ring is encircled by the protective ring in a top down view.
Ma teaches a seal ring in the dielectric layers of the interconnect structure, wherein the seal ring encircles the electrical device in a top down view (Fig. 1A and 4, inner most 105 structure guard ring 401 closest to and encircling circuit area 107, col 5 lines 45-65, materials include aluminum alloy).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Gillis to include the seal ring as taught by Ma in order to prevent moisture, contaminants, and crack propagation of the device, noting that the seal ring 401 closest to and encircling the circuit area, taught into Gillis would then be close enough to the circuit area that, the far exterior protective ring 46, 51, 56, 61, 66, 71, 76, 81, 86, and 91 would encircle the taught in seal ring from Ma.
Regarding claim 2, Gillis as modified teaches the limitations of claim 1 upon which claim 2 depends.
Gillis teaches wherein the protective ring is electrically isolated from the electrical device (Fig. 4a, structure from 46 to 91 electrically isolated from electrical device).
Regarding claim 3, Gillis as modified teaches the limitations of claim 1 upon which claim 3 depends.
Gillis teaches wherein the protective ring extends through the dielectric layers of the interconnect structure, and wherein the first material of the protective ring is different from materials of the dielectric layers (Fig. 4A, structure from 46-91 extends through dielectric layers 40 and 50, para 16-17, para 24, different materials).
Regarding claim 4, Gillis as modified teaches the limitations of claim 1 upon which claim 4 depends.
Gillis teaches wherein the protective ring is completely embedded in the substrate (Fig. 4A, 46 completely embedded in 10).
Claims 5-9, and 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over Gillis et al (US Publication 20100237472) in view of Ma et al (US Patent 6509622) and Onuma (US Publication 20210104473).
Regarding claims 5 and 6, Gillis as modified teaches the limitations of claim 1 upon which claim 5 depends.
Gillis does not teach:
[claim 5] wherein the protective ring is between an outer edge of the seal ring and a first edge of the integrated circuit die in the top down view, wherein the first edge of the integrated circuit die is a closest edge of the integrated circuit die to the outer edge of the seal ring, and wherein the first edge of the integrated circuit die comprises a chamfered corner of the integrated circuit die.
[claim 6] wherein the protective ring is between an outer edge of the seal ring and a first edge of the integrated circuit die in the top down view, wherein the first edge of the integrated circuit die is a closest edge of the integrated circuit die to the outer edge of the seal ring, wherein the outer edge of the seal ring is spaced apart from the first edge of the integrated circuit die by a first distance, wherein the integrated circuit die has a first width, and wherein a ratio of the first distance to the first width is in a range from 0.004 to 0.008.
Onuma teaches
[claim 5] wherein the protective ring is between an outer edge of the seal ring and a first edge of the integrated circuit die in the top down view (Fig. 20, 78 positioned between outer edge of 731 and KERF), wherein the first edge of the integrated circuit die is a closest edge of the integrated circuit die to the outer edge of the seal ring (Fig. 20, edge of memory stack and 78), and wherein the first edge of the integrated circuit die comprises a chamfered corner of the integrated circuit die
[claim 6] wherein the protective ring is between an outer edge of the seal ring and a first edge of the integrated circuit die in the top down view (Fig. 18D, 78 between outer edge of seal ring 731 and KERF), wherein the first edge of the integrated circuit die is a closest edge of the integrated circuit die to the outer edge of the seal ring (Fig. 20, edge of memory stack and 78), wherein the outer edge of the seal ring is spaced apart from the first edge of the integrated circuit die by a first distance (Fig. 18D, area labeled dummy staircase track and seal ring 731), wherein the integrated circuit die has a first width (Fig. 18D, width BD to BD), and wherein a ratio of the first distance to the first width is in a range from 0.004 to 0.008 (Fig. 18D, ratio of width BD to DB to distance between outer edge of 731 and BD).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Gillis as modified to include the protective ring, seal ring, and IC edges as taught by Onuma in order to prevent moisture, contaminants, and crack propagation of the device.
Regarding claim 7, Gillis teaches a
semiconductor structure, comprising:
a first integrated circuit die (Fig. 4A), wherein the first integrated circuit die comprises:
a substrate having a device region (Fig. 4A, region including 30, 32, 34, and 14), wherein the substrate comprises a first material (Fig. 4A, 10, para 14, semiconductor material as listed);
an interconnect structure on the substrate (Fig. 3, interconnect structure including 47, 52, 57, 62, 72, 77, 82, 87, 92);
a protective feature in the interconnect structure and the substrate (Fig. 4A, 46 and associated metallization), wherein the protective feature comprises a second material different from the first material (para 21, Cu),
wherein the protective feature comprises a first portion in the substrate (Fig. 4A, 46 in 10), wherein a first surface of the first portion is in contact with a first surface of the interconnect structure (Fig. 4A, surface of 46 in contact with interconnect structure including 40 and 50), and wherein the first surface of the interconnect structure is in contact with a first surface of the substrate (Fig. 4A, surface of interconnect structure including 40 and 50 in contact with 10).
Gillis does not teach:
a seal ring in the interconnect structure; and wherein the seal ring is between the protective feature and the device region.
Ma teaches a seal ring in the interconnect structure (Fig. 1A and 4, inner most 105 structure guard ring 401 closest to and encircling circuit area 107, col 5 lines 45-65, materials include aluminum alloy)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Gillis to include the seal ring as taught by Ma in order to prevent moisture, contaminants, and crack propagation of the device.
Gillis as modified still lacks wherein the seal ring is between the protective feature and the device region.
Onuma teaches wherein the seal ring is between the protective feature and the device region (Fig. 18D, 733 between 78 and cell array)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Gillis as modified to include the protective ring, seal ring, and IC edges as taught by Onuma in order to prevent moisture, contaminants, and crack propagation of the device.
Regarding claims 8 and 9, Gillis as modified teaches the limitations of claim 7 upon which claim 8 depends.
Gillis teaches:
[claim 8] wherein the second material is a dielectric material (para 21)
[claim 9] wherein the second material is a conductive material (para 21).
Regarding claim 12, Gillis as modified teaches the limitations of claim 7 upon which claim 12 depends.
Gillis teaches wherein [[a]] the first surface of the first portion is level with [[a]] the first surface of the substrate (Fig. 4A, surface of 46 level with surface of 10).
Regarding claim 13, Gillis as modified teaches the limitations of claim 7 upon which claim 13 depends.
Gillis teaches wherein the protective feature is one or more concentric continuous rings encircling the seal ring in a top down view (Fig. 4A-C, 46/71).
Regarding claim 14, Gillis as modified teaches the limitations of claim 7 upon which claim 14 depends.
Gillis teaches wherein the protective feature is one or more concentric fragmented rings encircling the seal ring in a top down view (Fig. 7).
Regarding claim 15, Gillis teaches a method of forming a semiconductor structure, the method comprising:
forming a first portion of a protective structure in a semiconductor wafer (Fig. 2, 46 in 10),
wherein the semiconductor wafer comprises a first material (para 14, semiconductor material as listed), wherein the first portion of the protective structure comprises a second material different from the first material (para 21, Cu);
after forming the first portion of the protective structure, forming an interconnect structure on the semiconductor wafer (Fig. 3, interconnect structure including 47, 52, 57, 62, 72, 77, 82, 87, 92)
Gillis does not teach:
wherein the interconnect structure comprises a seal ring in the interconnect structure.
performing a singulation process to form an integrated circuit die by separating the semiconductor wafer, wherein the integrated circuit die comprises the protective structure, the seal ring, and the interconnect structure, and wherein the protective structure is between the seal ring and an edge of the integrated circuit die in a top down view.
Ma teaches wherein the interconnect structure comprises a seal ring in the interconnect structure (Fig. 1A and 4, inner most 105 structure guard ring 401 closest to and encircling circuit area 107, col 5 lines 45-65, materials include aluminum alloy)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Gillis to include the seal ring as taught by Ma in order to prevent moisture, contaminants, and crack propagation of the device.
Gillis as modified still lacks performing a singulation process to form an integrated circuit die by separating the semiconductor wafer, wherein the integrated circuit die comprises the protective structure, the seal ring, and the interconnect structure, and wherein the protective structure is between the seal ring and an edge of the integrated circuit die in a top down view.
Onuma teaches performing a singulation process to form an integrated circuit die by separating the semiconductor wafer, wherein the integrated circuit die comprises the protective structure, the seal ring, and the interconnect structure, and wherein the protective structure is between the seal ring and an edge of the integrated circuit die in a top down view (Fig. 18D, 78, 733, and cell area, para 156).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Gillis as modified to include the protective ring, seal ring, and IC edges as taught by Onuma in order to prevent moisture, contaminants, and crack propagation of the device.
Regarding claim 16, Gillis as modified teaches the limitations of claim 15 upon which claim 16 depends.
Gillis teaches further comprising forming a second portion of the protective structure, wherein the second portion of the protective structure extends through the interconnect structure (Fig. 3, second portion including structure of 51-91).
Regarding claim 17, Gillis as modified teaches the limitations of claim 16 upon which claim 17 depends.
Gillis teaches wherein the second portion of the protective structure comprises the second material (para 21, materials include Cu).
Gillis does not teach wherein the seal ring comprises a third material and wherein the second material is a same material as the third material.
Ma teaches wherein the seal ring comprises a third material (Fig. 1A and 4, inner most 105 structure guard ring 401 closest to and encircling circuit area 107, col 5 lines 45-65, materials include Cu)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Gillis as modified to include the materials as taught by Ma in order to improve the manufacturing principles and reliability of the device.
Regarding claim 18, Gillis as modified teaches the limitations of claim 15 upon which claim 18 depends.
Gillis does not teach wherein the protective structure has a frame shape in the top down view, wherein the seal ring has a frame shape in the top down view, and wherein the protective structure encloses the seal ring in the top down view.
Onuma teaches wherein the protective structure has a frame shape in the top down view, wherein the seal ring has a frame shape in the top down view, and wherein the protective structure encloses the seal ring in the top down view (Fig. 18D, 78, 733, and cell area, para 156).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Gillis as modified to include the protective ring, seal ring, and IC edges as taught by Onuma in order to prevent moisture, contaminants, and crack propagation of the device.
Regarding claim 19, Gillis as modified teaches the limitations of claim 15 upon which claim 19 depends.
Gillis teaches wherein a horizontal surface of the first portion of the protective structure is in contact and at least partially covered by the interconnect structure (Fig. 4A, 46 horizontal surface in contact with and partially covered by interconnect structure including 40), wherein the horizontal surface of the first portion of the protective structure is disposed below a horizontal surface of the semiconductor wafer (Fig. 3, portion of 46 disposed below 10), and wherein the seal ring is in contact with the horizontal surface of the semiconductor wafer (Fig. 1B, 105 in contact with horizontal surface of 108).
Claims 10, 11, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gillis et al (US Publication 20100237472) in view of Ma et al (US Patent 6509622), Onuma (US Publication 20210104473), and Lin et al (US Publication 20120199965).
Regarding claims 10 and 20, Gillis as modified teaches the limitations of claims 7 and 15 upon which these claims depend.
Gillis does not teach:
[claim 10] further comprising an encapsulant, wherein the encapsulant comprises a polymer.
[claim 20] further comprising forming an encapsulant around the integrated circuit die, wherein a coefficient of thermal expansion of the encapsulant is larger than a coefficient of thermal expansion of the integrated circuit die.
Lin teaches:
claim 10] further comprising an encapsulant, wherein the encapsulant comprises a polymer (para 49, encapsulant 146 polymer).
[claim 20] further comprising forming an encapsulant around the integrated circuit die, wherein a coefficient of thermal expansion of the encapsulant is larger than a coefficient of thermal expansion of the integrated circuit die. (para 49, encapsulant 146 polymer).
The coefficient of thermal expansion (CTE) for polymer semiconductors varies significantly based on their specific chemical composition, molecular structure, and manufacturing processes. Values for general polymers typically fall in the range of 50–200 ppm/°C, which is substantially higher than traditional inorganic semiconductors like silicon (2.33–4.15 ppm/K).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Gillis as modified to include the polymer encapsulant as taught by Lin in order to improve the manufacturing principles and operability of the device.
Regarding claim 11, Gillis as modified teaches the limitations of claim 10 upon which claim 11 depends.
Gillis does not teach wherein the first integrated circuit die is one of one or more integrated circuit dies, wherein the one or more integrated circuit dies have a first total area in a top down view, wherein the encapsulant has a second total area in the top down view, and wherein a ratio of the first total area to the second total area is in a range from 2 to 3.
Onuma teaches wherein the first integrated circuit die is one of one or more integrated circuit dies, wherein the one or more integrated circuit dies have a first total area in a top down view, wherein the encapsulant has a second total area in the top down view, and wherein a ratio of the first total area to the second total area is in a range from 2 to 3 (Fig. 18D and 20, para 154, passivation layer 990 area 2 to 3 times larger than area of cell array).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Gillis as modified to include the IC die and associated areas as taught by Onuma in order to improve the manufacturing principles and operability of the device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 7, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818