DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 7-17, 21-29 have been considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7-10, 13-17, and 30 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification as filed fails to provide support for the claim limitation of the last 5 lines of claim 7. Paragraph 91 recites that nanoscale structure 320 and HA structure 316 comprise the same dielectric material, and further recites 320 may be filled with a first dielectric, followed by a subsequent photolithographic process to form the pyramidal recess 414, and then 414 is filled with a second dielectric. The claim recites a different order of steps which forms an array of nanoscale holes (line 14), etching the pyramidal pattern, depositing an additional dielectric into the pyramidal pattern (line 18), and then depositing a dielectric material in the array of nanoscale holes and in the HA structure.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21, 23, 26-28, 31, and 32 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US PGPub 2022/0190010; hereinafter “Wang”).
Re claim 21: Wang teaches (e.g. fig. 4 and 2C) a method, comprising: forming a photodiode (CMOS image sensor; e.g. paragraph 19; hereinafter “PD”) within a substrate (Si substrate; e.g. paragraph 55; hereinafter “S”); forming a high absorption (HA) structure (11C the deeper antireflection layer AR; e.g. paragraph 53; hereinafter “HAS”) over the photodiode (PD); wherein the HA structure (HAS) has an approximately pyramidal shape (inverted pyramid; e.g. paragraph 53), extends into the substrate (S) and is at least partially filled with a dielectric material (SiO2 fills the inside of the inverted pyramids; e.g. paragraph 53; hereinafter “DM”); and forming an array of nanoscale structures (12C shallow antireflection layer AR; e.g. paragraph 53; hereinafter “NS”) at least partially surrounding (NS surrounds HAS) the HA structure (13), wherein the array of nanoscale structures (NS) are approximately spaced at regular intervals (see fig. 2C) and comprise rectangular holes (12C has a rectangular opening) filled with the dielectric material (DM).
Re claim 23: Wang teaches the method of claim 21, wherein each nanoscale structure (NS) has a cross-section that is approximately square (fig. 2C shows 11C has a square shape from above).
Re claim 26: Wang teaches the method of claim 21, further comprising: forming an isolation structure (deep trench isolation DTI as shown in fig. 3C; hereinafter “DTI”) that surrounds the photodiode (PD), wherein a ratio of a depth of the isolation structure (DTI) from a top of the substrate (S) to a depth of the photodiode (PD) from the top of substrate is in a range from approximately 0.5 to approximately 0.8 (PD is 75% of the depth of deep trench isolation DTI).
Re claim 27: Wang teaches (e.g. fig. 4 and 2C) a method, comprising: forming a photodiode (CMOS image sensor; e.g. paragraph 19; hereinafter “PD”) within a substrate (Si substrate; e.g. paragraph 55; hereinafter “S”); and forming an array of nanoscale structures (12C shallow antireflection layer AR; e.g. paragraph 53; hereinafter “NS”) over the photodiode (PD), wherein the array of nanoscale structures (NS) are approximately spaced at regular intervals (see fig. 2C) and comprise rectangular holes (12C has a rectangular opening) filled with a dielectric material (SiO2 fills the inside of the inverted pyramids; e.g. paragraph 53; hereinafter “DM”); and forming a high absorption (HA) structure (11C the deeper antireflection layer AR; e.g. paragraph 53; hereinafter “HAS”) over the photodiode (PD), wherein the HA structure (HAS) has an approximately pyramidal shape (inverted pyramid; e.g. paragraph 53), extends into the substrate (S), and is at least partially filled with the dielectric material (DM).
Re claim 28: Wang teaches the method of claim 27, further comprising: forming an isolation structure (deep trench isolation DTI as shown in fig. 3c) that surrounds the photodiode (PD), wherein a ratio of a depth of the isolation structure (DTI) from a top of the substrate (S) to a depth of the photodiode (PD) from the top of substrate is in a range from approximately 0.5 to approximately 0.8 (DTI is approximately 75% of the depth of deep trench isolation DTI).
Re claim 31: Wang teaches the method of claim 21, wherein the HA structure (HAS) is configured to reflect infrared light toward the photodiode (PD), and the array of nanoscale structures (NS) is configured to reflect visible light toward the photodiode (PD). As discussed in MPEP 2112.01(i) when the structure of the prior art is substantially identical to that of the claimed structure, claimed properties are presumed to be present.
Re claim 32: Wang teaches the method of claim 27, wherein the HA structure (HAS) is configured to reflect infrared light toward the photodiode (PD), and the array of nanoscale structures (NS) is configured to reflect visible light toward the photodiode (PD). As discussed in MPEP 2112.01(i) when the structure of the prior art is substantially identical to that of the claimed structure, claimed properties are presumed to be present.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22, 24, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claims 21 and 27, respectively, above, and further in view of Wells (US PGPub 2006/0281266).
Re claim 22, 24, 29: Wang teaches substantially the entire method of claim 21 or 27 except explicitly teaching, wherein each nanoscale structure (NS of Wang) has a width that is in a range from approximately 10 nanometers (nm) to approximately 40 nm.
Wells teaches each nanoscale structure (20 of Zang) has a width that is in a range from approximately 10 nanometers (nm) to approximately 40 nm (275 of Wells has a pitch that is a quarter pitch of 124,145 which can be 100-200nm, therefore the spacing between each of 275 is 25-50nm; e.g. paragraphs 66, 83 and 89 of Wells).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the method as taught by Wells in the device of Wang in order to have the predictable result of using a known method for forming nanoscale mask patterns which has reduced variation (see paragraph 45 of Wells).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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