Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant's arguments filed 12/16/25 have been fully considered but they are not persuasive.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-11 is/are stand rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yeh et al. (U.S. Patent Publication No. 2022/0310532), as previously applied.
Referring to figures 12-, Yeh et al. teaches a carrier substrate, comprising:
a first circuit structure (322a/324a) comprising a first dielectric layer (322a) and a first circuit layer (324a) formed on the first dielectric layer (see figure 12a), wherein the first circuit structure is defined with a plurality of first routing regions on an outermost side of the first dielectric layer, such that one of the plurality of first routing regions is defined as a first target region (see figure 12a); and
a second circuit structure (322b/324b) disposed on a side of the first circuit structure, and the second circuit structure comprising a second dielectric layer (322b) and a second circuit layer (324b) formed on the second dielectric layer, wherein the second circuit structure is defined with a plurality of second routing regions on an outermost side of the second dielectric layer, such that one of the plurality of second routing regions is defined as a second target region with the same shape and area as the first target region, and a position of the first target region and a position of the second target region are overlapped and aligned with each other, so that a difference between a routing ratio of the first circuit layer on the first target region and a routing ratio of the second circuit layer on the second target region is within 10% (see figure 12a, it is noted that the same structure would provide the same routing ratio),
wherein the first circuit structure (322a/324a) is served as an outer side of the carrier substrate (300), and the second circuit structure (322b/324b) is served as another outer side of the carrier substrate (see figure 12).
Regarding to claim 2, a core structure (310), wherein the second circuit structure is bonded to the first circuit structure via the core structure, such that the first circuit structure and the second circuit structure are disposed on opposing sides of the core structure respectively (see figure 12a).
Regarding to claim 3, the core structure (310) has a first surface and a second surface opposing the first surface, and the core structure has at least one conductive via (314) in communication with the first surface and the second surface, such that the first circuit structure and the second circuit structure are disposed on the first surface and the second surface of the core structure respectively, and the first circuit structure and the second circuit structure are electrically connected to the conductive via (see figure 12a).
Regarding to claim 4, wherein among the plurality of first routing regions, the first routing region at one corner of a surface of the first dielectric layer is served as the first target
Region (304, see figure 12a).
Regarding to claim 5, the routing ratios of the first circuit layer on any two of the plurality of first routing regions are different from each other (see figure 12a, paragraph# 119).
Regarding to claim 6, wherein at least one of the plurality of first routing regions is used as a chip-placement region for disposing chips, and the routing ratio of the first circuit layer on the chip-placement region is greater than the routing ratio of the first circuit layer on any other one of the plurality of first routing regions (see figure 13a).
Regarding to claim 7, wherein at least one of the plurality of first routing regions is used as a chip-placement region for disposing chips, and the routing ratio of the first circuit layer on the chip-placement region is at least 70% (see figure 12a, paragraph# 119).
Regarding to claim 8, the chip-placement region comprises a plurality of the first routing regions (see figure 13a).
Regarding to claim 9, wherein a difference between the routing ratio of the first circuit layer on the outermost side of the first dielectric layer and the routing ratio of the second circuit layer on the outermost side of the second dielectric layer is within 10% (see figure 12a).
Regarding to claim 10, the first circuit structure and the second circuit structure are directly in contact with and bonded to each other (see figure 12a).
Regarding to claim 11, wherein a part of the plurality of first routing regions is defined as the first target region, and another part of the plurality of first routing regions is defined as a third target region, wherein a part of the plurality of second routing regions is defined as the second target region, and another part of the plurality of second routing regions is defined as a fourth target region, wherein a difference between the routing ratio of the first circuit layer on the third target region and the routing ratio of the second circuit layer on the fourth target region is more than 10% (302, 304, see figure 12a).
Response to Arguments
Applicant's arguments filed 12/16/25 have been fully considered but they are not persuasive.
Applicant contends that Yeh fails to disclose "a difference between a routing ratio of the first circuit layer on the first target region and a routing ratio of the second circuit layer on the second target region is within 10%" in claim 1. This is found not persuasive because on paragraph# 119, the comparison between regions 304 and 302 which is different from the instant invention. The instant invention regions refer to the ratio between the 324A and 324B in the target regions 304 (top portion is the first target region, bottom portion is the second target region). Since figure 12 shows the same structure, therefore it would provide the same ratio within 10% (see paragraph# 108).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893