DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 10/16/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fumitake (CN-103915387-B with English translation for citation purposes).
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Regarding claim 16, Fumitake discloses a method for forming a semiconductor structure, comprising: receiving a substrate Fig 14, 10 comprising a first region Fig 14, PMOS and a second region Fig 14, NMOS ;forming a first FET device in the first region and a second FET device in the second region Fig 14;forming a first gate trench Fig 3, 301 in the first FET device and a second gate trench Fig 3, 302 in the second FET device; forming a first high-k dielectric layer Fig 3, 401 in the first gate trench and a second high-k dielectric layer Fig 3, 401 in the second gate trench; forming a first work function metal layer Fig 4, 422 in the first gate trench and a second work function metal layer Fig 4, 422 in the second gate trench; removing a portion of the first work function metal layer from the first gate trench Fig 8; and filling the first gate trench with a first gap-filling metal layer Fig 14, 601 and filling the second gate trench with a second gap-filling metal layer Fig 14, 602,wherein a width of a top surface of the first gap-filing metal layer is greater than a width of a top surface of the second gap-filling metal layer Fig 14.
Regarding claim 17, Fumitake discloses wherein the first work function metal layer and the second work function metal layer comprise a same material Page 6 translation.
Regarding claim 18, Fumitake discloses wherein the removing of the portion of the first work function metal layer further comprises: forming a first sacrificial layer Fig 5, 404 in the first gate trench in the first region, wherein a top surface of the first sacrificial layer is lower than an opening of the first gate trench Fig 7 ;forming a second sacrificial layer Fig 5, 405 in the second region; and removing the portion of the first work function metal layer exposed through the first sacrificial layer Fig 8.
Regarding claim 19, Fumitake discloses forming a first intervening metal layer Fig 14, 410 in the first gate trench, wherein a portion of the first intervening metal layer is in contact with the first high-k dielectric layer Fig 7, and a portion of the first intervening metal layer is in contact with a topmost portion of the first work function metal layer Fig 7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20-30 are rejected under 35 U.S.C. 103 as being unpatentable over Fumitake (CN-103915387-B with English translation for citation purposes) in view of Fumitake (CN-103915386-B with English translation for citation purposes).
Regarding claim 20, Fumitake CN-103915387-B discloses forming a second intervening metal layer in the second gate trench. Fumitake (CN-103915387-B with English translation for citation purposes) discloses all the limitations but silent on the arrangement of the intervening layer relative to the high k dielectric layer. Whereas Fumitake (CN-103915386-B) discloses wherein the second intervening metal layer Fig 12, 211 is entirely separated from the second high-k dielectric layer Fig 12, 206 NMOS area. Fumitake (CN-103915387-B and CN-103915386-B) are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fumitake (CN-103915387-B) because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the Fumitake (CN-103915387-B) and incorporate the teachings of Fumitake (CN-103915386-B) to improve device performance and prevent diffusion.
Regarding claim 21, Fumitake CN-103915387-B discloses method for forming a semiconductor structure, comprising: forming a first FET device and a second FET device over a substrate Fig 14;forming a first gate trench in the first FET device Fig 14, PMOS and a second gate trench in the second FET device Fig 14, NMOS; forming a first high-k dielectric layer Fig 3, 401 in the first gate trench and a second high-k dielectric layer Fig 3, 401 in the second gate trench; forming a first work function metal layer Fig 4, 422 in the first gate trench and a second work function metal layer Fig 4, 422 in the second gate trench; removing a portion of the first work function metal layer from the first gate trench Fig 8;forming a first intervening metal layer Fig 14, 410 in the first gate trench and a second intervening metal layer Fig 14, 410 in the second gate trench; and filling the first gate trench with a first gap-filling metal layer Fig 14, 601 and filling the second gate trench with a second gap-filling metal layer Fig 14, 602,wherein the first intervening metal layer is in contact with the first high-k dielectric layer Fig 14. Fumitake CN-103915387-B discloses forming a second intervening metal layer in the second gate trench. Fumitake (CN-103915387-B with English translation for citation purposes) discloses all the limitations but silent on the arrangement of the intervening layer relative to the high k dielectric layer. Whereas Fumitake (CN-103915386-B) discloses wherein the second intervening metal layer Fig 12, 211 is entirely separated from the second high-k dielectric layer Fig 12, 206 NMOS area. Fumitake (CN-103915387-B and CN-103915386-B) are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fumitake (CN-103915387-B) because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the Fumitake (CN-103915387-B) and incorporate the teachings of Fumitake (CN-103915386-B) to improve device performance and prevent diffusion.
Regarding claim 22, Fumitake CN-103915387-B discloses wherein the first work function metal layer and the second work function metal layer comprise a same material Page 6 translation.
Regarding claim 23, Fumitake CN-103915386-B discloses wherein the first intervening metal layer and the second intervening metal layer comprise a same material Page 7-8 translation.
Regarding claim 24, Fumitake CN-103915387-B discloses wherein the removing of the portion of the first work function metal layer further comprises: forming a first sacrificial layer Fig 5, 404 in the first gate trench in the first region and a second sacrificial layer Fig 5, 405 in the second gate trench, wherein a top surface of the first sacrificial layer is lower than a top surface of the second sacrificial layer Fig 7; and removing the portion of the first work function metal layer exposed through the first sacrificial layer Fig 8.
Regarding claim 25, Fumitake CN-103915387-B wherein the first intervening metal layer is in contact with a topmost portion of the first work function metal layer Fig 14.
Regarding claim 26, Fumitake CN-103915387-B discloses wherein a topmost portion of the first work function metal layer is lower than a topmost portion of the first high-k dielectric layer, a topmost portion of the first intervening layer, and a top surface of the first gap-filling layer Fig 14.
Regarding claim 27, Fumitake CN-103915386-B discloses wherein a topmost portion of the second work function metal layer, a topmost portion of the second high-k dielectric layer, a topmost portion of the second intervening layer, and a top surface of the second gap-filling layer are aligned with each other Fig 12.
Regarding claim 28, Fumitake CN-103915387-B discloses wherein the topmost portion of the first work function metal layer is lower than the topmost of the second work function metal layer, the topmost portion of the second high-k dielectric layer, the topmost portion of the second intervening layer, and the top surface of the second gap-filling layer Fig 14.
Regarding claim 29, Fumitake CN-103915387-B discloses wherein the first gap-filling metal layer comprises a T- shaped configuration Fig 14.
Regarding claim 30, Fumitake CN-103915387-B discloses wherein the second gap-filling metal layer comprises an I-shaped configuration Fig 14.
Claims 31-33, 35 are rejected under 35 U.S.C. 103 as being unpatentable over Fumitake (CN-103915387-B with English translation for citation purposes) in view of Song et al (US Publication No. 2018/0226300).
Regarding claim 31, Fumitake CN-103915387-B discloses a method for forming a semiconductor structure, comprising: forming a first FET device and a second FET device over a substrate Fig 14;forming a first gate trench in the first FET device Fig 14, PMOS and a second gate trench in the second FET device Fig 14, NMOS; forming a first high-k dielectric layer Fig 3, 401 in the first gate trench and a second high-k dielectric layer Fig 3, 401 in the second gate trench; forming a first metal layer Fig 5, 422 in the first gate trench and a second metal layer Fig 5, 422 in the second gate trench; forming a third metal layer Fig 5, 403 over the first metal layer Fig 5, 422 and a fourth metal layer Fig 5, 403 over the second metal layer Fig 5, 422, wherein a thickness of the third metal layer is equal to a thickness of the fourth metal layer Fig 5; removing a portion of the first metal layer Fig 11, 422 and a portion of the third metal layer Fig 11, 403 from the first gate trench and removing a portion of the second metal layer and a portion of the fourth metal layer from the second gate trench Fig 7; and filling the first gate trench with a first gap-filling metal layer Fig 14, 601 and filling the second gate trench with a second gap-filling metal layer Fig 14, 602, wherein a width of a top surface of the first gap-filing metal layer is greater than a width of a top surface of the second gap-filling metal layer Fig 14.Fumitaki discloses all the limitations but silent on the different thickness of the work function layer. Whereas Song discloses forming a first high-k dielectric layer Fig 2, 170 in the first gate trench and a second high-k dielectric layer Fig 2, 270 in the second gate trench; forming a first metal layer Fig 2, 180 in the first gate trench and a second metal layer Fig 2, 280 in the second gate trench, wherein a thickness of the first metal layer is less than a thickness of the second metal layer Fig 2. Fumitake (CN-103915387-B) and Song are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fumitake (CN-103915387-B) because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the Fumitake (CN-103915387-B) and incorporate the teachings of Song to adjust the device threshold voltage.
Regarding claim 32, Fumitake CN-103915387-B discloses wherein the first metal layer and the second metal layer comprise a same material Page 6 translation.
Regarding claim 33, Fumitake CN-103915387-B discloses wherein the third metal layer and the fourth metal layer comprise a same material Page 7 translation.
Regarding claim 35, Fumitake CN-103915387-B discloses wherein the removing of the portion of the first metal layer and the portion of the third metal layer from the first gate trench and the removing the portion of the second metal layer and the portion of the fourth metal layer from the second gate trench further comprises:forming a first sacrificial layer Fig 5, 404 in the first gate trench and a second sacrificial layer Fig 5, 405 in the second gate trench, wherein a top surface of the first sacrificial layer is lower thanan opening of the first gate trench, and a top surface of the second sacrificial layer is lower than an opening of the second gate trench Fig 7; and removing the portion of the first metal layer and the portion of the third metal layer exposed through the first sacrificial layer Fig 8, and removing the portion of the second metal layer and the portion of the fourth metal layer exposed through the second sacrificial layer Fig 8.
Claims 31-33, 35 are rejected under 35 U.S.C. 103 as being unpatentable over Fumitake (CN-103915387-B with English translation for citation purposes) in view of Song et al (US Publication No. 2018/0226300) and in further view of Fumitake (CN-103915386-B with English translation for citation purposes).
Regarding claim 34, Fumitake CN-103915387-B discloses all the limitations except for the arrangement of the layers. Whereas Fumitake CN-103915386-B discloses wherein a distance between a bottom surface of the first gap-filling metal layer and a top surface of the first high-k dielectric layer is less than a distance between a bottom surface of the second gap-filling metal layer and a top surface of the second high-k dielectric layer Fig 12. Fumitake (CN-103915387-B and CN-103915386-B) are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fumitake (CN-103915387-B) because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the Fumitake (CN-103915387-B) and incorporate the teachings of Fumitake (CN-103915386-B) to improve device performance.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811