DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/13/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 5-13, and 16-17 are rejected under U.S.C. 103 as being unpatentable over Guo et al.; US 2020/0161131 A1; 03/2019 in view of Jiang et al.; US 9748264 B1; 05/2016
Claim 2: Guo and Jiang disclose the method of claim 8 ( as discussed below).
Guo teaches the silicon substrate ( Fig. 6 #200 ) comprises a single-crystal silicon ( [0049] the monocrystalline substrate material (Si) of the bottom surface ) from which the epitaxial silicon core is grown ( [0046] a selective epitaxial growth process is used to form the epitaxial silicon structure (SEG) in the trench ) through the channel hole ( Fig. 6 #205 ).
Claim 3: Guo and Jiang disclose the method of claim 8 ( as discussed below).
Guo teaches the alternating material layers ( Fig. 6 #204 ) comprise alternating layers of an oxide material ([0057] the material of the second insulating layer #203 is silicon oxide ) and a nitride material ( [0057] the material of the first insulating layer #202 is silicon nitride ).
Claim 5: Guo and Jiang disclose the method of claim 8 ( as discussed below).
Guo teaches the epitaxial silicon core ( Fig. 6 #206) extends into the silicon substrate ( Fig. 6 #200).
Claim 6: Guo and Jiang disclose the method of claim 8 ( as discussed below).
Guo teaches epitaxially growing a layer of epitaxial silicon ( [0036] forming method of the epitaxial layer of the present invention ) that extends beyond the channel hole ( [0036] the first annealing process is performed after forming the channel holes and the trenches ), wherein the layer of epitaxial silicon ( [0064] an epitaxial layer is formed in the trench #206 ) is between the silicon substrate ( Fig. 6 #200 ) and the plurality of alternating material layers ( Fig. 6 #204 ), and the layer of epitaxial silicon ( Fig. 6 #206 ) connects the epitaxial silicon core ( [0050] epitaxial silicon structure #109 ) to a plurality of other channels ( [0063] the stacked structure #204 is etched to form a plurality of channel holes #205 passing through the stacked structure #204; the substrate #200 situated at bottoms of the channel holes #205 is etched along the channel holes #205, so as to form a plurality of trenches #206 in the substrate #200 ) in the memory structure ( [0088] a storage structure is formed on the epitaxial layer #210 ).
Claim 7: Guo and Jiang disclose the method of claim 6 ( as discussed above).
Guo teaches forming a support structure ( Fig. 10 #210 ) that extends through the plurality of alternating material layers ( Fig. 10 #204 ) and the layer of epitaxial silicon ( Fig. 10 #203 ) and extends into the silicon substrate ( Fig. 10 #200 ).
Claim 8: Guo discloses a method of fabricating a three-dimensional (3D) NAND memory structure ( [0051] a forming method of a 3D NAND memory ), the method comprising:
forming a plurality of alternating material layers ( [0057] A material of the first insulating layer #202 is different from a material of the second insulating layer #203 ) arranged in a vertical stack ( [0063] the stacked structure #204 ) on a silicon substrate ( Fig. 6 #200 );
etching a channel hole ( [0063] etched to form a plurality of channel holes #205 ) that extends through the plurality of alternating material layers ( [0063] passing through the stacked structure #204 ) to the silicon substrate ( Fig. 6 #200 );
Guo does not appear to disclose forming a tunneling layer around the channel hole covering vertical sidewalls of the channel hole and contacting the plurality of alternating material layers; and epitaxially growing an epitaxial silicon core up from the silicon substrate to fill the channel hole inside of the tunneling layer to form an epitaxial silicon channel for a memory element in the 3D NAND structure.
However, Jiang teaches forming a tunneling layer ( Fig. 1E tunneling layer 185 around the channel hole ( Fig. 1E isolation trench 160 ) covering vertical sidewalls of the channel hole ( as shown in Fig. 1E ) and contacting the plurality of alternating material layers ( as shown in Fig. 1E );
epitaxially growing an epitaxial silicon core ( Fig. 1E epitaxial structure 170 ) up from the silicon substrate ( Fig. 1E substrate 110 ) to fill the channel hole ( Fig. 1E #160 ) inside of the tunneling layer ( Fig. 1E #185 ) to form an epitaxial silicon channel for a memory element in the 3D NAND structure ( Col. 6 lines 36 – 41 the epitaxial structure 170 is formed between the isolation trench 160 and the substrate 110 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jiang with Guo to implement forming a tunneling layer around the channel hole covering vertical sidewalls of the channel hole and contacting the plurality of alternating material layers; and epitaxially growing an epitaxial silicon core up from the silicon substrate to fill the channel hole inside of the tunneling layer to form an epitaxial silicon channel for a memory element in the 3D NAND structure because this improves electrical characteristics, enhances reliability, and reduces leakage.
Claim 9: Guo and Jiang disclose the method of claim 8 ( as discussed above).
Guo teaches etching a slit ( [0090] formed at positions corresponding to the removed first insulating layers #202 ) in the memory structure ( as shown in Fig. 6 ) that extends through the plurality of alternating material layers ( Fig. 6 #204 ) into a sacrificial nitride layer ( Fig. 6 #202 ) that is above the silicon substrate ( Fig. 6 #200 ).
Claim 10: Guo and Jiang disclose the method of claim 9 ( as discussed above).
Guo teaches exposing the sacrificial nitride layer ( Fig. 6 #202 ) to an etch process that is configured to selectively etch the sacrificial nitride layer ( [0091] the first insulating layers #202 are removed by a wet etching process).
Claim 11: Guo and Jiang disclose the method of claim 10 ( as discussed above).
Guo teaches removing a portion of the tunneling layer ( Fig. 6 #203 ) that is exposed after removing the sacrificial nitride layer ( [0091] an etching rate for the first insulating layer #202 is much greater than the etching rates for the second insulating layer #203 and the epitaxial layer #210 ).
Claim 12: Guo and Jiang disclose the method of claim 10 ( as discussed above), further comprising: epitaxially growing an epitaxial silicon layer ( [0064] an epitaxial layer is formed in the trench #206 ) from the silicon substrate ( Fig. 6 #200 ) to replace the sacrificial nitride layer ( Fig. 6 #202 ).
Claim 13: Guo and Jiang disclose the method of claim 8 ( as discussed above ).
Guo teaches etching a second channel hole ( Fig. 10 two holes shown as #205 ) that extends through the plurality of alternating material layers ( Fig. 10 #204 ) into the silicon substrate ( Fig. 10 #200 ); and filling the second channel hole ( Fig. 10 #205 ) with a gap fill material as a support structure ( Fig. 10 #209 ).
Claim 16: Guo and Jiang disclose the method of claim 7 ( as discussed above).
Guo teaches the support structure comprises a gap-fill material ( [ 0090] a plurality of metal gates #211 ) in a slit ( [0090] formed at positions corresponding to the removed first insulating layers #202 ) in the memory structure ( as shown in Fig. 11 ).
Claim 17: Guo and Jiang disclose the method of claim 16 ( as discussed above).
Guo teaches alternating slits ( as shown in Fig. 11 ) in the memory structure form a plurality of support structures ( as shown in Fig. 11 ).
Claims 15 and 18 are rejected under U.S.C. 103 as being unpatentable over Guo et al.; US 2020/0161131 A1; 03/2019 in view of Jiang et al.; US 9748264 B1; 05/2016 as it relates to claim 7 above and further in view of Lee; US 2021/0174839 A1; 05/2019
Claim 15: Guo and Jiang disclose the method of claim 7 ( as discussed above).
Neither Guo nor Jiang appear to disclose the support structure comprises a metal that fills one of a plurality of channel holes.
However, Lee teaches the support structure ( Fig. 8: support pillars SP ) comprises a metal that fills one of a plurality of channel holes ( [0065] the support pillars SP may include polysilicon, metal, TiN or SiCN ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Guo and Jiang to implement the support structure comprises a metal that fills one of a plurality of channel holes because metal provides a low-resistance electrical connection and facilitates efficient operation.
Claim 18: Guo, Jiang and Lee disclose the method of claim 17 ( as discussed above), wherein the plurality of support structures comprises a combination of: a gap-fill material ( [ 0090] a plurality of metal gates #211 ) in one or more slits in the memory structure ( as shown in Fig. 11 ).
Neither Guo nor Jiang appear to disclose a metal that fills one or more of the plurality of channel holes.
However, Lee teaches a metal that fills one or more of the plurality of channel holes ( [0065] the support pillars SP may include polysilicon, metal, TiN or SiCN ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Guo and Jiang to implement a metal that fills one or more of the plurality of channel holes because metal provides a low-resistance electrical connection and facilitates efficient operation.
Response to Amendment / Arguments
Applicant’s arguments, see pages 6 - 7 of remarks, filed 03/09/2026, with respect to the rejection(s) of claim 8 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Jiang.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights