DETAILED ACTION
Examiner Remarks
Due to clerical errors in the prior art rejections of the previous office action—a non-final rejection mailed 13 December 2025—a new non-final rejection is presented here, providing appropriate corrections and restarting the associated shortened statutory period for reply.
For clarity of record, said clerical errors were in the form of referencing the prior art authors as “REF1” and “REF2” as opposed to their last names, PACHAMUTHU and KANG, respectively.
No other changes have been made.
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with paragraph numbers and line numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner are encouraged to fill out the online Automated Interview Request (AIR) form:
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
See MPEP § 502.03 & § 713.01(II) and Interview Practice for additional details.
Status of claims to be treated in this office action:
Pending: Claims 1 – 20
Independent: Claims 1 & 12
Amended: Claims 1 & 20
Withdrawn: Claims 1 – 11
Examined: Claims 12 – 20
Election/Restrictions
Applicant’s election without traverse of Invention II, corresponding to Claims 12 – 20, in the reply filed on 25 November 2025 is acknowledged.
Applicant’s election without traverse of Species VIII, corresponding to at least Fig. 9I, in the reply filed on 25 November 2025 is acknowledged.
Claims 1 – 11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species and/or invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 25 November 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 & 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 19,
the limitation “an epitaxial silicon core” is cited with the indefinite article. However, “an epitaxial silicon core” is also cited with the indefinite article in Claim 12, upon which this claim depends, making the antecedent basis unclear.
For the purposes of examination, the citation of “an epitaxial silicon core” in Claim 19 will be interpreted as “the epitaxial silicon core”.
Regarding Claim 20,
the limitation “an etch process that is configured to selectively etch the layer” is cited. However, a second layer for comparison to the layer is not cited, making the meaning of the adverb “selectively” unclear.
For the purposes of examination, the citation “an etch process that is configured to selectively etch the layer” will be interpreted as “an etch process that is configured to
Further, Claim 20 is dependent upon Claim 19, therefore inheriting its rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12 – 15 & 17 – 19 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by PACHAMUTHU (US 20150079765 A1).
Regarding Independent Claim 12 (Original),
PACHAMUTHU discloses:
A method of fabricating a three-dimensional (3D) NAND memory structure (PACHAMUTHU Abstract), the method comprising:
forming a layer on a silicon substrate (PACHAMUTHU Fig. 3A shows a layer 303 formed on a substrate 100—where 100 may be silicon, PACHAMUTHU ¶ [0028].);
etching a hole that extends through the layer to expose the silicon substrate (PACHAMUTHU Fig. 3F shows a hole 314—which may be formed via etching, PACHAMUTHU ¶ [0033]—that extends through the layer 303 to expose the silicon substrate 100.);
epitaxially growing epitaxial silicon for a channel from the silicon substrate through the hole (PACHAMUTHU Figs. 3H & 3I show epitaxial silicon 321—which may be epitaxially grown, PACHAMUTHU ¶ [0035]—for a channel 1—channel portions 1B shown, PACHAMUTHU ¶ [0036]—from the silicon substrate 100 through the hole 314.);
and forming the 3D NAND memory structure over the layer and the substrate (PACHAMUTHU Fig. 6E shows the 3D NAND memory structure 120 formed over the layer 303 and the substrate 100.)
such that a channel hole in the 3D NAND memory structure comprises an epitaxial silicon core grown from the epitaxial silicon (PACHAMUTHU Fig. 5G shows a channel hole 81 in the 3D NAND memory structure 120 comprises a hollow core 519—which may be silicon, PACHAMUTHU ¶ [0056], formed via epitaxial growth, PACHAMUTHU ¶ [0019]—grown from the epitaxial silicon 321.).
Regarding Claim 13 (Original),
PACHAMUTHU discloses all of the limitations of Claim 12, upon which this claim depends.
PACHAMUTHU further discloses:
wherein the epitaxial silicon is grown above a top surface of the layer (PACHAMUTHU Figs. 3H & 3I show the epitaxial silicon 321 is grown above a top surface of the layer 303.).
Regarding Claim 14 (Original),
PACHAMUTHU discloses all of the limitations of Claim 12, upon which this claim depends.
PACHAMUTHU further discloses:
wherein the layer comprises a silicon oxide layer (PACHAMUTHU ¶ [0028] teaches the layer 303 may comprise silicon oxide.).
Regarding Claim 15 (Original),
PACHAMUTHU discloses all of the limitations of Claim 12, upon which this claim depends.
PACHAMUTHU further discloses:
wherein forming the 3D NAND memory structure over the layer and the substrate comprises:
forming a nitride layer over the layer and the epitaxial silicon (PACHAMUTHU Fig. 5A shows a layer 501—which may be silicon nitride, PACHAMUTHU ¶ [0043]—formed over the layer 303 and the epitaxial silicon 321.).
Regarding Claim 17 (Original),
PACHAMUTHU discloses all of the limitations of Claim 12, upon which this claim depends.
PACHAMUTHU further discloses:
wherein forming the 3D NAND memory structure over the layer and the substrate comprises:
forming a plurality of alternating nitride and oxide layers over the layer and the substrate (PACHAMUTHU Fig. 5A shows a plurality of alternating nitride 121 and oxide 19 layers formed over the layer 303 and the substrate 100).
Regarding Claim 18 (Original),
PACHAMUTHU discloses all of the limitations of Claim 17, upon which this claim depends.
PACHAMUTHU further discloses:
wherein forming the 3D NAND memory structure over the layer and the substrate further comprises:
etching a channel hole through the plurality of alternating nitride and oxide layers to expose the epitaxial silicon (PACHAMUTHU Figs. 5C & 5D show a channel hole 81—which may be formed via etching, PACHAMUTHU ¶ [0046] & [0049]—through the plurality of alternating nitride 121 and oxide 19 layers to expose the epitaxial silicon 321.);
and epitaxially growing the epitaxial silicon up through the channel hole to form the epitaxial silicon core of the channel hole (PACHAMUTHU Fig. 5G shows the epitaxial silicon 321 grown—as per PACHAMUTHU ¶ [0019]—up through the channel hole 81 to form the epitaxial silicon core 519 of the channel hole 81.).
Regarding Claim 19 (Original),
PACHAMUTHU discloses all of the limitations of Claim 12, upon which this claim depends.
PACHAMUTHU further discloses:
wherein forming the 3D NAND memory structure over the layer and the substrate comprises:
forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate (PACHAMUTHU Fig. 5A shows a plurality of alternating material layers 70 formed and arranged in a vertical stack on a silicon substrate 100.);
etching a channel hole that extends through the plurality of alternating material layers to the epitaxial silicon (PACHAMUTHU Figs. 5C & 5D show a channel hole 81—which may be formed via etching, PACHAMUTHU ¶ [0046] & [0049]—that extends through the plurality of alternating material layers 70 to the epitaxial silicon 321.);
forming a tunneling layer around the channel hole contacting the plurality of alternating material layers (PACHAMUTHU Fig. 5E shows a tunneling layer 11 formed around the channel hole 81 indirectly contacting the plurality of alternating material layers 70 via layers 7 & 9.);
and epitaxially growing the epitaxial silicon core from the epitaxial silicon through the channel hole inside of the tunneling layer (PACHAMUTHU Fig. 5G shows the epitaxial silicon core 519 epitaxially grown—as per PACHAMUTHU ¶ [0019]—from the epitaxial silicon 321 through the channel hole 81 inside of the tunneling layer 11.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over PACHAMUTHU.
Regarding Claim 16 (Original),
PACHAMUTHU discloses all of the limitations of Claim 15, upon which this claim depends.
PACHAMUTHU does not disclose:
wherein forming the 3D NAND memory structure over the layer and the substrate further comprises: polishing the nitride layer to remove surface variations caused by a difference in height between the layer and the epitaxial silicon.
However, while PACHAMUTHU does not disclose the fabrication steps:
growing the epitaxial silicon, then forming the nitride layer, then polishing to remove surface variations, then forming the 3D NAND memory structure,
PACHAMUTHU does disclose the fabrication steps:
growing the epitaxial silicon (PACHAMUTHU Fig. 3I: 321), then polishing to remove surface variations (PACHAMUTHU ¶ [0035]), then forming the nitride layer (PACHAMUTHU Fig. 5A: 501), then forming the 3D NAND memory structure (PACHAMUTHU Fig. 5A: 120).
Further, one of ordinary skill in the art could have perused any one of these known potential orderings of the above fabrication steps of PACHAMUTHU with a reasonable expectation of success. Therefore, PACHAMUTHU would arrive at the claimed invention, as cited above, as it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because, these inventions are of the same field of endeavor, and “a person of ordinary skill has a good reason to pursue the known options within his or her technique’s grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense”.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over PACHAMUTHU in view of KANG (US 20200312874 A1).
Regarding Claim 20 (Currently Amended),
PACHAMUTHU discloses all of the limitations of Claim 19, upon which this claim depends.
PACHAMUTHU further discloses:
further comprising:
etching a slit in the memory structure that extends through the plurality of alternating material layers into the layer (PACHAMUTHU Fig. 6B shows a slit 605—which may be formed via etching, PACHAMUTHU ¶ [0057]—in the memory structure 120 that extends through the plurality of alternating material layers 70 into the layer 303.);
exposing the layer to an etch process that is configured to
PACHAMUTHU does not disclose:
removing a portion of the tunneling layer that is exposed after removing the layer.
However, for a similar method, KANG discloses:
removing a portion of the tunneling layer that is exposed after removing the layer (KANG Fig. 10 shows a portion of 165—which comprises the tunneling layer 172, as shown in KANG Fig. 6B—removed that is exposed after removing the layer 132 in the previous step, as shown in KANG Fig. 9. Note also that 132 is comprised of silicon oxide, KANG ¶ [0045].).
That is, while PACHAMUTHU does not teach:
the forming of the source’s contact with the channel in the method of KANG—which would satisfy the above limitation—
PACHAMUTHU does teach:
the forming of the source’s contact with the channel in a known and competitive alternative method, as evidenced by the disclosure of PACHAMUTHU itself.
Further, one of ordinary skill in the art could have perused any one of these known potential methods for forming a source contact with the channel with a reasonable expectation of success. Therefore, PACHAMUTHU would arrive at the claimed invention, as cited above, as it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because, these inventions are of the same field of endeavor, and “a person of ordinary skill has a good reason to pursue the known options within his or her technique’s grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
RAJASHEKHAR (CN 113169179 A) discloses a highly analogous invention and reads on many of the claim elements of the instant application, including but not limited to a similar method of making source contacts to the channel for a 3D NAND device.
HU (CN 107887395 A) discloses a highly analogous invention and reads on many of the claim elements of the instant application, including but not limited to a similar method of making source contacts to the channel for a 3D NAND device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898