DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Remarks, filed 12/01/2025, with respect to the rejection(s) of claim 1 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su) in view of Yoo, Jong Ryeol (Pub No. US 20240339498 A1) (hereinafter, Yoo).
6. Applicant’s arguments, see Remarks, filed 12/01/2025, with respect to the rejection(s) of claim 4 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su) in view of Bomberger, Cory et al. (Pub No. US 20200312981 A1) (hereinafter, Bomberger).
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim 1, 3, 7-12 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su), and further in view of Yoo, Jong Ryeol (Pub No. US 20240339498 A1) (hereinafter, Yoo).
Su, Fig 2A, Forming stack of epitaxial layers over substrate
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Re Claim 1, (Currently Amended) Su teaches a method of manufacturing a semiconductor device, the method comprising:
forming a stack (Epitaxial stack; 120; Fig 2A; ¶[0019]) of epitaxially grown layers (Epitaxial layers; 122/124; Fig 2A; ¶[0019]) alternating between a first semiconductor material (Silicon (Si); 124; ¶[0019]) and a second semiconductor material (Silicon Germanium (SiGe); 122; ¶[0019]) that is etch selective (Per ¶[0061] sacrificial layer 122 and channel 124 are SiGe and silicon allowing for selective removal/etching) to the first semiconductor material;
Su, Fig 3A, Forming fins from epitaxial layers
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forming fin structures (Fins; 130; Fig 3A; ¶[0024]) from the stack, the fin structures including channel structures (Per ¶[0022] epitaxial layers 124 are referred to as channel layers) formed of the first semiconductor material;
Su, Figs 18B/18C, Forming source and drain structures on opposing ends of channels
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forming source/drain (S/D) structures (Source/drain epitaxial structures; 250S/250D; Fig 18C; ¶[0049]) on opposing ends (Opposing ends of fins 130 which comprise of channel structures, see Fig 18B; ¶[0049]) of the channel structures by epitaxially growing a third semiconductor material (Epitaxial material, e.g. Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material; ¶[0050]); and
forming a silicide (Metal silicide regions; 340; Fig 26C; ¶[0070]) around the S/D structures, and (See Fig 26C below)
before forming the silicide around the S/D structures, forming a sacrificial film (Sacrificial epitaxial structures/dielectric material/contact etch stop layer; 170/260/270; Figs 19B/19C; ¶[0057]) around and in direct contact with the S/D structures.
Su, Fig 26C, Forming silicide around the S/D structures
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However, Su does not teach before forming the silicide around the S/D structures, forming a sacrificial film around and in direct contact with the S/D structures by epitaxially growing a fourth semiconductor material that is etch selective to the third semiconductor material.
In the same field of endeavor, Yoo teaches before forming the silicide (Silicide pattern; 190; Fig 31; ¶[0092]) around the S/D structures (Epitaxial patterns/blocking film; 160/260/162; Fig 28; ¶[0032]), forming a sacrificial film (Sacrificial pattern; 164; Fig 28; ¶[0205]) around and in direct contact with the S/D structures by epitaxially growing a fourth semiconductor material (Per ¶¶[0151, 0180] blocking film 162 is epitaxially grown from epitaxial pattern 160 in order to subsequently grow sacrificial epitaxial pattern 164. Further, ¶[0083] discloses 160 may be a semiconducting material such as SiGe) that is etch selective to the third semiconductor material (Epitaxial material of epitaxial patterns/blocking film; 160/260/162; Fig 28; ¶[0032]; Note: Per ¶[0205] sacrificial pattern 164 is etch selective with respect to blocking film 162). (See Yoo Figs 28 and 31 below)
Yoo, Fig 28: Forming sacrificial layer over source/drain regions before the silicidation process
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Yoo, Fig 31: Forming the silicide pattern over the source/drain region
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to combined the method of manufacturing the semiconductor device comprising: before forming the silicide around the S/D structures, forming a sacrificial film around and in direct contact with the S/D structures by epitaxially growing a fourth semiconductor material that is etch selective to the third semiconductor material, as taught by Yoo, with the method of manufacturing the semiconductor device as taught by Su. One would have been motivated to do this with a reasonable expectation of success in order to increase the contact area between the source/drain regions and the silicide pattern. Further, increasing contact area improves the contact resistance of the source/drain region (Yoo, ¶[0092]).
Re Claim 3, (Currently Amended) Su teaches the method of claim 1, further comprising:
covering the sacrificial film (Sacrificial structures; 170; Fig 19B; ¶[0061]) with a dielectric film (Dielectric material; 260; Fig 19C; ¶[0057]; Dielectric film 260 of Fig 19C covers sacrificial structure 170 of Fig 19B being aligned cross-sections of semiconductor device of Fig 15A);
forming openings (Gate trenches; GT1; Figs 20A/20B; ¶[0060]) in the stack (Epitaxial stack; 120; Fig 2A; ¶[0019]) ; and
removing (Sacrificial structures 170 removed by selective wet etching process; ¶[0061]) the sacrificial film around the S/D structures.
Re Claim 7, (Original) Su teaches the method of claim 4, wherein:
the filler material (Patterned mask; 325; Fig 23C; ¶[0068]) covers the bulk semiconductor material (Backside via rail; 152; Fig 23C; ¶[0068]) and a sidewall (Sidewall of 300; Fig 24C) of the CESL (CESL; 300; Fig 24C; ¶[0066]) while forming the silicide (Metal silicide regions; 340; Fig 26C; ¶[0070]).
Re Claim 8, (Original) Su teaches the method of claim 1, further comprising:
forming a metal capping material (Source contact; 352; Fig 27C; ¶[0073]) around the silicide (Metal silicide regions; 340; Fig 26C; ¶[0070]).
Re Claim 9, (Original) Su teaches the method of claim 1, further comprising:
forming a protective film (Dielectric layer; 222; Figs 15B/15C; ¶[0043]) over the fin structures (Fins; 130; Fig 3A; ¶[0024]);
forming a dummy gate (Dummy gate electrodes; 224; Figs 15B/15C; ¶[0044]) over the protective film; and
patterning (Pattering dummy gate electrode to remove exposed portions of dielectric layer 222 while still remaining over fins 130; ¶[0044]) the dummy gate while the protective film protects the fin structures.
Re Claim 10, (Original) Su teaches the method of claim 9, wherein:
the dummy gate (Dummy gate electrodes; 224; Figs 15B/15C; ¶[0044]) is patterned in a direction (Vertical direction; Fig 18A) orthogonal (Orthogonal to horizontal surface of fins 130) to the fin structures (Fins; 130; Fig 18A; ¶[0024]).
Re Claim 11, (Original) Su teaches the method of claim 9, further comprising:
forming a hardmask material (Hard mask; 226/228; Fig 18B; ¶[0044]) over the dummy gate (Dummy gate electrodes; 224; Figs 15B/15C; ¶[0044]).
Re Claim 12, (Original) Su teaches the method of claim 1, further comprising:
forming a constraint material (First spacer layer/inner spacers; 232/240; Fig 19A; ¶¶[0045, 0048]) covering the fin structures (Fins; 130; Fig 3A; ¶[0024]), the constraint material including sidewall constraints (Inner spacers; 240; Fig 19A; ¶[0048]) and top constraints (First spacer layer; 232; Fig 19A; ¶[0045]) covering S/D regions (Source/drain epitaxial structures; 250S/250D; Fig 18C; ¶[0049]).
Re Claim 21, (New) Su teaches method of claim 1, wherein:
a portion (Contact etch stop layer; 270; Fig 21C; ¶[0057]) of the sacrificial film (Dielectric material/contact etch stop layer; 260/270; Fig 21C; ¶[0057]) is formed completely above the S/D structures (Source/drain epitaxial structures; 250S/250D; Fig 21C; ¶[0049]).
9. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su) in view of Yoo, Jong Ryeol (Pub No. US 20240339498 A1) (hereinafter, Yoo) as applied to claim 1 above, and further in view of Bomberger, Cory et al. (Pub No. US 20200312981 A1) (hereinafter, Bomberger).
Re Claim 4, (Currently Amended) Su teaches the method of claim 1, further comprising:
partially filling the at least one via opening with a filler material (Patterned mask; 325; Fig 23C; ¶[0068]) before forming the silicide (Metal silicide regions; 340; Fig 26C; ¶[0070]).
However, Su in view of Yoo does not teach forming at least one via opening in the stack to uncover a bulk semiconductor material below the stack.
In the same field of endeavor, Bomberger teaches forming at least one via opening (Second conductive contact structure; 436; Fig 4J; ¶[0063]) in the stack (Stack of nanowires/source or drain structures; 406’/422; Fig 4J; ¶[0058]) to uncover a bulk semiconductor material (Fin; 402; Fig 4J; ¶[0063]) below the stack.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have formed at least one via opening in the stack to uncover a bulk semiconductor material below the stack, as taught by Bomberger, with the method of manufacturing the semiconductor device as taught by Su in view of Yoo. One would have been motivated to do this with a reasonable expectation of success in order to couple the source/drain regions to a backside power delivery network which connects to a frontside, such that the shortened path from the power source to the transistors and circuitry may enable reduced resistance (Bomberger, ¶[0066]).
10. Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su) in view of Yoo, Jong Ryeol (Pub No. US 20240339498 A1) (hereinafter, Yoo) as applied to claim 12 above, and further in view of Pan, Kuan-Ting et al. (Pub No. US 20220320088 A1) (hereinafter, Pan).
Re Claim 13, (Original) Su in view of Yoo does not teach the method of claim 12, further comprising:
removing the top constraints to uncover top surfaces of the fin structures while keeping the sidewall constraints covering sidewalls of the fin structures.
In the same field of endeavor, Pan teaches the method of claim 12, further comprising: removing the top constraints (Dummy gate dielectric; 292; Figs 21-22; ¶[0036]) to uncover top surfaces (Top surfaces of the fin structures 215/220; Figs 21 - 22) while keeping the sidewall constraints (Dielectric liner; 235; Figs 21-22; ¶[0021]) covering sidewalls of the fin structures (Fin structures; 215/220; Figs 21-22; ¶[0017]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have removed the top constraints to uncover top surfaces of the fin structures while keeping the sidewall constraints covering sidewalls of the fin structures, as taught by Pan, with the method of manufacturing the semiconductor device as taught by Su in view of Yoo. One would have been motivated to do this with a reasonable expectation of success because removing the top constraints allows for additional space within the gate openings, thereafter filling the space with gate electrodes, as suggested by Pan (¶[0049]).
Re Claim 14, (Original) Su teaches the method of claim 13, further comprising:
removing exposed portions (Sacrificial layers; 122; Fig 19A; ¶[0042]) of the fin structures (Fins; 130; Fig 3A; ¶[0024]) between the sidewall constraints (Inner spacers; 240; Fig 19A; ¶[0048]).
Re Claim 15, (Original) Su teaches the method of claim 14, further comprising:
forming the S/D structures (Source/drain epitaxial structures; 250S/250D; Fig 18A; ¶[0049]) between the sidewall constraints (Inner spacers; 240; Fig 18A; ¶[0048]).
Re Claim 16, (Original) Su teaches the method of claim 14, further comprising:
forming recesses (Recesses; R2; Fig 17; ¶[0048]) in the second semiconductor material (Silicon Germanium (SiGe); 122; ¶[0019]) ; and
forming inner spacers (Inner spacers; 240; Fig 19A; ¶[0048]) in the recesses.
11. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su) in view of Yoo, Jong Ryeol (Pub No. US 20240339498 A1) (hereinafter, Yoo) as applied to claim 1 above, and further in view of Bao, Rugiqang et al. (Pub No. US 20230170352 A1) (hereinafter, Bao).
Re Claim 18, (Original) Su in view of Yoo does not teach the method of claim 1, further comprising:
bonding a first wafer to a second wafer via a first bonding dielectric layer,
the first wafer including a first bulk semiconductor material,
the second wafer including the stack formed over a second bulk semiconductor material; and
removing the second bulk semiconductor material to uncover the stack before forming the fin structures from the stack.
In the same field of endeavor, Bao teaches the method of claim 1, further comprising:
bonding a first wafer (Hardmask bonding layer/Second semiconductor material stack/Buried insulator layer/Handle substrate; 216/S2/208/205; Fig 3A; ¶[0034]) to a second wafer (Hardmask bonding layer/First semiconductor material stack/Buried insulator layer/Top substrate; 116/S1/108/105; Fig 3A; ¶[0032]) via a first bonding dielectric layer (Bonded dielectric material layer; 316; Fig 3A; ¶[0048]), the first wafer including a first bulk semiconductor material (Handle substrate; 205; Fig 3A; ¶[0034]), the second wafer including the stack formed over a second bulk semiconductor material (Top substrate; 105; Fig 3A; ¶[0032]); and
removing (Top substrate 105 is removed during operation 310; Fig 3A) the second bulk semiconductor material to uncover the stack before forming the fin structures (Fin structure in operation 320; Fig 3A) from the stack. (See Fig 3A below)
Bao, Fig 3A, Method of forming fin structures from second wafer
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have bonded a first wafer to a second wafer via a bonding dielectric layer, and removing the second bulk semiconductor material to uncover the stack before forming fin structures, as taught by Bao, with the method of manufacturing the semiconductor device as taught by Su in view of Yoo.
One would have been motivated to do this with a reasonable expectation of success in order to grow the epitaxial semiconductor layers on the second bulk semiconductor material, and to remove the second bulk semiconductor material after flipping the second wafer in order to creating room for a transistor on top of the second wafer, as suggested by Bao (¶[0091]).
12. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su) in view of Yoo, Jong Ryeol (Pub No. US 20240339498 A1) (hereinafter, Yoo) in view of Bao, Rugiqang et al. (Pub No. US 20230170352 A1) (hereinafter, Bao) as applied to claim 18 above, and further in view of Liao, Yi-Bo et al. (Pub No. US 20210366907 A1) (hereinafter, Liao).
Laio, Figs 50A/50B, Forming power delivery network within semiconductor device
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Re Claim 19, (Original) Su in view of Bao does not teach the method of claim 18, further comprising:
removing the first bulk semiconductor material to uncover the first bonding dielectric layer; and
forming a power delivery network in contact with the first bonding dielectric layer, the power delivery network including backside power rails in contact with vias that extend through the first bonding dielectric layer.
In the same field of endeavor, Liao teaches the method of claim 18, further comprising:
removing the first bulk semiconductor material (Substrate; 202; Fig 37; ¶[0020]) to uncover the first bonding dielectric layer (Base layer; 238; Fig 47A; ¶[0037]); and
forming a power delivery network (Power rails/fifth contact via; 211-2/259; Fig 50A; ¶[0083]) in contact with the first bonding dielectric layer, the power delivery network including backside power rails (Power rails; 211-2; Fig 50A; ¶[0083]) in contact with vias (Fifth contact vias; 259; Fig 50A; ¶[0083]) that extend through the first bonding dielectric layer.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have formed a power delivery network in contact with the first bonding dielectric layer, as taught by Liao, with the method of manufacturing the semiconductor device as taught by Su in view of Bao.
One would have been motivated to do this with a reasonable expectation of success because process flexibility and reduced contact resistance/parasitic capacitance may be achieved with offset device stacking, such that the drain region and contact vias are spaced apart in the stacked transistors. Further, the power rails must extend through the dielectric without a bulk semiconductor material in order to keep the power rails electrically isolated from the first transistor to the second transistor, as suggested by Liao (¶[0095]).
Allowable Subject Matter
13. Claims 5-6, 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 5, the closest prior art Su, Huan-Chieh et al. (Pub No. US 20210399109 A1) (hereinafter, Su) either singularly or in combination fails to anticipate or render obvious
“The method of claim 4, further comprising:
forming local interconnect (LI) openings to uncover the CESL; and
removing the CESL to uncover the sacrificial film,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, referring to Fig 22C of Su, a contact etch stop layer (CESL) is removed to uncover a dielectric layer to form local interconnect openings, however, the sacrificial film of claim 2 on which claim 5 depends cannot be the dielectric layer because the sacrificial film of claim 2 is epitaxially grown. Therefore the sacrificial film cannot be considered the dielectric layer below the CESL.
Regarding Claim 17, the closest prior art Zhou, Hong-Ru (Pub No. CN 119300455 A) (hereinafter, Zhou) either singularly or in combination fails to anticipate or render obvious
“The method of claim 13, further comprising: forming an uppermost layer of the second semiconductor material of the stack with a sufficient thickness so as to avoid protrusion shape of the S/D structures,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Referring to Fig. 9A of Zhou, the width defined by the channel layers does not exclusively apply to the uppermost semiconductor material layer, nor is there evidence as to avoiding a protrusion shape of the S/D structures surrounding the channels layers.
Regarding Claim 20, the closest prior art Bao, Rugiqang et al. (Pub No. US 20230170352 A1) (hereinafter, Bao) either singularly or in combination fails to anticipate or render obvious
“The method of claim 19, further comprising:
bonding a third wafer to the second wafer via a second bonding dielectric layer, the third wafer including another stack of alternating layers of epitaxially grown semiconductor layers formed over a third bulk semiconductor material;
removing the third bulk semiconductor material; and
forming a tier of transistors from another stack,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Bao discloses a first and second wafer bonded via a bonding dielectric layer, however, Bao does not disclose a third wafer consisting of a third stack of transistors, nor removing a third bulk semiconductor material.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Wang, Wei-Ren et al. (Pub No. US 20230121210 A1) (hereinafter, Wang) discloses an improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.
[2] Chang, Kangguo et al. (Pub No. US 20230187551 A1) (hereinafter, Chang) discloses a device comprises a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is disposed between the first and second interconnect structures. The stacked complementary transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type. The first contact connects a first source/drain element of the first transistor to the first interconnect structure. The second contact connects a first source/drain element of the second transistor to the second interconnect structure. The first and second contacts are disposed in alignment with each other.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817