DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of provisional application 63/344,143 submitted on 5/20/2022 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 5/18/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hook et al. (US 10283411; hereinafter ‘Hook’) in view of Smith et al. (US 2021/0098306; hereinafter ‘Smith’).
Regarding claim 1, Hook teaches a method of manufacturing a semiconductor device (1200, FIG. 12), the method comprising:
forming a first tier of transistors (402, FIG.4, col. 8, lines 39-40) and a second tier of transistors (404, FIG. 7, col. 10, lines 10-11) over the first tier of transistors (402), the first tier of transistors (402) formed on a first bonding dielectric layer (412-2 and 412-2, FIG. 4, col. 8, lines 54-58) on a first bulk semiconductor material (410, FIG. 4, col 8, line 42) the second tier of transistors (404) formed on a second bonding dielectric layer (426, FIG. 5, col. 9, line 32), the second bonding dielectric layer (426) separating the first tier of transistors (402) from the second tier of transistors (404);
forming first via openings (442 and 448, FIG. 9, col. 10, line 49) that extend through the first tier of transistors (402); and
forming second via openings (444 and 446, FIG. 9, col. 10, line 49) that extend through the second tier of transistors (404), the second bonding dielectric layer (426, since 426 is disposed between 402 and 404), and the first tier of transistors (402).
Hook does not teach the method comprising: the first tier of transistors and the second tier of transistors having gate-all-around transistors; forming first via openings that extend through the first bonding dielectric layer; subsequent to forming the first via openings, forming first local interconnect (LI) openings that connect with the first via openings; forming second via openings that extend through the first bonding dielectric layer; and subsequent to forming the second via openings, forming second LI openings that connect with the second via openings.
Smith teaches a method of manufacturing a semiconductor device [0048], the method comprising:
the first tier of transistors and the second tier of transistors having gate-all-around transistors (transistors are GAA, [0053]);
forming first via openings (256a, FIGS. 9-10, [0091-0092]) that extend through the first bonding dielectric layer (208, FIG. 10, [0082]);
subsequent to forming the first via openings (256a), forming first local interconnect (LI) openings (258a, FIG. 10, [0092]) that connect with the first via openings (256a);
forming second via openings (266a, FIGS. 21-22, [0103]) that extend through the first bonding dielectric layer (208); and
subsequent to forming the second via openings (266a), forming second LI openings (267a, FIG. 22, [0104]) that connect with the second via openings (266a).
As taught by Smith, one of ordinary skill in the art would utilize and modify the above teaching into Hook to obtain and achieve the method comprising: the first tier of transistors and the second tier of transistors having gate-all-around transistors; forming first via openings that extend through the first bonding dielectric layer; subsequent to forming the first via openings, forming first local interconnect (LI) openings that connect with the first via openings; forming second via openings that extend through the first bonding dielectric layer; and subsequent to forming the second via openings, forming second LI openings that connect with the second via openings as claimed, because GAA structures were recognized as a candidate device architecture capable of overcoming contacted gate pitch scaling limitations associated with manufacturing variability and electrostatic constrains [0004]. Further, the formation of a vertical via opening followed by isotropic lateral removal of the replacement materials inherently creates a surrounding cavity around the source/drain structure, thereby enabling a wrap-around contact configuration [0010, 0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Smith in combination with Hook due to above reason.
Regarding claim 2, Hook in view of Smith teaches the method of claim 1, Hook does not teach the method further comprising: filling the first via openings and the first LI openings with conductive metal material in a first metallization process to form first vias and first LI structures.
Smith teaches the method further comprising: filling the first via openings (256a, FIGS. 10 and 37, [0120]) and the first LI openings (258a, FIGS. 10-11) with conductive metal material (W, Co, Ru, Al, Cu, or other conductive materials, [0061]) in a first metallization process (a metallization process to fill 256 with conductive metal to form via; hereinafter ‘MP1’) to form first vias (232 formed in 256a; hereinafter ‘232256a’) and first LI structures (218 formed in 258a; hereinafter ‘218258a’).
Note: As described in paragraph [0120], Smith refers to the “first interconnect trenches 258” as the trenches that are metallized to form the first local interconnect structures 218. These trenches correspond to the interconnected trench system formed during earlier processing, which includes the local interconnect trench portion 258 and the connected via opening portion 256, as shown in FIGS. 10-11. Thus, Smith uses reference number 258 to denote the interconnect trench system that is subsequently metallized to form the first local interconnect structures 218 shown in FIG. 37).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: filling the first via openings and the first LI openings with conductive metal material in a first metallization process to form first vias and first LI structures as claimed, because a single high-conductivity metal fill streamlines processing and provides cost and uniformity benefits [0077, 0120].
Regarding claim 3, Hook in view of Smith teaches the method of claim 2, Hook does not teach the method further comprising: forming third LI openings that are separated from the first via openings and configured to be electrically connect to S/D structures of the first tier of transistors.
Smith teaches the method further comprising: forming third LI openings (258b, FIGS. 9-10, [0091-0092]) that are separated from the first via openings (256a) and configured to be electrically connect to S/D structures (212b, [0059]) of the first tier of transistors (a lower device having 212, 242, and gate structures surrounding 242, [0085]; hereinafter ‘TR1’).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: forming third LI openings that are separated from the first via openings and configured to be electrically connect to S/D structures of the first tier of transistors as claimed, because a via to drain structure provide access to the replacement materials for isotropic removal, resulting in formation of a surrounding cavity before silicide deposition [0075, 0116].
Regarding claim 4, Hook in view of Smith teaches the method of claim 3, Hook does not teach the method further comprising: forming the first LI openings and the third LI openings in a same etch process; and filling the third LI openings in the first metallization process to form third LI structures.
Smith teaches the method further comprising:
forming the first LI openings (258a) and the third LI openings (258b) in a same etch process (258a and 258b formed in the same etching step using a common mask and etch operation, FIGS. 9-10, [0090-0092]); and
filling the third LI openings (258b, FIGS. 10 and 37, [0120]) in the first metallization process (MP1) to form third LI structures (218 formed in 258b; hereinafter ‘218258b’).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: forming the first LI openings and the third LI openings in a same etch process; and filling the third LI openings in the first metallization process to form third LI structures as claimed, because the same interconnect level is defined by a common patterned template and transferred in a single etch step, and is subsequently filled in a single metallization process [0090-0092, 0120].
Regarding claim 5, Hook in view of Smith teaches the method of claim 4, Hook does not teach the method further comprising: forming third via openings, which extend through the second tier of transistors and the second bonding dielectric layer, to uncover the third LI structures.
Smith teaches the method further comprising: forming third via openings (256b, FIGS. 9-10, [0091-0092]), which extend through the second tier of transistors (an upper device having 224, 252, and gate structures surrounding 252, [0098-0099]; hereinafter ‘TR2’) and the second bonding dielectric layer (220), to uncover the third LI structures (218258b, since 218258b is defined as being formed in 258b and the 256b does not cover 218258b).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: forming third via openings, which extend through the second tier of transistors and the second bonding dielectric layer, to uncover the third LI structures as claimed, because maintaining electrical isolation and proper alignment of independent interconnect paths requires spatial separation of the vias.
Regarding claim 6, Hook in view of Smith teaches the method of claim 5, Hook does not teach the method wherein after forming the third via openings, forming fourth LI openings that connect with the third via openings.
Smith teaches the method, wherein after forming the third via openings (256b), forming fourth LI openings (273b, FIG. 30, [0113]) that connect with the third via openings (256b).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method wherein after forming the third via openings, forming fourth LI openings that connect with the third via openings as claimed, because electrically coupling the via-to-rail opening and the via-to-drain opening establishes a continuous conductive path between the source/drain region and the buried power rail through the local interconnect structure [0091, 0120].
Regarding claim 7, Hook in view of Smith teaches the method of claim 6, Hook does not teach the method further comprising: filling the third via openings and the fourth LI openings with a conductive metal material in a second metallization process to form third vias and fourth LI structures.
Smith teaches the method, further comprising: filling the third via openings (256b, FIGS. 10 and 37, [0120]) and the fourth LI openings (273b) with a conductive metal material (W, Co, Ru, Al, Cu, or other conductive materials, [0061]) in a second metallization process (a metallization process to fill 256b and 273b with conductive metal; hereinafter ‘MP2’) to form third vias (232 formed in 256b; hereinafter ‘232256b’) and fourth LI structures (232 formed in 273b; hereinafter ‘232273b’).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: filling the third via openings and the fourth LI openings with a conductive metal material in a second metallization process to form third vias and fourth LI structures as claimed, because a single high-conductivity metal fill streamlines processing and provides cost and uniformity benefits [0077, 0120].
Regarding claim 8, Hook in view of Smith teaches the method of claim 7, Hook does not teach the method wherein: each of the third vias connects a respective third LI structure to a respective fourth LI structure.
Smith teaches the method wherein each of the third vias (232256b) connects a respective third LI structure (218258b) to a respective fourth LI structure (232273b, see the annotated FIG. 37).
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method wherein: each of the third vias connects a respective third LI structure to a respective fourth LI structure as claimed, because electrically coupling the via-to-rail opening and the via-to-drain opening establishes a continuous conductive path between the source/drain region and the buried power rail through the local interconnect structure [0091, 0120].
Regarding claim 9, Hook in view of Smith teaches the method of claim 2, Hook does not teach the method further comprising: filling the second via openings and the second LI openings in a second metallization process to form second vias and second LI structures.
Smith teaches the method further comprising: filling the second via openings (266a, FIGS. 22 and 37, [0120]) and the second LI openings (267a, FIG. 22) in a second metallization process (a metallization process to fill 266a and 267a with conductive metal; hereinafter ‘MP2R’) to form second vias (232 formed in 266a; hereinafter ‘232266a’) and second LI structures (228 formed in 267a; hereinafter ‘228267a’).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: filling the second via openings and the second LI openings in a second metallization process to form second vias and second LI structures as claimed, because a single high-conductivity metal fill streamlines processing and provides cost and uniformity benefits [0077, 0120].
Regarding claim 10, Hook in view of Smith teaches the method of claim 9, Hook does not teach the method further comprising: forming third LI openings that are separated from the second via openings and configured to be electrically connect to S/D structures of the second tier of transistors.
Smith teaches the method further comprising: forming third LI openings (267b, FIG. 22, [0104]) that are separated from the second via openings (266a) and configured to be electrically connect to S/D structures (224b) of the second tier of transistors (TR2).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: forming third LI openings that are separated from the second via openings and configured to be electrically connect to S/D structures of the second tier of transistors as claimed, because maintaining electrical isolation and proper alignment of independent interconnect paths requires spatial separation of the vias.
Regarding claim 11, Hook in view of Smith teaches the method of claim 10, Hook does not teach the method further comprising: forming the second LI openings and the third LI openings in a same etch process; and filling the third LI openings in the second metallization process to form third LI structures.
Smith teaches the method further comprising:
forming the second LI openings (267a, FIG. 22) and the third LI openings (267b) in a same etch process (267a and 267b formed in the same etching step using a common mask and etch operation, FIGS. 22, [0104]); and
filling the third LI openings (267b, FIGS. 22 and 37, [0120]) in the second metallization process (MP2R) to form third LI structures (228 formed in 267b; hereinafter ‘228267b’).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: forming the second LI openings and the third LI openings in a same etch process; and filling the third LI openings in the second metallization process to form third LI structures as claimed, because the same interconnect level is defined by a common patterned template and transferred in a single etch step, and is subsequently filled in a single metallization process [0090-0092, 0120].
Regarding claim 14, Hook in view of Smith teaches the method of claim 1, Hook does not teach the method further comprising: forming backside power rails so that the backside power rails and the first tier of transistors are positioned on opposing sides of the first bonding dielectric layer.
Smith teaches the method further comprising: forming backside power rails (204, FIG. 4, [0082]) so that the backside power rails (204) and the first tier of transistors (TR1) are positioned on opposing sides of the first bonding dielectric layer (208).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: forming backside power rails so that the backside power rails and the first tier of transistors are positioned on opposing sides of the first bonding dielectric layer as claimed, because it enables vertical device stacking while providing a common power supply without consuming routing resources in upper interconnect levels [0053-0054].
Claims 1, 2, 9, and 12 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Hook (US 10283411) in view of Smith (US 2021/0098306).
Regarding claim 1, Hook teaches a method of manufacturing a semiconductor device (1200, FIG. 12), the method comprising:
forming a first tier of transistors (402, FIG.4, col. 8, lines 39-40) and a second tier of transistors (404, FIG. 7, col. 10, lines 10-11) over the first tier of transistors (402), the first tier of transistors (402) formed on a first bonding dielectric layer (412-2 and 412-2, FIG. 4, col. 8, lines 54-58) on a first bulk semiconductor material (410, FIG. 4, col 8, line 42) the second tier of transistors (404) formed on a second bonding dielectric layer (426, FIG. 5, col. 9, line 32), the second bonding dielectric layer (426) separating the first tier of transistors (402) from the second tier of transistors (404);
forming first via openings (442 and 448, FIG. 9, col. 10, line 49) that extend through the first tier of transistors (402); and
forming second via openings (444 and 446, FIG. 9, col. 10, line 49) that extend through the second tier of transistors (404), the second bonding dielectric layer (426, since 426 is disposed between 402 and 404), and the first tier of transistors (402).
Hook does not teach the method comprising: the first tier of transistors and the second tier of transistors having gate-all-around transistors; forming first via openings that extend through the first bonding dielectric layer; subsequent to forming the first via openings, forming first local interconnect (LI) openings that connect with the first via openings; forming second via openings that extend through the first bonding dielectric layer; and subsequent to forming the second via openings, forming second LI openings that connect with the second via openings.
Smith teaches a method of manufacturing a semiconductor device [0048], the method comprising:
the first tier of transistors and the second tier of transistors having gate-all-around transistors (transistors are GAA, [0053]);
forming first via openings (256a, FIGS. 9-10, [0091-0092]) that extend through the first bonding dielectric layer (208, FIG. 10, [0082]);
subsequent to forming the first via openings (256a), forming first local interconnect (LI) openings (258a, FIG. 10, [0092]) that connect with the first via openings (256a);
forming second via openings (266a, FIGS. 21-22, [0103]) that extend through the first bonding dielectric layer (208); and
subsequent to forming the second via openings (266a), forming second LI openings (274a, FIGS. 31 and 36, [0114]) that connect with the second via openings (266a).
As taught by Smith, one of ordinary skill in the art would utilize and modify the above teaching into Hook to obtain and achieve the method comprising: the first tier of transistors and the second tier of transistors having gate-all-around transistors; forming first via openings that extend through the first bonding dielectric layer; subsequent to forming the first via openings, forming first local interconnect (LI) openings that connect with the first via openings; forming second via openings that extend through the first bonding dielectric layer; and subsequent to forming the second via openings, forming second LI openings that connect with the second via openings as claimed, because GAA structures were recognized as a candidate device architecture capable of overcoming contacted gate pitch scaling limitations associated with manufacturing variability and electrostatic constrains [0004]. Further, the formation of a vertical via opening followed by isotropic lateral removal of the replacement materials inherently creates a surrounding cavity around the source/drain structure, thereby enabling a wrap-around contact configuration [0010, 0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Smith in combination with Hook due to above reason.
Regarding claim 2, Hook in view of Smith teaches the method of claim 1, Hook does not teach the method further comprising: filling the first via openings and the first LI openings with conductive metal material in a first metallization process to form first vias and first LI structures.
Smith teaches the method further comprising: filling the first via openings (256a, FIGS. 10 and 37, [0120]) and the first LI openings (258a, FIGS. 10-11) with conductive metal material (W, Co, Ru, Al, Cu, or other conductive materials, [0061]) in a first metallization process (a metallization process to fill 256a and 258a with conductive metal to form via) to form first vias (232 formed in 256a; hereinafter ‘232256a’) and first LI structures (218 formed in 258a; hereinafter ‘218258a’).
Note: As described in paragraph [0120], Smith refers to the “first interconnect trenches 258” as the trenches that are metallized to form the first local interconnect structures 218. These trenches correspond to the interconnected trench system formed during earlier processing, which includes the local interconnect trench portion 258 and the connected via opening portion 256, as shown in FIGS. 10-11. Thus, Smith uses reference number 258 to denote the interconnect trench system that is subsequently metallized to form the first local interconnect structures 218 shown in FIG. 37).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: filling the first via openings and the first LI openings with conductive metal material in a first metallization process to form first vias and first LI structures as claimed, because a single high-conductivity metal fill streamlines processing and provides cost and uniformity benefits [0077, 0120].
Regarding claim 9, Hook in view of Smith teaches the method of claim 2, Hook does not teach the method further comprising: filling the second via openings and the second LI openings in a second metallization process to form second vias and second LI structures.
Smith teaches the method further comprising: filling the second via openings (266a, FIGS. 22 and 37, [0120]) and the second LI openings (274a, FIGS. 31 and 37) in a second metallization process (a metallization process to fill 266a and 274a with conductive metal; hereinafter ‘MP2R’) to form second vias (232 formed in 266a; hereinafter ‘232266a’) and second LI structures (232 formed in 274a; hereinafter ‘232274a’).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: filling the second via openings and the second LI openings in a second metallization process to form second vias and second LI structures as claimed, because a single high-conductivity metal fill streamlines processing and provides cost and uniformity benefits [0077, 0120].
Regarding claim 12, Hook in view of Smith teaches the method of claim 9, Hook does not teach the method further comprising: partially filling the second via openings with a second filler material, before forming the second LI openings; and removing the second filler material, before forming the second vias and the second LI structures.
Smith teaches the method further comprising:
partially filling the second via openings (266a, FIGS. 22 and 25) with a second filler material (269a, [0107]), before forming the second LI openings (274a, FIG. 31); and
removing the second filler material (269a, FIG. 33), before forming the second vias (232266a, FIG. 37) and the second LI structures (232274a).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: partially filling the second via openings with a second filler material, before forming the second LI openings; and removing the second filler material, before forming the second vias and the second LI structures as claimed, because temporary material is intended only to withstand high thermal processing and must be replaced with a high-conductivity metal to establish the final electrical interconnect structure [0116-0117, 0120].
Claims 1, 2, and 13 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Hook (US 10283411) in view of Smith (US 2021/0098306).
Regarding claim 1, Hook teaches a method of manufacturing a semiconductor device (1200, FIG. 12), the method comprising:
forming a first tier of transistors (402, FIG.4, col. 8, lines 39-40) and a second tier of transistors (404, FIG. 7, col. 10, lines 10-11) over the first tier of transistors (402), the first tier of transistors (402) formed on a first bonding dielectric layer (412-2 and 412-2, FIG. 4, col. 8, lines 54-58) on a first bulk semiconductor material (410, FIG. 4, col 8, line 42) the second tier of transistors (404) formed on a second bonding dielectric layer (426, FIG. 5, col. 9, line 32), the second bonding dielectric layer (426) separating the first tier of transistors (402) from the second tier of transistors (404);
forming first via openings (442 and 448, FIG. 9, col. 10, line 49) that extend through the first tier of transistors (402); and
forming second via openings (444 and 446, FIG. 9, col. 10, line 49) that extend through the second tier of transistors (404), the second bonding dielectric layer (426, since 426 is disposed between 402 and 404), and the first tier of transistors (402).
Hook does not teach the method comprising: the first tier of transistors and the second tier of transistors having gate-all-around transistors; forming first via openings that extend through the first bonding dielectric layer; subsequent to forming the first via openings, forming first local interconnect (LI) openings that connect with the first via openings; forming second via openings that extend through the first bonding dielectric layer; and subsequent to forming the second via openings, forming second LI openings that connect with the second via openings.
Smith teaches a method of manufacturing a semiconductor device [0048], the method comprising:
the first tier of transistors and the second tier of transistors having gate-all-around transistors (transistors are GAA, [0053]);
forming first via openings (256a, FIGS. 9-10, [0091-0092]) that extend through the first bonding dielectric layer (208, FIG. 10, [0082]);
subsequent to forming the first via openings (256a), forming first local interconnect (LI) openings (273a, FIG. 30, [0113]) that connect with the first via openings (256a);
forming second via openings (266a, FIGS. 21-22, [0103]) that extend through the first bonding dielectric layer (208); and
subsequent to forming the second via openings (266a), forming second LI openings (267a, FIG. 22, [0104]) that connect with the second via openings (266a).
As taught by Smith, one of ordinary skill in the art would utilize and modify the above teaching into Hook to obtain and achieve the method comprising: the first tier of transistors and the second tier of transistors having gate-all-around transistors; forming first via openings that extend through the first bonding dielectric layer; subsequent to forming the first via openings, forming first local interconnect (LI) openings that connect with the first via openings; forming second via openings that extend through the first bonding dielectric layer; and subsequent to forming the second via openings, forming second LI openings that connect with the second via openings as claimed, because GAA structures were recognized as a candidate device architecture capable of overcoming contacted gate pitch scaling limitations associated with manufacturing variability and electrostatic constrains [0004]. Further, the formation of a vertical via opening followed by isotropic lateral removal of the replacement materials inherently creates a surrounding cavity around the source/drain structure, thereby enabling a wrap-around contact configuration [0010, 0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Smith in combination with Hook due to above reason.
Regarding claim 2, Hook in view of Smith teaches the method of claim 1, Hook does not teach the method further comprising: filling the first via openings and the first LI openings with conductive metal material in a first metallization process to form first vias and first LI structures.
Smith teaches the method further comprising: filling the first via openings (256a, FIGS. 10 and 37, [0120]) and the first LI openings (273a, FIGS. 30 and 37) with conductive metal material (W, Co, Ru, Al, Cu, or other conductive materials, [0061]) in a first metallization process (a metallization process to fill 256a and 273a with conductive metal to form via) to form first vias (232 formed in 256a; hereinafter ‘232256a’) and first LI structures (232 formed in 273a; hereinafter ‘232273a’).
Note: As described in paragraph [0120], Smith refers to the “first interconnect trenches 258” as the trenches that are metallized to form the first local interconnect structures 218. These trenches correspond to the interconnected trench system formed during earlier processing, which includes the local interconnect trench portion 258 and the connected via opening portion 256, as shown in FIGS. 10-11. Thus, Smith uses reference number 258 to denote the interconnect trench system that is subsequently metallized to form the first local interconnect structures 218 shown in FIG. 37).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: filling the first via openings and the first LI openings with conductive metal material in a first metallization process to form first vias and first LI structures as claimed, because a single high-conductivity metal fill streamlines processing and provides cost and uniformity benefits [0077, 0120].
Regarding claim 13, Hook in view of Smith teaches the method teaches the method of claim 2, Hook does not teach the method further comprising: partially filling the first via openings with a first filler material, before forming the first LI openings; and removing the first filler material, before forming the first vias and the first LI structures.
Smith teaches the method further comprising:
partially filling the first via openings (256a, FIGS. 10 and 13) with a first filler material (262a, [0095]), before forming the first LI openings (273a, FIG. 30); and
removing the first filler material (262a, FIG. 33), before forming the first vias (232256a) and the first LI structures (232273a).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: partially filling the first via openings with a first filler material, before forming the first LI openings; and removing the first filler material, before forming the first vias and the first LI structures as claimed, because temporary material is intended only to withstand high thermal processing and must be replaced with a high-conductivity metal to establish the final electrical interconnect structure [0116-0117, 0120].
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hook (US 10283411) in view of Smith (US 2021/0098306), and further in view of Park et al. (US 2022/0157723; hereinafter ‘Park’).
Regarding claim 15, Smith in view of Hook teaches the method of claim 14, but dees not teach the method wherein: the backside power rails are formed after forming the first via openings and forming the second via openings.
Park teaches a method (FIGS. 6A-6F, [0054]), wherein: the backside power rails (200b FIG. 6F, [0064]) are formed after forming the first via openings and forming the second via openings (200b are formed after forming 200a having vias openings for 20 and 30, FIG. 6E, [0065])).
As taught by Park, one of ordinary skill in the art would utilize and modify the above teaching into Hook in view of Smith to obtain and achieve the method wherein: the backside power rails are formed after forming the first via openings and forming the second via openings as claimed, because it allows accurate alignment and reliable electrical connection between the power distribution structures and the transistor device, thereby improving connectivity and reducing resistance [0053, 0064, 0066].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Park in combination with Hook in view of Smith due to above reason.
Regarding claim 16, Hook in view of Smith teaches the method of claim 1, Hook does not teach the method further comprising: filling the first via openings and the second via openings with conductive metal material to form first vias and second vias; and removing the first bulk semiconductor material to uncover the first bonding dielectric layer, the first vias and the second vias.
Smith teaches the method further comprising: filling the first via openings (256a, FIGS. 10 and 37, [0120]) and the second via openings (266a, FIGS. 22 and 37, [0120]) with conductive metal material (W, Co, Ru, Al, Cu, or other conductive materials, [0061]) to form first vias (232 formed in 256a; hereinafter ‘232256a’) and second vias (232 formed in 266a; hereinafter ‘232266a’).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: filling the first via openings and the second via openings with conductive metal material to form first vias and second vias; and removing the first bulk semiconductor material to uncover the first bonding dielectric layer, the first vias and the second vias as claimed, because a single high-conductivity metal fill streamlines processing and provides cost and uniformity benefits [0077, 0120].
Hook in view of Smith does not teach the method further comprising: removing the first bulk semiconductor material to uncover the first bonding dielectric layer, the first vias and the second vias.
Park teaches a method (FIGS. 6A-6F, [0054]) further comprising: removing the first bulk semiconductor material (100a, FIG. 6E, [0063]) to uncover the first bonding dielectric layer (500, FIG. 6E, [0063]), the first vias (30, FIG. 6F, [0064-0065]) and the second vias (20).
As taught by Park, one of ordinary skill in the art would utilize and modify the above teaching into Hook in view of Smith to obtain and achieve the method further comprising: removing the first bulk semiconductor material to uncover the first bonding dielectric layer, the first vias and the second vias as claimed, because it exposes alignment reference structures, thereby enabling accurate formation and electrical connection of the backside power structure to the alignment structure and associated device structures [0063-0064, 0066].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Park in combination with Hook in view of Smith due to above reason.
Regarding claim 17, Hook in view of Smith and Park teaches the method of claim 16, Hook in view of Park does not teach the method wherein: forming backside power rails that are in contact with at least one via selected from the group consisting of the first vias and the second vias.
Smith teaches the method wherein forming backside power rails (204, FIG. 4, [0082]) that are in contact with at least one via selected from the group consisting of the first vias (232256a, FIGS. 10 and 37,) and the second vias (232266a, FIGS. 22 and 37).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method wherein: forming backside power rails that are in contact with at least one via selected from the group consisting of the first vias and the second vias as claimed, because electrically coupling the buried power rails and the vias establishes a continuous conductive path to deliver supply voltage from the power rails to the source/drain regions through the local interconnect structures [0054, 0091, 0120].
Regarding claim 18, Hook in view of Smith teaches the method of claim 1, Hook does not teach the method further comprising: forming a signal wiring layer over the second tier of transistors.
Smith teaches the method further comprising: forming a wiring layer (238, FIG. 37, [0120]) over the second tier of transistors (TR2).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: forming a signal wiring layer over the second tier of transistors as claimed, because it enables electrical connection through the via structure to provide an electrical path between the upper transistor and the interconnect level [0058, 0120].
Hook in view of Smith does not teach that the wiring layer is a signal wiring layer.
Park teaches a method (FIG. 1, [0036]) further comprising: forming a signal wiring layer (1210).
As taught by Park, one of ordinary skill in the art would utilize and modify the above teaching into Hook in view of Smith to obtain and achieve the method further comprising: forming a signal wiring layer as claimed, because it alleviates routing congestion and reduces resistance and IR drop, thereby improving overall device performance [0036].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Park in combination with Hook in view of Smith due to above reason.
Regarding claim 19, Hook in view of Smith and Park teaches the method of claim 18, Hook in view of Park does not teach the method further comprising: forming third vias that are configured to electrically connect the signal wiring layer to the first tier of transistors; and forming fourth vias that are configured to electrically connect the signal wiring layer to the second tier of transistors.
Smith teaches the method further comprising:
forming third vias (232a, FIG. 37, [0120, 0122]) that are configured to electrically connect the signal wiring layer (238a) to the first tier of transistors (TR1); and
forming fourth vias (232b) that are configured to electrically connect the signal wiring layer (238b) to the second tier of transistors (TR2).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method further comprising: forming third vias that are configured to electrically connect the signal wiring layer to the first tier of transistors; and forming fourth vias that are configured to electrically connect the signal wiring layer to the second tier of transistors as claimed, because a 3D stacked transistor architecture requires interconnect structures and metal lines to provide electrical communication between the device and higher interconnect levels [0053, 0058, 0120].
Regarding claim 20, Hook in view of Smith and Park teaches the method of claim 19, Hook in view of Park does not teach the method wherein: the signal wiring layer is formed, after forming the first via openings, the second via openings, the third vias and the fourth vias.
Smith teaches the method wherein the signal wiring layer (238, FIG. 37, [0120]) is formed, after forming the first via openings, the second via openings, the third vias and the fourth vias (238 is formed after 256a, 266a, 232a, and 232b).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Smith to obtain and achieve the method wherein: the signal wiring layer is formed, after forming the first via openings, the second via openings, the third vias and the fourth vias as claimed, because the uppermost wiring layer is formed after completion of high-temperature processing and replacement material removal, thereby preventing thermal damage and enabling final metallization of the interconnect structure [0111m 0119-0120].
Conclusion
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/3/26