DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/09/2026 has been entered.
Response to Arguments
Applicant’s arguments see remarks, filed 04/09/2026, with respect to claims 1-6, have been fully considered but are moot because the arguments do not apply to the current references and current combinations of references being used in the current rejection.
Applicant’s arguments see remarks, filed 04/09/2026, with respect to claims 7, 9, 14, are fully considered and comprising of allowable subject matter as disclosed below therefore claims 7, 9, 14 and their dependent claims 8, 10-13 and 15-20 are now been submitted as allowable once the double patenting rejection.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-6 provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claims 1, 3-6 of Co-pending Application No. 19/276306 (reference application) in view of Takahashi et al. (US 20200135844 A1), hereinafter referenced as Takahashi.
This is a provisional non-statutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Although the claims of this Application No. 18/320020 and the claims at issue of Co-pending Application No. 19/276306 are not identical, they are not patentably distinct from each other because the instant application and the conflicting co-pending Application are claiming common subject matter, as follows:
This Application No. 18/320020
Co-pending Application No. 19/276306
Claim 1: A semiconductor structure, comprising: a contact feature disposed in a first dielectric layer; a first etch stop layer (ESL) over the contact feature and the first dielectric layer; a second dielectric layer over the first ESL;
a second ESL over the second dielectric layer; a third dielectric layer over the second ESL; a third ESL over the third dielectric layer; a fourth dielectric layer over the third ESL; comprising:
and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, the second dielectric layer, and the first ESL,
an insulator layer disposed over the bottom electrode layer and extending at least through the fourth dielectric layer and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, and the second dielectric layer,
and a top electrode layer disposed over the insulator layer such that the top electrode layer is spaced apart from the bottom electrode layer by the insulator layer, (Line 1-22)
and a capacitor comprising: a bottom electrode layer continuously extending from over and along a top surface of the fourth dielectric layer toward the contact feature, the bottom electrode layer extending continuously and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, the second dielectric layer, and the first ESL
Claim 1: A semiconductor structure, comprising: a first dielectric layer, a contact feature disposed in the first dielectric layer, a first etch stop layer (ESL) over the contact feature and the first dielectric layer, a second dielectric layer over the first ESL,
a second ESL over the second dielectric layer, a third dielectric layer over the second ESL, a third ESL over the third dielectric layer, a fourth dielectric layer over the third ESL,
a bottom electrode layer continuously extending along a top surface of the fourth dielectric layer and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, the second dielectric layer, and the first ESL,
an insulator layer disposed over the bottom electrode layer and extending at least through the fourth dielectric layer and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, and the second dielectric layer, and a top electrode layer disposed over the insulator layer such that the top electrode layer is spaced apart from the bottom electrode layer by the insulator layer.
(Line 1-6)
Although, Co-pending Application No. 19/276306 claim 1 teaches semiconductor structure, comprising: a contact feature disposed in a first dielectric layer; a first etch stop layer (ESL) over the contact feature and the first dielectric layer; a second dielectric layer over the first ESL; a second ESL over the second dielectric layer; a third dielectric layer over the second ESL; a third ESL over the third dielectric layer; a fourth dielectric layer over the third ESL; comprising.
Co-pending Application No. 19/276306 claim 1 as stated in the table above with respect to claim 1, fail to teach a capacitor comprising: a bottom electrode layer continuously extending from over and along a top surface of the fourth dielectric layer toward the contact feature, the bottom electrode layer extending continuously and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, the second dielectric layer, and the first ESL.
However, Takahashi et al. (US 20200135844 A1), explicitly teaches a capacitor (Fig. 2A, #114 called a MIM capacitor. Paragraph [0027]) comprising:
a bottom electrode layer (Fig. 2A, #116 called a lower conductive electrode. Paragraph [0027]- Takahashi discloses the MIM capacitor 114 includes a lower conductive electrode 116 that is separated from an upper conductive electrode 120 by a capacitor dielectric structure 118. Please see the annotation diagram of figure 2A.) continuously extending from over and along a top surface of the fourth dielectric layer toward the contact feature (Fig. 2A, illustrates the bottom electrode layer #116 extends from over the top surface of the fourth dielectric layer toward the contact feature #108a. Paragraph [0027]- Takahashi discloses the lower interconnect layer 108a and the upper interconnect layer 108b may comprise a metal (e.g., copper, tungsten, aluminum, or the like). In some embodiments, the lower conductive electrode 116 and the upper conductive electrode 120 may comprise a metal that is different than that of the lower interconnect layer 108a and/or the upper interconnect layer 108b. Please see the annotation diagram of figure 2A.) the bottom electrode layer (Fig. 2A, #116 called a lower conductive electrode. Paragraph [0027]) extending continuously and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, the second dielectric layer, and the first ESL (Fig. 2A, illustrates the bottom electrode layer #116 extending continuously and vertically through the fourth, third and second dielectric layers towards the contact feature #108a. Paragraph [0027-0028]. Please see the annotation diagram of figure 2A.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of the Co-pending Application No. 19/276306 claim 1 of having wherein semiconductor structure, comprising: a contact feature disposed in a first dielectric layer; a first etch stop layer (ESL) over the contact feature and the first dielectric layer, with the teachings of Takahashi et al. (US 20200135844 A1), of having wherein a capacitor comprising: a bottom electrode layer continuously extending from over and along a top surface of the fourth dielectric layer toward the contact feature, the bottom electrode layer extending continuously and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, the second dielectric layer, and the first ESL.
Wherein having Co-pending Application No. 19/276306 claim 1 having semiconductor structure, a capacitor comprising: a bottom electrode layer continuously extending from over and along a top surface of the fourth dielectric layer toward the contact feature, the bottom electrode layer extending continuously and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, the second dielectric layer, and the first ESL.
The motivation behind the modification would have been to obtain a trench capacitor semiconductor structure system that enhances the fabrication process efficiency and miniaturization.
The further limitations of the dependent claims are similar as indicated below:
This Application No. 18/320020
Co-pending Application No. 19/276306
Claim 3: wherein a composition of the second ESL is different from a composition of the first ESL or the third ESL. (Line 1-2).
Claim 4: wherein the first ESL and the third ESL comprise silicon carbide, wherein the second ESL comprises silicon nitride. (Line 1-3).
Claim 5: wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer comprise silicon oxide. (Line 1-2).
Claim 6: wherein the bottom electrode layer and the top electrode layer comprise titanium nitride, wherein the insulator layer comprises zirconium oxide and aluminum oxide. (Line 1-2).
Claim 3: wherein a composition of the second ESL is different from a composition of the first ESL or the third ESL. (Line 1-2).
Claim 4: wherein the first ESL and the third ESL comprise silicon carbide, wherein the second ESL comprises silicon nitride. (Line 1-3).
Claim 5: wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer comprise silicon oxide. (Line 1-2).
Claim 6: wherein the bottom electrode layer and the top electrode layer comprise titanium nitride, wherein the insulator layer comprises zirconium oxide and aluminum oxide. (Line 1-2).
Claims 3-6, contains the same limitations as Co-pending Application No. 19/276306 claim 3-6 respectively. Therefore, given that claims 3-6 depend from claim 1, respectively and claims 3-6 of Co-pending Application No. 19/276306 depend from claim 1, respectively. Claim 3-6 are rejected for the same reasons set forth in the rejection of the independent claim 1 above.
Claim 2, is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1, of Co-pending Application No. 19/276306 (reference application) in view of Takahashi et al. (US 20200135844 A1), hereinafter referenced as Takahashi and in further in view of Ando et al. (US 20160181353 A1), hereinafter referenced as Ando.
Regarding claim 2, Co-pending Application No. 19/276306 claim 1 teaches the semiconductor structure of claim 1, Co-pending Application No. 19/276306 claim 1 fail to explicitly teach wherein tungsten is present at an interface between a top surface of the insulator layer and a bottom surface of the top electrode layer.
However, Ando et al. (US 20160181353 A1), explicitly teaches wherein tungsten is present at an interface (Fig. 11, #118 called an oxygen gettering layer. Paragraph [0052]) between a top surface of the insulator layer (Fig. 11, illustrates an interface #118 is between a top surface of the insulator layer #110 on the side. Paragraph [0052]-Ando discloses aluminum containing compounds to be used as the oxygen gettering layer 118 may include titanium aluminum nitride, titanium aluminum carbide, tantalum aluminum nitride, tantalum aluminum carbide, tungsten aluminum nitride, tungsten aluminum carbide, cobalt aluminum nitride, or cobalt aluminum carbide. Further in paragraph [0046]-Ando discloses the buried insulator layer 110 may be formed from any of several dielectric materials known in the art. Further in paragraph [0060-0061]-Ando discloses the recessed portion of the thin metallic film 120 will form an outer or buried electrode 128 for the trench capacitors of the present embodiment. Referring now to FIG. 10, yet another isotropic etching step is shown. In the present etching step, the second trench fill 126 may be completely removed from the deep trench 116 to expose the outer electrode 128.) and a bottom surface of the top electrode layer (Fig. 11, illustrates an interface #118 between the insulator layer #110 and a bottom surface of the top electrode layer #132. Paragraph [0052]-Ando discloses aluminum containing compounds to be used as the oxygen gettering layer 118 may include titanium aluminum nitride, titanium aluminum carbide, tantalum aluminum nitride, tantalum aluminum carbide, tungsten aluminum nitride, tungsten aluminum carbide, cobalt aluminum nitride, or cobalt aluminum carbide. Further in paragraph [0046]-Ando discloses the buried insulator layer 110 may be formed from any of several dielectric materials known in the art. Further in paragraph [0062]-Ando discloses Referring now to FIG. 11, subsequent to the etching steps described hereinabove, a node dielectric layer 130 and an inner electrode film 132 are deposited over the entire structure 100 and within the deep trench 116.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Co-pending Application No. 19/276306 claim 1 of having a semiconductor structure, comprising: a contact feature disposed in a first dielectric layer; a first etch stop layer (ESL) over the contact feature and the first dielectric layer; a second dielectric layer over the first ESL; a second ESL over the second dielectric layer; a third dielectric layer over the second ESL; a third ESL over the third dielectric layer; a fourth dielectric layer over the third ESL; and a capacitor comprising: a bottom electrode layer continuously extending along a top surface of the fourth dielectric layer and vertically through the fourth dielectric layer, with the teachings of Ando of having wherein tungsten is present at an interface between a top surface of the insulator layer and a bottom surface of the top electrode layer.
Wherein having Co-pending Application No. 19/276306 claim 1’ a semiconductor structure, wherein tungsten is present at an interface between a top surface of the insulator layer and a bottom surface of the top electrode layer.
The motivation behind the modification would have been to obtain a trench capacitor semiconductor structure system that enhances integration without any conductive feature damage and minimum feature size.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 4, and 6, are rejected under 35 U.S.C. 102(a) (1)/(a) (2) as being anticipated by Takahashi et al. (US 20200135844 A1), hereinafter referenced as Takahashi.
Regarding claim 1, Takahashi teaches a semiconductor structure (Fig. 2A, #200 called a integrated chip. Paragraph [0036]), comprising: a contact feature (Fig. 2A, #108a1-3 called a lower interconnect layer. Paragraph [0027]) disposed in a first dielectric layer (Fig. 2A, illustrates an inter-level dielectric (ILD) #202 that is located over the etch stop layer (ESL) #204 that is in contact with the lower interconnect layer #108a1-3. Paragraph [0025]); a first etch stop layer (ESL) (Fig. 2A, illustrates the first etch stop layer (ESL) #204 that is the third (ESL) from the substrate #102 in the upwards direction. Paragraph [0025]) over the contact feature and the first dielectric layer (Fig. 2A. Paragraph [0026]- Takahashi discloses a plurality of conductive interconnect layers 108 are arranged within the dielectric structure 104. The plurality of conductive interconnect layers 108 comprise alternating layers of interconnect wires 110 and interconnect vias 112 respectively surrounded by one of the plurality of ILD layers 202. For example, a first interconnect wire may be surrounded by a first ILD layer, a second interconnect wire may be surrounded by a second ILD layer, etc.); a second dielectric layer over the first ESL (Fig. 2A, illustrates the second dielectric layer #202, the fourth dielectric layer upward from the substrate #102 over the first ESL #204. Paragraph [0031]); a second ESL over the second dielectric layer (Fig. 2A, illustrates second ESL the ESL layer #204 that is the fourth ESL upward from the substrate #102 over the first ESL #204. Paragraph [0031]); a third dielectric layer over the second ESL (Fig. 2A, illustrates the third dielectric layer #202, the fifth dielectric layer upward from the substrate #102 over the first ESL #204. Paragraph [0031]); a third ESL over the third dielectric layer (Fig. 2A, illustrates third ESL the ESL layer #204 that is the fifth ESL upward from the substrate #102 over the first ESL #204. Paragraph [0031]); a fourth dielectric layer over the third ESL (Fig. 2A, illustrates the third dielectric layer #202, the sixth dielectric layer upward from the substrate #102 over the first ESL #204. Paragraph [0031]. Please see the annotation diagram of figure 2A.);
and a capacitor (Fig. 2A, #114 called a MIM capacitor. Paragraph [0027]) comprising:
a bottom electrode layer (Fig. 2A, #116 called a lower conductive electrode. Paragraph [0027]- Takahashi discloses the MIM capacitor 114 includes a lower conductive electrode 116 that is separated from an upper conductive electrode 120 by a capacitor dielectric structure 118. Please see the annotation diagram of figure 2A.) continuously extending from over and along a top surface of the fourth dielectric layer toward the contact feature (Fig. 2A, illustrates the bottom electrode layer #116 extends from over the top surface of the fourth dielectric layer toward the contact feature #108a. Paragraph [0027]- Takahashi discloses the lower interconnect layer 108a and the upper interconnect layer 108b may comprise a metal (e.g., copper, tungsten, aluminum, or the like). In some embodiments, the lower conductive electrode 116 and the upper conductive electrode 120 may comprise a metal that is different than that of the lower interconnect layer 108a and/or the upper interconnect layer 108b. Please see the annotation diagram of figure 2A.) the bottom electrode layer (Fig. 2A, #116 called a lower conductive electrode. Paragraph [0027]) extending continuously and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, the second dielectric layer, and the first ESL (Fig. 2A, illustrates the bottom electrode layer #116 extending continuously and vertically through the fourth, third and second dielectric layers towards the contact feature #108a. Paragraph [0027-0028]. Please see the annotation diagram of figure 2A.),
an insulator layer (Fig. 2A, #118 called a capacitor dielectric structure. Paragraph [0027]) disposed over the bottom electrode layer (Fig. 2A. Paragraph [0027]- Takahashi discloses the MIM capacitor 114 includes a lower conductive electrode 116 that is separated from an upper conductive electrode 120 by a capacitor dielectric structure 118. In some embodiments, the lower conductive electrode 116 has a top surface that is below the capacitor dielectric structure 118, and the capacitor dielectric structure 118 has a top surface that is below the upper conductive electrode 120. Please see the annotation diagram of figure 2A.) and extending vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, and the second dielectric layer (Fig. 2A, illustrates the insulator layer #118 is parallel to the bottom electrode layer #116, extending continuously and vertically through the fourth, third and second dielectric layers towards the contact feature #108a. Paragraph [0027-0028]. Please see the annotation diagram of figure 2A.),
and a top electrode layer (Fig. 2A, #120 called an upper conductive electrode. Paragraph [0027]) disposed over the insulator layer such that the top electrode layer is spaced apart from the bottom electrode layer by the insulator layer (Fig. 2A. Paragraph [0027]- Takahashi discloses A MIM capacitor 114 is also arranged within the dielectric structure 104 between a lower interconnect layer 108a and an upper interconnect layer 108b. The MIM capacitor 114 includes a lower conductive electrode 116 that is separated from an upper conductive electrode 120 by a capacitor dielectric structure 118. In some embodiments, the lower conductive electrode 116 has a top surface that is below the capacitor dielectric structure 118, and the capacitor dielectric structure 118 has a top surface that is below the upper conductive electrode 120.),
wherein a sidewall of the bottom electrode layer is spaced apart from the fourth dielectric layer by a protection layer (Fig. 2A, illustrates a sidewall of the bottom electrode layer #116 have a protection layer #210 to separate the bottom electrode layer #116 from the fourth dielectric layer #202. Paragraph [0027]- Takahashi discloses a barrier layer 210 (e.g., titanium, titanium nitride, or the like) may separate the lower conductive electrode 116 from the dielectric structure 104.),
wherein a composition of the protection layer (Fig. 2A, #210 called a barrier. Paragraph [0027]) is different from a composition of the fourth dielectric layer (Fig. 2A, #202 called a plurality of ILD layers. Paragraph [0025 and 0027]-Takahashi discloses the plurality of stacked ILD layers 202 may comprise one or more of silicon dioxide, doped silicon dioxide (e.g., carbon doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or the like. a barrier layer 210 (e.g., titanium, titanium nitride, or the like) may separate the lower conductive electrode 116 from the dielectric structure 104.).
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Regarding claim 4, Takahashi teaches the semiconductor structure of claim 1, Takahashi further teaches wherein the first ESL and the third ESL comprise silicon carbide, wherein the second ESL comprises silicon nitride (Fig. 2A. Paragraph [0025]- Takahashi discloses the plurality of etch stop layers 204 may comprise silicon carbide, silicon nitride, titanium nitride, tantalum nitride, or the like.).
Regarding claim 6, Takahashi teaches the semiconductor structure of claim 1, Takahashi further teaches wherein the bottom electrode layer and the top electrode layer comprise titanium nitride (Fig. 2A. Paragraph [0041]- Takahashi discloses the lower conductive electrode 116 and/or the upper conductive electrode 120 may comprise titanium, titanium nitride, tantalum, tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten nitride (e.g., WN, WN.sub.2), tungsten silicon nitride, titanium aluminum, copper, aluminum, cobalt, ruthenium, iridium, iridium oxide, platinum, tungsten, or the like.), wherein the insulator layer comprises zirconium oxide and aluminum oxide (Fig. 2A. Paragraph [0042]- Takahashi discloses the capacitor dielectric structure 118 may comprise one or more of silicon dioxide, silicon nitride (e.g., Si.sub.3N.sub.4), tantalum oxide (e.g., Ta.sub.2O.sub.5), aluminum oxide (e.g., Al.sub.2O.sub.3), lanthanum oxide (e.g., La.sub.2O.sub.3), hafnium oxide (e.g., HfO.sub.2), zirconium oxide (e.g., ZrO.sub.2), zirconium aluminum oxide (e.g., ZrAl.sub.xO.sub.y), hafnium aluminum oxide (e.g., HfAl.sub.xO.sub.y), bromide titanium oxide (e.g., BrTiO.sub.2), strontium titanium oxide (e.g., SrTiO.sub.2, SrTiO.sub.3), or the like.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2, is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al. (US 20200135844 A1), hereinafter referenced as Takahashi in view of Ando et al. (US 20160181353 A1), hereinafter referenced as Ando.
Regarding claim 2, Takahashi teaches the semiconductor structure of claim 1, Takahashi fail to further teaches wherein tungsten is present at an interface between a top surface of the insulator layer and a bottom surface of the top electrode layer.
However, Ando explicitly teaches wherein tungsten is present at an interface (Fig. 11, #118 called an oxygen gettering layer. Paragraph [0052]) between a top surface of the insulator layer (Fig. 11, illustrates an interface #118 is between a top surface of the insulator layer #110 on the side. Paragraph [0052]-Ando discloses aluminum containing compounds to be used as the oxygen gettering layer 118 may include titanium aluminum nitride, titanium aluminum carbide, tantalum aluminum nitride, tantalum aluminum carbide, tungsten aluminum nitride, tungsten aluminum carbide, cobalt aluminum nitride, or cobalt aluminum carbide. Further in paragraph [0046]-Ando discloses the buried insulator layer 110 may be formed from any of several dielectric materials known in the art. Further in paragraph [0060-0061]-Ando discloses the recessed portion of the thin metallic film 120 will form an outer or buried electrode 128 for the trench capacitors of the present embodiment. Referring now to FIG. 10, yet another isotropic etching step is shown. In the present etching step, the second trench fill 126 may be completely removed from the deep trench 116 to expose the outer electrode 128.) and a bottom surface of the top electrode layer (Fig. 11, illustrates an interface #118 between the insulator layer #110 and a bottom surface of the top electrode layer #132. Paragraph [0052]-Ando discloses aluminum containing compounds to be used as the oxygen gettering layer 118 may include titanium aluminum nitride, titanium aluminum carbide, tantalum aluminum nitride, tantalum aluminum carbide, tungsten aluminum nitride, tungsten aluminum carbide, cobalt aluminum nitride, or cobalt aluminum carbide. Further in paragraph [0046]-Ando discloses the buried insulator layer 110 may be formed from any of several dielectric materials known in the art. Further in paragraph [0062]-Ando discloses Referring now to FIG. 11, subsequent to the etching steps described hereinabove, a node dielectric layer 130 and an inner electrode film 132 are deposited over the entire structure 100 and within the deep trench 116.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Takahashi of having a semiconductor structure, comprising: a contact feature disposed in a first dielectric layer; a first etch stop layer (ESL) over the contact feature and the first dielectric layer; a second dielectric layer over the first ESL; a second ESL over the second dielectric layer; a third dielectric layer over the second ESL; a third ESL over the third dielectric layer; a fourth dielectric layer over the third ESL; and a capacitor comprising: a bottom electrode layer continuously extending along a top surface of the fourth dielectric layer and vertically through the fourth dielectric layer, with the teachings of Ando of having wherein tungsten is present at an interface between a top surface of the insulator layer and a bottom surface of the top electrode layer.
Wherein having Takahashi’ a semiconductor structure, wherein tungsten is present at an interface between a top surface of the insulator layer and a bottom surface of the top electrode layer.
The motivation behind the modification would have been to obtain a trench capacitor semiconductor structure system that enhances integration without any conductive feature damage and minimum feature size, since both Takahashi and Ando are systems that relate to capacitor integrated semiconductor structure. Wherein Takahashi’s semiconductor structure system the same dielectric material can improve a quality of the multi-layer capacitor dielectric structure, thereby improving electrical characteristics of the MIM capacitor, while Ando’s semiconductor structure system that improve the performance and reliability of the traditional MIM capacitor. Please see Takahashi et al. (US 20200135844 A1), Paragraphs [0048] and Ando et al. (US 20160181353 A1), Paragraphs [0036]
Claim 3, is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al. (US 20200135844 A1), hereinafter referenced as Takahashi in view of HUANG et al. (US 20170092580 A1), hereinafter referenced as HUANG.
Regarding claim 3, Takahashi teaches the semiconductor structure of claim 1, Although, Takahashi teaches the first, second, and third ESL. Takahashi fail to explicitly teach wherein a composition of the second ESL is different from a composition of the first ESL or the third ESL.
However, HUANG explicitly teaches wherein a composition of the second ESL is different from a composition of the first ESL or the third ESL (Fig. 1-2K. Paragraph [0019]-HUANG discloses Referring to FIGS. 1 and 2C, method 100 then proceeds to operation 108 with forming a second etch stop layer (ESL) 212 over the first etch stop layer 210. In some embodiments, the second ESL 212 is formed of a material that is different from the first ESL 210.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Takahashi of having a semiconductor structure, comprising: a contact feature disposed in a first dielectric layer; a first etch stop layer (ESL) over the contact feature and the first dielectric layer; a second dielectric layer over the first ESL; a second ESL over the second dielectric layer; a third dielectric layer over the second ESL; a third ESL over the third dielectric layer; a fourth dielectric layer over the third ESL; and a capacitor comprising: a bottom electrode layer continuously extending along a top surface of the fourth dielectric layer and vertically through the fourth dielectric layer, with the teachings of HUANG of having wherein a composition of the second ESL is different from a composition of the first ESL or the third ESL.
Wherein having Takahashi’ a semiconductor structure, wherein a composition of the second ESL is different from a composition of the first ESL or the third ESL.
The motivation behind the modification would have been to obtain a trench capacitor semiconductor structure system that enhances integration without any conductive feature damage and minimum feature size, since both Takahashi and HUANG are systems that relate to capacitor integrated semiconductor structure. Wherein Takahashi’s semiconductor structure system the same dielectric material can improve a quality of the multi-layer capacitor dielectric structure, thereby improving electrical characteristics of the MIM capacitor, while HUANG’s semiconductor structure system that even though the third etching process selectively etches the first ESL layer the process still involves the etching solution simultaneously forming protective layer over the exposed underlying conductive feature to prevent the conductive feature from any damage. Please see Takahashi et al. (US 20200135844 A1), Paragraphs [0048] and HUANG et al. (US 20170092580 A1), Paragraphs [0029]
Claim 5, is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al. (US 20200135844 A1), hereinafter referenced as Takahashi in view of Tsai et al. (US 20210036097 A1), hereinafter referenced as Tsai.
Regarding claim 5, Takahashi teaches the semiconductor structure of claim 1, Although, Takahashi teaches the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer. Takahashi fail to explicitly teach wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer comprise silicon oxide.
However, Tsai explicitly teach wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer comprise silicon oxide (Fig. 1-10. Paragraph [0022]-Tsai discloses Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, or the like), nitrides (such as SiN, or the like), oxynitrides (such as SiON, or the like), oxycarbides (such as SiOC, or the like), carbonitrides (such as SiCN, or the like), carbides (such as SiC, or the like), combinations thereof, or the like. Further in paragraph [0024]-Tsai discloses the dielectric layers 303A-303D may include a low-k dielectric material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of Takahashi of having a semiconductor structure, comprising: a contact feature disposed in a first dielectric layer; a first etch stop layer (ESL) over the contact feature and the first dielectric layer; a second dielectric layer over the first ESL; a second ESL over the second dielectric layer; a third dielectric layer over the second ESL; a third ESL over the third dielectric layer; a fourth dielectric layer over the third ESL; and a capacitor comprising: a bottom electrode layer continuously extending along a top surface of the fourth dielectric layer and vertically through the fourth dielectric layer, with the teachings of Tsai of having wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer comprise silicon oxide.
Wherein having Takahashi’ a semiconductor structure, wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer comprise silicon oxide.
The motivation behind the modification would have been to obtain a trench capacitor semiconductor structure system that enhances integration without any conductive feature damage and minimum feature size, since both Takahashi and Tsai are systems that relate to capacitor integrated semiconductor structure. Wherein Takahashi’s semiconductor structure system the same dielectric material can improve a quality of the multi-layer capacitor dielectric structure, thereby improving electrical characteristics of the MIM capacitor, while Tsai’s semiconductor structure system allows for increasing the capacitor density and improving semiconductor device yield, while Ando’s semiconductor structure system that improve the performance and reliability of the traditional MIM capacitor. Please see Takahashi et al. (US 20200135844 A1), Paragraphs [0048] and Tsai et al. (US 20210036097 A1), Paragraphs [0012].
Allowable Subject Matter
Claim 7, along with its dependent claims, 8 are therefrom objected to as being dependent upon rejected base claims, claim 1, and 6, respectively but would be allowable if rewritten in independent form including all of the limitations of the base claims and any intervening claims, once the double patenting rejections are overcome.
Claim 9, an independent claim comprises of allowable subject matter, independent claim 9 and its dependent claims 10-13 are allowable once the double patenting rejections are overcome.
Claim 14, an independent claim comprises of allowable subject matter, independent claim 14 and its dependent claims 15-20 are allowable once the double patenting rejections are overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior arts fail to explicitly teach, further comprising: a barrier layer disposed between the bottom electrode layer and the top surface of the fourth dielectric layer as well as between the bottom electrode layer and sidewalls of the first ESL, the second dielectric layer, the second ESL, the third dielectric layer, the third ESL, and the fourth dielectric layer, wherein the protection layer interfaces the barrier layer, as claimed in claim 7.
Regarding claim 9, the prior arts fail to explicitly teach, wherein the trench barrier layer is spaced apart from a sidewall of a topmost one of the at least three dielectric layers by a cap layer, as claimed in claim 9.
Regarding claim 14, the prior arts fail to explicitly teach, depositing a sidewall cap layer over the pilot trench such that the sidewall cap layer overhangs edges of the pilot trench;
after the depositing, extending the pilot trench through the first ESL and the second dielectric layer to form a deep trench to expose the metal feature; conformally depositing a bottom electrode layer in the deep trench;
conformally depositing an insulator layer over the bottom electrode layer; and conformally depositing a top electrode layer over the insulator layer, as claimed in claim 14.
Conclusion
Listed below are the prior arts made of record and not relied upon but are considered pertinent to applicant`s disclosure.
(a) Lin (US 20160020267 A1)- The circuit has first trench capacitor (C1) comprising first and second capacitor plates arranged in a set of trenches (106) in a semiconductor substrate (102). Second trench capacitor (C2) is arranged over the first trench capacitor. The second trench capacitor comprises the second capacitor plate. Third capacitor plate is arranged in the set of the trenches and separated from the second capacitor plate by a capacitor dielectric. An interconnect structure (118) connects the first and third capacitor plates such that the trench capacitors are in parallel............Please see Fig. 1. Abstract.
(b) CHOU et al. (US 20180076276 A1)- The structure (20) has a first dielectric layer (21a) arranged on a surface of a substrate (2). A first conductive layer (22a) is arranged on the first dielectric layer. A second dielectric layer (21b) is arranged on the first conductive layer. A second conductive layer (22b) is arranged on the second dielectric layer. A third dielectric layer (21c) is arranged on the second conductive layer. A third conductive layer (22c) is arranged in a filled trench and on the third dielectric layer, where a top surface of the third conductive layer is lower than a surface of the second conductive layer......... ......... Fig. 1-2. Abstract.
(c) Suo et al. (US 20190051596 A1)- Methods of processing a substrate include providing a substrate having a polymer dielectric layer and a metal layer formed atop the polymer dielectric layer; depositing a plurality of polymer layers atop the substrate; patterning the plurality of polymer layers to form at least one via that extends from a top surface of an uppermost polymer layer to a top surface of the metal layer; and forming a three-dimensional metal-insulator-metal (3D MIM) capacitance stack in the at least one via and over a portion of the metal layer and the plurality of polymer layers.......... ......... Fig. 1-2. Abstract.
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/CHINEYERE WILLS-BURNS/Supervisory Patent Examiner, Art Unit 2673
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