DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 04/07/2026 has been accepted and entered. Claim 1-16 remain pending in this application. Applicant’s amendments to the Specification, Drawing, and Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed on 01/08/2026.
Claim Objections
Claim 13 is objected to because of the following informalities:
Claim 13 recites “wherein the second semiconductor layer are between” in Lines L2, but should read – wherein the second semiconductor layer is between--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al. (US20180219044A1-Zhao44).
Regarding claim 11, Zhao44 discloses a semiconductor device, comprising:
a first gate (First gate 105-Examiner’s annotated Fig 5);
a second gate over the first gate (Second gate 112 over First gate 105- Examiner’s annotated Fig 5);
a first contact (First contact 103- Examiner’s annotated Fig 5);
a second contact (Second contact 109-Examiner’s annotated Fig 5);
a third contact between the first gate and the second gate (Third contact 108/102-Examiner’s annotated Fig 5);
a first semiconductor layer between the first gate and the third contact (First semiconductor layer 101 between first gate 105 and third contact 108/102 as shown by the sloping-up dashed line-Examiner’s annotated Fig 5); and
a second semiconductor layer between the second gate and the third contact (Second semiconductor layer 107 between second gate 112 and third contact 108/102 as showed by the sloping-down dashed line-Examiner’s annotated Fig 5),
wherein the second semiconductor layer is between the second gate and the first semiconductor layer (Second semiconductor layer 107 being between the second gate 112 and the first semiconductor layer 101 as shown by the vertical dashed line-Examiner’s annotated Fig 5).
PNG
media_image1.png
690
956
media_image1.png
Greyscale
Regarding claim 12, Zhao44 discloses all the elements of claim 1, as noted above.
Zhao44 further discloses a semiconductor device
wherein the first semiconductor layer and the second semiconductor layer are between the second gate and the first semiconductor layer (the first semiconductor layer 101 and the second semiconductor layer 107 are between the second gate 112 and the first semiconductor layer 105- Examiner’s annotated Fig 5).
Regarding claim 13, Zhao44 discloses all the elements of claim 11, as noted above.
Zhao44 further discloses a semiconductor device
wherein the second semiconductor layer are between the first gate and the second gate (the second semiconductor layer 111 being between the first gate 105 and the second gate 112- Examiner’s annotated Fig 5).
Regarding claim 14, Zhao44 discloses all the elements of claim 11, as noted above.
Zhao44 further discloses a semiconductor device
wherein the first gate, the second gate, the first semiconductor layer and the second semiconductor layer are located at different level heights (the first gate 105, the second gate112, the first semiconductor layer 101 and the second semiconductor layer 107 being vertically stacked so located at different level heights -Examiner’s annotated Fig 5).
Regarding claim 15, Zhao44 discloses all the elements of claim 11, as noted above.
Zhao44 further discloses a semiconductor device
wherein the first semiconductor layer comprises a first channel region, a first source region electrically connected to the first contact and a first drain region electrically connected to the third contact. (the first semiconductor layer 101 comprising a first channel region in the central part of 101, a first source region/ left region in direct contact so electrically connected to the first contact 103, and a first drain region/ right region in direct contact so electrically connected to the third contact 108/102-Examiner’s annotated Fig 5).
Regarding claim 16, Zhao44 discloses all the elements of claim 11, as noted above.
Zhao44 further discloses a semiconductor device
wherein the second semiconductor layer comprises a second channel region, a second source region electrically connected to the second contact and a second drain region electrically connected to the third contact. (the second semiconductor layer 107 comprising a second channel region in the central part of 107, a second source region/ left region in direct contact so electrically connected to the second contact 109, and a second drain region/ right region in direct contact so electrically connected to the third contact 108/102-Examiner’s annotated Fig 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-7, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US20170133279A1-Peng79) in view of Zhao et al. (US20180219044A1-Zhao44).
Regarding claim 1, Peng79 discloses a semiconductor device, comprising:
a first gate (First/Bottom gate 124/125-Examiner's annotated Fig 10);
a second gate disposed over the first gate (Second/Top Gate 124/125 on bottom gate 124/125-Examiner's annotated Fig 10);
a first contact (First contact 140a-Examiner's annotated Fig 13);
a second contact (Second contact 126a-Examiner's annotated Fig 10) ;
a third contact disposed between the first gate and the second gate (Third contact 128 between first gate 125/124 and second gate 124/125-Examiner's annotated Fig 13, [0053] L10);
a first semiconductor layer (Layer 112/108'/112-Examiner's annotated Fig 10/13) disposed between the first gate and the third contact (disposed between bottom/first gate 125/124 and third contact 126a-Examiner's annotated Fig 13),
wherein the first semiconductor layer comprises
a first channel region (first channel 108'-Examiner's annotated Fig 13),
a first source region laterally in contact with the first contact (First source 112 laterally in contact with first contact 140a-Examiner's annotated Fig 13) and
a first drain region in contact with the third contact (First drain region 112 in contact with third contact 128-Examiner's annotated Fig 10), and
the first channel region laterally extends between the first drain region and the first contact (first channel region 108' laterally extending between the first drain region 112 and the first contact 140a/106-Examiner's annotated Fig 13); and
a second semiconductor layer disposed between the second gate and the third contact (Layer 112/108'/112 between second/top gate 118' and third contact 128-Examiner's annotated Fig 10/13),
wherein the second semiconductor layer comprises
a second channel region (second channel region 118'-Examiner's annotated Fig 10/13),
a second source region laterally in contact with the second contact and (source region 122 laterally in contact with second contact 126a-Examiner's annotated Fig 10)
a second drain region in contact with the third contact (second drain region 122 in contact with third contact 128-Examiner's annotated Fig 10), and
the second channel region laterally extends between the second drain region and the second contact (second channel 118' laterally extending between second drain region 122 and second contact 126a-Examiner's annotated Fig 10).
Peng79 does not disclose a semiconductor device
wherein the first semiconductor layer and the second semiconductor layer are between the first gate and the second gate.
Zhao44 teaches a semiconductor device
wherein the first semiconductor layer and the second semiconductor layer are between the first gate and the second gate (first semiconductor layer 101 and second semiconductor layer 107 being vertically stacked so between the second gate 112 and the first gate 105 as shown by the central dashed box-Examiner’s annotated Fig 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of peng79, as taught by Zhao44 for the purpose of having high gain, large noise margin (NM), low static power consumption, and exactly matched input and output voltage (Zhao44: [0085]).
PNG
media_image2.png
697
1018
media_image2.png
Greyscale
PNG
media_image3.png
756
1295
media_image3.png
Greyscale
PNG
media_image1.png
690
956
media_image1.png
Greyscale
Regarding claim 2, Peng79 and Zhao44 combination discloses all the elements of claim 1, as noted above.
Peng79 further discloses a semiconductor device
wherein the first gate and the second gate are disposed between first contact and the second contact (the first/bottom gate 124/125 and the top/second gate 124/125 are disposed between first contact 140a/106 and second contact 126a).
Regarding claim 3, Peng79 and Zhao44 combination discloses all the elements of claim 1, as noted above.
Peng79 further discloses a semiconductor device
wherein the first gate is located at a first level height (bottom/first gate 124/125 located at a first height-Examiner's annotated Fig 10),
the second gate is located at a second level height different from the first level height (top/second gate 124/125 located at a second height-Examiner's annotated Fig 10), and
the third contact is located a third level height between the first level height and the second level height (third contact 128 located between both gates 124/125-Examiner's annotated Fig 10).
Regarding claim 4, Peng79 and Zhao44 combination discloses all the elements of claim 3, as noted above.
Peng79 further discloses a semiconductor device
wherein the first contact extends from the first level height to the second level height (first contact 140a/106 from the first/bottom level height to the second/top level height-Examiner's annotated Fig 13).
Regarding claim 6, Peng79 and Zhao44 combination discloses all the elements of claim 1, as noted above.
Peng79 further discloses a semiconductor device
wherein the first semiconductor layer is spaced apart from the second contact (First semiconductor layer 112/108'/112 spaced apart from the second contact 126a-Examiner's annotated Fig 13), and
the second semiconductor layer is spaced apart from the first contact (Second semiconductor layer 122/118'/122 spaced apart from the first contact 140a/106-Examiner's annotated Fig 13).
Regarding claim 7, Peng79 and Zhao44 combination discloses all the elements of claim 1, as noted above.
Peng79 further discloses a semiconductor device further comprising:
a first gate insulating layer disposed between the first gate and the first semiconductor layer (first gate insulating layer 123 vertically stacked between, so disposed between, the first gate 125/124 and the first conductor layer 112/108'/112-Examiner's annotated Fig 10); and
a second gate insulating layer disposed between the second gate and the second semiconductor layer (second gate insulating layer123 vertically stacked between, so disposed between, the second gate 125/124 and the second conductor layer 122/118'/122-Examiner's annotated Fig 10).
Regarding claim 10, Peng79 and Zhao44 combination discloses all the elements of claim 1, as noted above.
Peng79 further discloses a semiconductor device further comprising:
wherein the first contact is spaced apart from the third contact by a first lateral distance (LD1-Examiner's annotated Fig 10),
the second contact is spaced apart from the third contact by a second lateral distance (LD2-Examiner's annotated Fig 10), and
the first lateral distance is different from the second lateral distance (Ld1 is different from LD2-Examiner's annotated Fig 10).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US20170133279A1-Peng79) in view of Nelson et al (US20190355756A1-Nelson56).
Regarding claim 8, Peng79 and Zhao44 combination discloses all the elements of claim 7, as noted above.
Peng79 and Zhao44 combination does not disclose a semiconductor device
wherein ends of the first gate insulating layer are in contact with the first contact and the second contact, and
ends of the second gate insulating layer are in contact with the first contact and the second contact.
Nelson56 teaches a semiconductor device
wherein ends of the first gate insulating layer (lower gate electrode 250 formed on dielectric layer so on the gate sidewalls-[0032]) are in contact with the first contact and the second contact (Examiner's annotated Fig 2), and
ends of the second gate insulating layer (upper gate electrode 250 formed on dielectric layer so on the gate sidewalls-[0032]) are in contact with the first contact and the second contact (250 in contact with first contact 122 and second contact 222-Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Peng79 in view of Zhao44, as taught by Nelson56 for the purpose of saving die area (Nelson56-[0026] L8).
PNG
media_image4.png
725
881
media_image4.png
Greyscale
Regarding claim 9, Peng79 and Zhao44 combination discloses all the elements of claim 7, as noted above.
Peng79 further discloses a semiconductor device
wherein the first semiconductor layer, the second semiconductor layer and the third contact are disposed between the first gate insulating layer and the second gate insulating layer (Examiner's annotated Fig 1, Examiner's annotated Fig 2).
PNG
media_image5.png
743
867
media_image5.png
Greyscale
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art of record does not teach or suggest a semiconductor device, namely “wherein the first semiconductor layer is located at a fourth level height between the first level heigh and the third level height, and the second semiconductor layer is located at a fifth level height between the second level height and the third level height”
References such as Peng et al. (US20170133279A1-Peng79), Zhao et al. (US20180219044A1-Zhao44), and Nelson et al (US20190355756A1-Nelson56) combination, teaches a semiconductor device, but does not teach or suggest a semiconductor device, namely “wherein the first semiconductor layer is located at a fourth level height between the first level heigh and the third level height, and the second semiconductor layer is located at a fifth level height between the second level height and the third level height.”, in combination with other claimed elements.
The balance of the claims are allowable for at least the above-stated reasons.
Response to Arguments
Applicant’s arguments see pages 7-8 of Remarks, filed on 04/07/2026 with respect to the 35 U.S.C 102 rejection of claims 1-4, 6-7, 10-11, and 14-16 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claims 1 and 11-16 have been amended to further define the claimed subject matter see pages 2-6 of Amendments to Claims, filed on 04/07/2026.
Amended claim(s) 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al. (US20180219044A1-Zhao44), as described above.
Therefore, claims 11-16 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al. (US20180219044A1-Zhao44).
Claim(s) 1-4, 6-7, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US20170133279A1-Peng79) in view of Zhao et al. (US20180219044A1-Zhao44), as described above.
Therefore, claim(s) 1-4, 6-7, 10 stand rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US20170133279A1-Peng79) in view of Zhao et al. (US20180219044A1-Zhao44).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US20170133279A1-Peng79) in view of Nelson et al (US20190355756A1-Nelson56), as described above.
Therefore, claim(s) 8-9 stand rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US20170133279A1-Peng79) in view of Nelson et al (US20190355756A1-Nelson56).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 04/15/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights