Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to the requirement for Restriction/Election filed on 03/09/2026, applicant elected, without traverse, Group I with original claims 1-14. Additionally, applicant canceled claims 15-20 and added new method claims 21-26 which read onto the elected claims of Group I. Therefore, the claims 1-14, and 21-26 will be examined upon the merits below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,2,5 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Islam et al (US 20210271020).
Islam et al teaches
[claim 1] A method for forming a package structure, comprising: forming electrical devices over a substrate (figure 22A, paragraph 0056, where elements 312, 314, 324 and 322 are formed over a substrate [element 102C from figure 7]);
forming an interconnect structure over front sides of the electrical devices (figure 22A, paragraph 0056, where element 312 has interconnect structures on the top of the device that connect to element 314, and likewise element 322 has interconnect structures formed on the top that connect to element 324 – where the top of each semiconductor die is the frontside);
thinning the substrate (figure 7, paragraph 0031, where element 102C is the substrate and thinned);
forming backside through vias connecting to backsides of the electrical devices (figure 22A, paragraph 0066, where element 510 are the vias formed on the backside [bottom side] of the electrical devices [element 312 and 322]);
attaching a waveguide layer over backsides of the electrical devices (figures 2 and 22A, where element 104 is the waveguide layer attached to the backside of the electrical devices [element 312 and 322] as seen in figure 22A);
and forming conductive vias through the waveguide layer and electrically connected to the backside through vias (figures 23A, paragraph 0070, where the vias through the waveguide layer [layer that contains element 104] are connected to the backside of the electric devices [element 310A, 310B and 620 in figure 23A]).
[claim 2] The method for forming a package structure as claimed in claim 1, further comprising: forming waveguide features over the waveguide layer (figure 23A, paragraph 0064, where element 120A is a waveguide feature formed over the waveguide layer [layer of element 650 that contains the waveguide element 104]);
and forming a dielectric layer covering the waveguide features and the conductive vias (figures 3 and 23A, paragraph 0025, where element 108 is the layer that contains the waveguide [element 104] as shown in figure 23A, and element 108 is a dielectric layer and covers the waveguide features [element 120/120A] and conductive vias [portions of element 650 that extend through the waveguide layer and connect to the backside of the electric devices 310A, 310B and 620]).
[claim 5] The method for forming a package structure as claimed in claim 2, further comprising: forming a bonding structure over the dielectric layer (figures 22A and 23A, paragraph 0052, where element 226 [conductive connectors] above element 104 [and subsequently element 108, the dielectric layer, as shown by figures 2-3], which is the bonding structure);
and bonding the bonding structure to an interposer structure, wherein the interposer structure comprises: interposer-through-vias electrically connected to the conductive vias (figures 22A and 23A, where element 510 of figure 22A [part of element 550] in the same position of figure 23A is the interposer structure which comprises through vias electrically connected from the conductive vias [element 112 through element 650 of figure 23A] to the electric devices [elements 310A and 310B of figure 23A]).
[claim 6] The method for forming a package structure as claimed in claim 5, wherein the interposer structure further comprises: an interposer substrate (figures 14, 22A and 23A, paragraphs 0040, and 0066, where element 510 of figure 22A is the same interposer structure as the interposer within element 650 of figure 23A, per paragraph 0040 each interposer is formed by the same process and thus the interposer structure in element 650 is formed with a substrate, similar to element 210 on a substrate element 202),
and an optical structure formed over the interposer substrate, wherein the interposer-through-vias penetrate through the interposer substrate (figure 23A, paragraphs 0063, and 0070, where element 620 is an optical structure [optical switch device] formed over the interposer [portion of element 650 which equates to element 510 of figure 22A], and has interposer through vias penetrating through the interposer substrate [element 404 of element 410 in figure 21A equivalent to element 610 of figure 23A]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Islam et al (US 20210271020) in view of Hsia et al (US 115992618).
Islam et al teaches all of the limitations of the parent claim, claim 2, but does not specifically disclose
[claim 3] The method for forming a package structure as claimed in claim 2, further comprising: forming an isolation layer over the waveguide features and the waveguide layer, wherein the conductive vias are formed through the isolation layer.
However, Hsia et al does teach
[claim 3] The method for forming a package structure as claimed in claim 2, further comprising: forming an isolation layer over the waveguide features and the waveguide layer, wherein the conductive vias are formed through the isolation layer (figure 22, col 14 line 58 – col 15 line 21, where element 330B is the isolation layer formed over the waveguide features [elements 104, 106 and 107 comprise the waveguide and the features] and the conductive vias [element 112] are formed through the isolation layer [element 330B layer]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Islam et al to incorporate the teachings of Hsia et al in order to form an isolation layer to minimize any electrical coupling that is unwanted, and maximizing efficiency of the device.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Islam et al (US 20210271020) in view of Lambert (US 20160306111).
Islam et al teaches all of the limitations of the parent claim, claim 2, but does not specifically disclose
[claim 4] The method for forming a package structure as claimed in claim 2, further comprising: forming an amorphous Si layer covering at least one of the waveguide features, and forming a conductive structure partially covering the amorphous Si layer and in contact with the conductive vias, the waveguide layer, and the amorphous Si layer.
However, Lambert does teach
[claim 4] The method for forming a package structure as claimed in claim 2, further comprising: forming an amorphous Si layer covering at least one of the waveguide features (figure 10, paragraph 0106, where element 530 is an amorphous silicon layer covering the waveguide [element 220] which also contains the waveguide features [as read into from Islam et al as modified above]);
and forming a conductive structure partially covering the amorphous Si layer and in contact with the conductive vias, the waveguide layer, and the amorphous Si layer (figures 9 and 10, paragraph 0100, where element 470 is a conductive structure partially covering the amorphous Si layer [element 530, which fills in element 510 form figure 9], and is contact with the waveguide layer [element 220], amorphous Si layer [element 530]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Islam et al as modified to incorporate the teachings of Lambert to incorporate an amorphous Si layer with a conductive strip to protect the waveguide feature as well as connect any circuitry to the waveguide and any circuitry below the waveguide to form a functioning waveguide device.
Claim(s) 7-12, and 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Islam et al (US 20210271020) in view of Odnoblyudov et al (US 20180240902).
Islam et al teaches
[claim 7] A method for forming a package structure, comprising: forming a first interconnect structure over a first side of the transistor (figure 22A, paragraph 0056, where element 312 has interconnect structures on the top of the electrical device [which contains a transistor] that connect to element 314, and likewise element 322 has interconnect structures formed on the top that connect to element 324 – where the top of each semiconductor die is the frontside);
at least partially removing the semiconductor substrate from a second side of the semiconductor substrate (figure 7, paragraph 0031, where element 102C is the substrate and thinned from the backside [bottom side of element 102C]);
forming a backside through via landing on a second side of the transistor (figure 22A, paragraph 0066, where element 510 are the vias formed on the backside [bottom side] of the electrical devices [element 312 and 322 which contain the transistors]);
disposing a waveguide layer over the backside through via (figures 2 and 22A, where element 104 is the waveguide layer attached to the backside of the electrical devices [element 312 and 322] as seen in figure 22A and over the through vias [element 112]);
forming first waveguide features over the waveguide layer (figure 23A, paragraph 0064, where element 120A is a waveguide feature formed over the waveguide layer [layer of element 650 that contains the waveguide element 104]);
and forming a second interconnect structure covering the first waveguide features and the waveguide layer, wherein the first interconnect structure and the second interconnect structure are at opposite sides of the transistor (figure 22A, paragraphs 0068-0069 where elements 226 over element 312 and 322 in figure 22A are the first interconnect structure, and element 510 is the second interconnect structure, both are over the waveguide and waveguide features [elements 104, 107 and 106] and the second interconnect structure is on a bottom side of the transistor [bottom side of elements 312 and 322] where the transistor is located).
[claim 21] A method for forming a package structure, comprising: forming a waveguide layer overlapping the transistor and the backside through via (figures 2 and 22A, where element 104 is the waveguide layer attached to the backside of the electrical devices [element 312 and 322 which contain the transistors] as seen in figure 22A and over the through vias [element 112]);
and forming conductive vias through the waveguide layer and electrically connected to the backside through via (figures 4-6 and 23A, paragraph 0028, where element 112 is formed through the waveguide layer [layer that contains element 104] and electrically connected to the backside through vias, which are element 114 within layer 510 [510 is shown in figure 22A, the equivalent portion is in figure 23A in element 650 which is the second inerposer and has conductive vias on the backside of the electrical devise [element 310A and 310B which contain the transistors]).
forming a contact landing on a first side of the source/drain structure in a third direction that is different from the first direction and the second direction (figure 22A, paragraph 0056, where element 312 has interconnect structures on the top of the electrical device [which contains a transistor] that connect to element 314, and likewise element 322 has interconnect structures formed on the top that connect to element 324 – where the top of each semiconductor die is the frontside, where the top side of the electrical devices [transistors] is the first side in a third direction [vertical/y-direction] which is different than the first [x-direction] and third direction [z-direction into the page]);
However, Islam et al does not specifically disclose
[claim 7] forming a transistor over a first side of a semiconductor substrate.
[claim 21] forming a transistor over a substrate, wherein the transistor comprises channel structures, a source/drain structure attaching to the channel structures in a first direction, and a gate structure wrapping around the channel structures and extending in a second direction that is different from the first direction; forming a contact landing on a first side of the source/drain structure in a third direction that is different from the first direction and the second direction; forming a backside through via connecting to a second side of the source/drain structure in the third direction;
However, Odnoblyudov et al does teach
[claim 7] forming a transistor over a first side of a semiconductor substrate (figure 3A, paragraphs 0048-0049, where element 360, 370 and 350 form the transistor formed on a front side of the substrate [element 315]);
[claim 21] forming a transistor over a substrate (figure 3A, paragraphs 0048-0049, where element 360, 370 and 350 form the transistor formed on a front side of the substrate [element 315]);
wherein the transistor comprises channel structures, a source/drain structure attaching to the channel structures in a first direction (figure 4, paragraph 0054, where the transistor comprises a gate [element 460] with source and drain adjacent in the first direction [established as the X-direction as seen in figure 4] to the gate [elements 470 and 450 are adjacent to element 460] and a backside via [element 412] is connected to a backside source drain via [element 412 connects to element 452 which all connects to the source structure 450]).
and a gate structure wrapping around the channel structures and extending in a second direction that is different from the first direction (figure 4, paragraph 0055, where element 430 [epitaxial layer] is the channel layer [semiconductor layer] and is vertically spaced apart from the substrate [element 415] and wrapped by the gate structure [element 460 is on both sides of the epitaxial layer as shown in figure 5], where the gate structure extends into the page [according to figure 4, as seen in figure 5 with the gate ‘lines]] which is the second direction and different than the first direction [x-direction])
forming a backside through via connecting to a second side of the source/drain structure in the third direction (figure 4, paragraph 0054, a backside via [element 412] is connected to a backside source drain via [element 412 connects to element 452 which all connects to the source structure 450] all located in the third direction [vertical/y-direction]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Islam et al to incorporate the teachings of Odnoblyudov et al to form a transistor in the electrical devices to operate electrical devices with the waveguide features, increasing the functionality of the device.
Regarding claims 8-10 and 22-24,
Islam et al as modified teaches all of the limitations of the parent claim, claim 7, and Islam et al further discloses
[claim 8] The method for forming a package structure as claimed in claim 7, wherein second waveguide features are embedded in the second interconnect structure (figure 23A, paragraphs 0063, and 0070, where element 620 is an optical structure [optical switch device] formed over the interposer [portion of element 650 which equates to element 510 of figure 22A], and has interposer through vias penetrating through the interposer substrate [element 404 of element 410 in figure 21A equivalent to element 610 of figure 23A] and thus are embedded in the second interconnect structure [element 510]).
[claim 9] The method for forming a package structure as claimed in claim 7, further comprising: forming a conductive via through the waveguide layer, wherein the conductive via is electrically connected to the backside though via (figures 4-6 and 23A, paragraph 0028, where element 112 is formed through the waveguide layer [layer that contains element 104] and electrically connected to the backside through vias, which are element 114 within layer 510 [510 is shown in figure 22A, the equivalent portion is in figure 23A in element 650 which is the second inerposer and has conductive vias on the backside of the electrical devise [element 310A and 310B which contain the transistors]).
[claim 10] The method for forming a package structure as claimed in claim 9, further comprising: patterning a first portion of the waveguide layer to form the first waveguide features before forming the conductive via, wherein the conductive via is formed through a second portion of the waveguide layer (figures 2-6, paragraphs 0020 and 0028, where element 104 is the waveguide and formed before the conductive through vias [element 112], where the conductive vias are formed through a second portion of the waveguide layer [that is the portion of the waveguide layer that the waveguide is not specifically located in in the horizontal direction]).
[claim 22] The method for forming a package structure as claimed in claim 21, further comprising: forming an interconnect structure electrically connected to the contact, wherein the interconnect structure and the waveguide layer are at opposite sides of the transistor (figure 22A, paragraph 0056, where element 312 has interconnect structures on the top of the electrical device [which contains a transistor] that connect to element 314, and likewise element 322 has interconnect structures formed on the top that connect to element 324 – where the top of each semiconductor die is the frontside – where the interconnect is on the top side of the transistor [electrical devices] and the waveguide is on the opposite side, that backside of the transistor [electrical devices]).
[claim 23] The method for forming a package structure as claimed in claim 22, wherein the interconnect structure is formed before forming the waveguide layer (figures 1-7 and figure 19, where the semiconductor devices [elements 312, 314, 322 and 324] are packaged onto the portion with the waveguide [element 104] after the waveguide is formed, thus signifying that the electrical devices were already formed before the waveguide was formed and thus the interconnect structures with them are formed before the waveguide is formed).
[claim 24] The method for forming a package structure as claimed in claim 21, further comprising: thinning the substrate before forming the backside through via ((figures 6-8, paragraphs 0031 and 0066, where element 102C [substrate] is thinned before forming elements 112 which are the backside through vias).
Regarding claims 11 and 12,
Islam et al as modified teaches all of the limitations of the parent claim, claim 7, but does not specifically disclose
[claim 11] The method for forming a package structure as claimed in claim 7, wherein the transistor comprises: a gate structure; and a source/drain structure formed adjacent to the gate structure, wherein the backside through via is connected to a backside of the source/drain structure.
[claim 12] The method for forming a package structure as claimed in claim 11, wherein the transistor further comprises: channel layers vertically spaced apart from the first side of the semiconductor substrate and from each other, wherein the channel layers are wrapped by the gate structure.
However, However, Odnoblyudov et al does teach
[claim 11] The method for forming a package structure as claimed in claim 7, wherein the transistor comprises: a gate structure; and a source/drain structure formed adjacent to the gate structure, wherein the backside through via is connected to a backside of the source/drain structure (figure 4, paragraph 0054, where the transistor comprises a gate [element 460] wth source and drain adjacent to the gate [elements 470 and 450 are adjacent to element 460] and a backside via [element 412] is connected to a backside source drain via [element 412 connects to element 452 which all connects to the source structure 450]).
[claim 12] The method for forming a package structure as claimed in claim 11, wherein the transistor further comprises: channel layers vertically spaced apart from the first side of the semiconductor substrate and from each other, wherein the channel layers are wrapped by the gate structure (figure 4, paragraph 0055, where element 430 [epitaxial layer] is the channel layer [semiconductor layer] and is vertically spaced apart from the substrate [element 415] and wrapped by the gate structure [element 460 is on both sides of the epitaxial layer as shown in figure 5]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Islam et al as modified to incorporate the teachings of Odnoblyudov et al to form a transistor in the electrical devices to operate electrical devices with the waveguide features.
Regarding claim 25,
Islam et al as modified above teaches all of the limitations of the parent claim, claim 21, but does not specifically disclose
[claim 25] The method for forming a package structure as claimed in claim 21, wherein the waveguide layer extends to a first edge of the package structure in the first direction.
However, MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Islam et al as modified to extend the waveguide layer as long as the package substrate to incorporate more waveguide functionality within different electronic devices for different use purposes.
Regarding claim 26,
Islam et al as modified teaches all of the limitations of the parent claim, claim 21, but does not specifically disclose
[claim 26] The method for forming a package structure as claimed in claim 21, wherein the waveguide layer has a non-planar top surface.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
B. Changes in Shape
In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Islam et al as modified to change the chape of the waveguide layer such that it is not perfectly planar but is instead non-planar or has any amount of curve or change in shape to accommodate specific use cases or specific device structures that may require a non-planar waveguide to operate the device efficiently.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Islam et al (US 20210271020), Odnoblyudov et al (US 20180240902) and in further view of Ambrosius et al (US 20200301068).
Islam et al as modified teaches all of the limitations of the parent claim, claim 7, but does not specifically disclose
[claim 13] The method for forming a package structure as claimed in claim 7, wherein the waveguide layer is a LiNbO3 layer.
However, Ambrosius et al does teach
[claim 13] The method for forming a package structure as claimed in claim 7, wherein the waveguide layer is a LiNbO3 layer (paragraph 0005, where the waveguide is made of LiNbO3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Islam et al to incorporate the teachings of Ambrosius et al to use LiNbO3 as the material for the waveguide to create an efficient waveguide layer for broadband usage to maximize the spectrum of wavelength that can be used in the waveguide.
Regarding claim 14,
Islam et al as modified above teaches all of the limitations of the parent claim, claim 13, and Islam et al further discloses
[claim 14] The method for forming a package structure as claimed in claim 13, wherein a width of the waveguide layer is smaller than a width of the semiconductor substrate (figure 2, paragraph 0020, where the waveguide [element 104] is less wide than the substrate layer [element 102C]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Weng et al (US 20230152542), Ecton et al (US 20230104330), Yu et al (US 20230161120), Yu et al (US 20220392881), Yu et al (US 10867982), and Huang et al (US 10459159) as devices with electronic/solid state devices combined with waveguides in a package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW JOHN ZABEL/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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