DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-8, 10-12 and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected inventions/species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1.17.2026.
Claims 9 and 13-15 are elected and examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 13, “ the capacitor die” lacks proper antecedent basis. Base claim 9 recites a first and second capacitor die and it is unclear if “the capacitor die” refers to either of those. For purposes of examination “the capacitor die” is treated as –the SoC die--. Claims 14 and 15 are rejected along with base claim 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20170206937 A1) in view of Chen et al. (US 20200091063 A1).
Regarding claim 9, Chang discloses a semiconductor package structure (Fig. 1), comprising:
a substrate (10) comprising a wiring structure (102);
a system-on-chip (SoC) die (211, “SoC 211”) disposed over the substrate and comprising a logic die ([0022])
a dynamic random access memory (DRAM) die (221 or 222, “DRAM dies 221 and 222”) stacked over and electrically coupled to the SoC die ([0024]), and comprising a memory die (221 or 222)
a first (multi-part and non-continuous which is not precluded by the claim; MPEP 2111) molding material (216 and 226) disposed over the substrate and surrounding (partly at least) the SoC die and the DRAM die (in the event the current claim language require a continuously formed molding material, which the examiner does not concede, it would have been obvious to one of ordinary sill in the art to provide a molding material as claimed in Chang so as to passivate/protect/insulate all devices in a semiconductor package from external conditions since the use of conventional materials, an molding in this case, to perform their known function is prima-facie obvious per MPEP 2144.07); and
a semiconductor die (301 or 302) electrically coupled to the SoC die and the DRAM die through the wiring structure (102) of the substrate (10, Fig. 1).
Chang fails to disclose (a) a system-on-chip (SoC) die comprising a logic die and a first capacitor die which comprises a plurality of capacitor structures and (b) a dynamic random access memory (DRAM) die comprising a memory die and a second capacitor die.
Chen discloses, regarding (a), a die (100A) comprising a logic die (in 110A, [0020]) and a first capacitor die (in 110B) which comprises a plurality of capacitor structures ([0026], Figs. 1A and 1D), and regarding (b), a memory die (100A) comprising a memory die (in 110A, [0020]) and a second capacitor die (in 110B, Figs. 1A and Fig. 1D.
It would have been obvious to one of ordinary skill in the art to include the configuration of Fig. 1D of Chen to both the SoC and DRAM of Chang and arrive at the claimed invention so as to improve “power integrity and system performance” (Chen, [0026]) of both SoC and DRAM of Chang.
Regarding claim 13,Chang/Chen discloses the semiconductor package structure as claimed in claim 9, wherein the SoC die (211) and the DRAM die (221 or 222) are stacked over a first surface (top) of the substrate (10), and the semiconductor die (301 or 302) is disposed over the first surface (top) of the substrate and adjacent to the capacitor (SoC) die (Fig. 1).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20170206937 A1) in view of Chen et al. (US 20200091063 A1) as applied to claim 13 above and further in view of Shi et al. ( of record, US 20190318975 A1).
Regarding claims 14 and 15, Chang/Chen fails to disclose (claim 14) the semiconductor package structure as claimed in claim 13, further comprising a package substrate disposed below a second surface of the substrate and electrically coupled to the wiring structure of the substrate, wherein the second surface is opposite to the first surface, and (claim 15) the semiconductor package structure as claimed in claim 13, wherein the substrate comprises an interposer substrate.
Shi discloses (claim 14) further comprising a package substrate (70, “package substrate 70”) disposed below a second surface (bottom) of the substrate (50) and electrically coupled (per 62) to the wiring structure (54) of the substrate, wherein the second surface (bottom) is opposite to the first surface (top, Fig. 1), and (claim 15) wherein the substrate (50) comprises an interposer substrate (Fig. 1. The term “interposer” is met by 50 since it is between structures. In the event element 50 is not an “interposer” substrate and the term “interposer” imparts additional structure not met by element 50, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include an interposer as claimed so as to provide high-density interconnects and mounting of different types of devices and/or because the use of conventional materials, an interposer in this case, to perform their known function is prima-facie obvious per MPEP 2144.07).
Finally, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the package and interposer of Shi in Chang/Chen and arrive at the claimed inventions so as to provide means to mount semiconductor packages onto highly integrated systems (e.g., a motherboard).
Response to Arguments
Applicant’s arguments with respect to claim 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner now relies on Chang et al. (US 20170206937 A1) and Chen et al. (US 20200091063 A1); see rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/ Primary Examiner, Art Unit 2818
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