DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group II (claims 9-15), Species B (Fig. 4) and Subspecies 1B (Fig. 1) with claims 9-15 elected by the applicant in the reply filed on 1.17.2026 is acknowledged. The traversal is on the ground that examination of all inventions/species/subspecies “in one application would not place an serious burden on the Examiner” (p. 7 of reply filed 1.17.2026). This is not found persuasive because applicant’s statement does not elaborate on reasons why there is no examining/searching burden and the previous Office Action (OA, mailed 11.18.2026) explains the reasons for burden for searching/examining all inventions/species/subspecies which the applicant has not addressed; hence, the reasons for burden of the previous OA are maintained and applicant’s traversal is not persuasive.
The requirement is still deemed proper and is therefore made FINAL.
The applicant alleges claims 9-15 read on Species B (Fig. 4) and Subspecies 1B (Fig. 1). Claim 10 recites “The semiconductor package structure as claimed in claim 9, wherein the capacitor die and the DRAM die are stacked over a first surface of the substrate, and the semiconductor die is disposed below a second surface of the substrate, wherein the second surface is opposite to the first surface” (emphasis added) which is not a feature of Fig. 4 (elected species B) which shows that the capacitor die, DRAM die and the semiconductor die are all disposed over the same surface.
Claim 10 (and dependent claims 11-12) read on non-elected species C (Fig. 5) and do not read on the elected species B (Fig.4); hence, claims 10-12 are hereby withdrawn by the examiner.
Claims 1-8, 10-12 and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected inventions/species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1.17.2026.
Claims 9 and 13-15 are elected and examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al. (US 20190318975 A1) in view of Gonzalez et al. (US 20020055225 A1).
Regarding claim 9, Shi discloses a semiconductor package structure (Fig. 1), comprising:
a substrate (50) comprising a wiring structure (54, [0028]);
a
a dynamic random access memory (DRAM) die (middle 26, “DRAM”, [0024]) stacked over and electrically coupled to the
a first molding material (40, [0028]) disposed over the substrate (50) and surrounding the
a semiconductor die (24) electrically coupled (at least at a device level, see [0027]) to the
Shi fails to discloses (i) a capacitor die disposed over the substrate and comprising a plurality of capacitor structures, (ii) a dynamic random access memory (DRAM) die stacked over and electrically coupled to the capacitor die, (iii) a first molding material disposed over the substrate and surrounding the capacitor die and the DRAM die, and (iv) a semiconductor die electrically coupled to the capacitor die and the DRAM die through the wiring structure of the substrate (emphasis added).
Note: modifying each memory die 26 (disclosed as DRAM in [0024]) of Shi to include a capacitor die and a DRAM die stacked thereon (bonded), meets the limitations as claimed.
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Gonzalez discloses (i) a capacitor die (top of 80, “a first semiconductor substrate 80”) over the substrate (12) and comprising a plurality of capacitor structures (50 and 52, Fig. 12) and (ii) a dynamic random access memory (DRAM) die (82, “second semiconductor substrate 82”) stacked over and electrically coupled to the capacitor die (Fig. 12, [0071-0072] – “Transistor structures 100 and 102, together with capacitor constructions 50 and 52 comprise a pair of DRAM cells” and “Transistors 100 and 102 can be considered to be DRAM sub-assemblies formed over base 72, and capacitors 50 and 52 can be considered DRAM sub-assemblies formed between base 12 and base 72”. See also, Abstract – “The invention includes a method of forming a DRAM cell. A first substrate is formed to comprise first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate comprising a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures”).
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Note: once each DRAM die 26 of Shi is modified to include the bonded structure of Fig. 12 of Gonzalez, the limitations (iii) a first molding material disposed over the substrate and surrounding the capacitor die and the DRAM die, and (iv) a semiconductor die electrically coupled to the capacitor die and the DRAM die through the wiring structure of the substrate are met by the combination.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify each DRAM die 26 of Shi with the arrangement of Gonzalez and arrive at the claimed invention so as to integrate DRAM capacitors to corresponding DRAM active devices within a single bonded structure and therefore create a compact and small DRAM die without the need of additional capacitor structures.
Regarding claim 13, Shi/Gonzalez (see Shi) discloses the semiconductor package structure as claimed in claim 9, wherein the capacitor die (modified 26 per Gonzalez) and the DRAM die (modified 26 per Gonzalez) are stacked over a first surface (top) of the substrate (50), and the semiconductor die (24) is disposed over the first surface (top) of the substrate and adjacent to the capacitor die (modified 26 per Gonzalez, Fig. 1)
Regarding claim 14, Shi/Gonzalez (see Shi) discloses the semiconductor package structure as claimed in claim 13, further comprising a package substrate (70, “package substrate 70”) disposed below a second surface (bottom) of the substrate (50) and electrically coupled (per 62) to the wiring structure (54) of the substrate, wherein the second surface (bottom) is opposite to the first surface (top, Fig. 1).
Regarding claim 15, Shi/Gonzalez (see Shi) the semiconductor package structure as claimed in claim 13, wherein the substrate (50) comprises an interposer substrate (Fig. 1. The term “interposer” is met by 50 since it is between structures).
In the event element 50 is not an “interposer” substrate and the term “interposer” imparts additional structure not met by element 50, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include an interposer as claimed so as to provide high-density interconnects and mounting of different types of devices and/or because the use of conventional materials (an interposer in this case) to perform their known function is prima-facie obvious (MPEP 2144.07).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/ Primary Examiner, Art Unit 2818