DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 28-33 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected invention and species. Election was made without traverse in the reply filed on 11/16/2025.
Claim 25 is further withdrawn from the consideration since claim 25 is not read on species I of figure 1.
Applicant’s election of claims 1-7 and newly added claims 21-24, 26-27 (instead of 1-7 and 21-27) in the reply filed on 11/16/2025 is acknowledged.
Claim Objections
Claim 21 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 7. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
► Claim 3 , lines 1-3, the limitation “wherein the plurality of first capacitor structures and the plurality of second capacitor structures are in contact with the first dielectric layer and spaced apart from the second dielectric layer” renders the claim indefinite. It is not clear what layer is spaced apart from the second dielectric. It is not clear which claim that claim 3 depended on.
For the purpose of examination, the limitation “wherein the plurality of first capacitor structures and the plurality of second capacitor structures are in contact with the first dielectric layer and spaced apart from the second dielectric layer” will read as -- wherein the plurality of first capacitor structures and the plurality of second capacitor structures are in contact with the first dielectric layer and the first dielectric layer spaced apart from the second dielectric layer”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7,21-24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al [US 2023/0024307] in view of HOSOGAI et al [US 2022/0028782].
► With respect to claim 1, Lee et al (fig 7, text [0001]-[0155])) discloses a semiconductor structure, comprising:
a first semiconductor substrate (110, IL1, IL2,IL3, text [0053]-[0054],[0067],[0104]);
a plurality of first capacitor structures (CPA, text [0101]) disposed in the first semiconductor substrate and arranged side-by-side;
a first dielectric layer (IL5, text [0102]) covering the plurality of first capacitor structures;
a second substrate (IL4, text [0102]) disposed over the first dielectric layer;
a plurality of second capacitor structures (CPB, text [0102]) disposed in the second semiconductor substrate and arranged side-by-side; and
a plurality of conductive pillars (550, text [0101]) extending in the first dielectric layer and electrically coupling the plurality of first capacitor structures to the plurality of second capacitor structures.
Lee et al fail to disclose a second substrate is a second semiconductor substrate. However, HOSOGAI et al (fig 5, text [0024]) disclose that a substrate (2, text [0024]) is the semiconductor substrate. Therefore, it would have been obvious to one skill in the art to use semiconductor material as taught by HOSOGAI et al into the device of Lee et al in order to provide the known purpose of support and cover the capacitor. Moreover, selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co., Inc. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
► With respect to claim 2, Lee et al (fig 7) discloses further comprising: a second dielectric layer (162, text [0146]) disposed over the second semiconductor substrate; and a conductive layer (170, text [4) disposed in the second dielectric layer and electrically coupled to the plurality of second capacitor structures.
► With respect to claim 3, Lee et al (fig 7) discloses wherein the plurality of first capacitor structures (CPA, text [0101]) and the plurality of second capacitor structures (CPB, text [0102]) are in contact with the first dielectric layer (IL5, text [0102]) and the first dielectric layer spaced apart from the second dielectric layer (162, text [0146]).
► With respect to claim 4, Lee et al (fig 7) discloses wherein the plurality of first capacitor structures (CPA, text [0101]) and the plurality of second capacitor structures (CPB, text [0102]) comprise deep trench capacitors.
► With respect to claim 5, Lee et al (fig 7, cols 8-9) discloses wherein each of the first capacitor structures (CPA, text [0101]) comprises: a first electrode layer (132, text [0062]); an interlayer dielectric layer (134, text [0062]) disposed over the first electrode layer and covering a top surface of the first electrode layer; and a second electrode layer (136, text [0062]) disposed over the interlayer dielectric layer and covering a top surface of the interlayer dielectric layer.
► With respect to claim 6, HOSOGAI et al (fig 5, text [0024]) discloses wherein the interlayer dielectric layer (3b, text [0027]) and the second electrode layer (3b, text [0027]) extend into the first dielectric layer (4, text [0030]). Moreover, the shape of the interlayer dielectric layer and the second electrode layer extend into the first dielectric layer are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious.
► With respect to claims 7 and 22, Lee et al (fig 7) discloses wherein a thickness of the first semiconductor substrate (110, IL1, IL2,IL3, text [0053]-[0054],[0067],[0104]) is greater than a thickness of the second substrate (IL4, text [0102]).
► With respect to claim 21, Lee et al (fig 7, cols 8-9) discloses wherein a sidewall of the first dielectric layer (IL5, text [0102]) is substantially coplanar with a sidewall of the first semiconductor substrate (110, IL1, IL2,IL3, text [0053]-[0054],[0067],[0104]) and a sidewall of the second substrate (IL4, text [0102]).
► With respect to claim 23, Lee et al (fig 7, text [0001]-[0155) discloses a semiconductor structure, comprising:
a first semiconductor substrate (110, IL1, IL2,IL3, text [0053]-[0054],[0067],[0104]);
a first dielectric layer (IL5, text [0102]) disposed over the first semiconductor substrate;
a second substrate (IL4, text [0102]) disposed over the first dielectric layer;
a plurality of first capacitor structures (CPA, text [0101]) arranged side-by-side, wherein each of the first capacitor structures comprises a top electrode layer (136, text [0062]); and
a plurality of second capacitor structures (CPB, text [0102]) disposed over the plurality of first capacitor structures and arranged side-by-side; and
a plurality of first conductive pillars (550, text [0101]) extending in the first dielectric layer and electrically coupling the plurality of first capacitor structures to the plurality of second capacitor structures.
Lee et al fail to disclose a second substrate is a second semiconductor substrate and the top electrode layer extending in the first dielectric layer. However, HOSOGAI et al (fig 5, text [0024]) disclose that a substrate (2, text [0024]) is the semiconductor substrate. Therefore, it would have been obvious to one skill in the art to use semiconductor material as taught by HOSOGAI et al into the device of Lee et al in order to provide the known purpose of support and cover the capacitor. Moreover, selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co., Inc. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
HOSOGAI et al (fig 5, text [0024]) discloses wherein the top electrode layer (3b, text [0027]) extending in the first dielectric layer (4, text [0030]). Moreover, the shape of the top electrode layer extending in the first dielectric layer are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious.
► With respect to claim 24, Lee et al (fig 7, cols 8-9) discloses wherein the plurality of first capacitor structures (CPA, text [0101]) is disposed in the first semiconductor substrate (110, IL1, IL2,IL3, text [0053]-[0054],[0067],[0104]) and the plurality of second capacitor structures (CPB, text [0102]) is disposed in the second substrate (IL4, text [0102]).
► With respect to claim 26, HOSOGAI et al (fig 5, text [0024]) discloses further comprising a plurality of second conductive pillars (11, 12) extending through the second semiconductor substrate (2, text [0024]) and electrically coupling the plurality of first capacitor structures (3a, 3b, 3c, text [0026]) to the plurality of second capacitor structures (3a, 3b, 3c, text [0026]).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al [US 2023/0024307] in view of HOSOGAI et al [US 2022/0028782] as applied to claim 23 above, and further in view of Murase et al [US 2019/0348496].
Lee et al disclose wherein the plurality of first capacitor structures (CPA, text [0101]) comprise deep trench capacitors disposed in the first semiconductor substrate. Lee et al fail to disclose the first semiconductor substrate comprises a doped region. However, Murase et al (fig 1) disclose the first semiconductor substrate (111, text [0030]-[0031]) comprises a doped region. Therefore, it would have been obvious to one skill in the art to have doped semiconductor substrate as taught by Murase et al into the device of Lee et al in order to provide suitable design function for the semiconductor memory device. Moreover, selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co., Inc. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Conclusion
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/THANHHA S PHAM/Primary Examiner, Art Unit 2812