DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-15 are cancelled.
Claims 16-20 are pending.
Claims 21-35 are new.
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on October 17, 2025 is acknowledged.
Applicant's election with traverse of Species C, FIG. 4 in the reply filed on October 17, 2025 is acknowledged. The traversal is on the ground(s) that Fig. 4 includes all the components shown in Fig. 2 or Fig. 3. This is not found persuasive because FIG. 4 does not have the components of items 203, 206, 208, 210, and 212 that are in FIG. 2.
The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the performing a patterning process on the dielectric structure in claim 21 and claim 31 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the after depositing the electrode layer on the dielectric structure, the electrode layer is further deposited in the trench so that the trench is partially filled by the electrode layer in claim 27 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the depositing a dielectric structure on a lower dielectric portion, the dielectric structure having a first dielectric portion and a second dielectric portion disposed to surround the first dielectric portion in claim 31 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 21. Claim 21 recites the limitation “depositing a filling material over the dielectric structure to fill the opening and removed excess amount of filling material” in the fifth paragraph of the claim language.
Regarding claim 29. Claim 29 recites the limitation “wherein the filling material is a dielectric material, an electrically conductive material, or a high-k dielectric material” in the fifth paragraph of the claim language.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 21-35 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 21, 27, and 31. Claim 21 recites the limitation “performing a patterning process on the dielectric structure to form an opening, a contact is the lower dielectric portion being exposed from the opening” in the second paragraph of the claim language.
Applicant does not have support in the originally filed specifications for performing a patterning process on the dielectric structure to form an opening.
Applicant does not have support in the originally filed specifications for performing all patterning process known to one skilled in the art.
Claims 27, and 31 rejected for the same analogous reasons as claim 21 above.
Claims 22-30, and 32-35 are rejected for dependence upon a 112(b) rejected instance claim.
Regarding claim 21 and 29. Claim 21 recites the limitation “depositing a filling material over the dielectric structure to fill the opening and removed excess amount of filling material” in the fifth paragraph of the claim language.
Applicant does not have support in the originally filed specifications for depositing a filling material over the dielectric structure to fill the opening and removed excess amount of filling material.
Applicant does not have support in the originally filed specifications for performing all patterning process known to one skilled in the art.
Claims 22-30 are rejected for dependence upon a 112(a) rejected instance claim
Claim 29 rejected for the same analogous reasons as claim 21 above.
Regarding claim 27. Claim 27 recites the limitation “after depositing the electrode layer on the dielectric structure, the electrode layer is further deposited in the trench so that the trench is partially filled by the electrode layer” in the second paragraph of the claim language.
Applicant’s originally filed specifications in [0025] state an electrode layer 248 is formed on the dielectric structure 238, and is formed in the openings 242 and the trench 244, where the openings 242 and the trench 244 are only partially filled by the electrode layer 248. Then, referring to FIG. 8, portions of the electrode layer 248 in FIG. 7 are removed to form a plurality of first electrodes 252 respectively in the openings 242 and a third electrode 256 in the trench 244 (i.e., the first and third electrodes 252, 256 are simultaneously formed)
However, Applicant does not have support in the originally filed specifications for the limitation after depositing the electrode layer on the dielectric structure, the electrode layer is further deposited in the trench so that the trench is partially filled by the electrode layer.
Claims 28-30 are rejected for dependence upon a 112(a) rejected instance claim
Regarding claim 31. Claim 31 recites the limitation “depositing a dielectric structure on a lower dielectric portion, the dielectric structure having a first dielectric portion and a second dielectric portion disposed to surround the first dielectric portion” in the second paragraph of the claim language.
Applicant does not have support in the originally filed specifications for depositing a dielectric structure on a lower dielectric portion, the dielectric structure having a first dielectric portion and a second dielectric portion disposed to surround the first dielectric portion.
Claims 32-35 are rejected for dependence upon a 112(a) rejected instance claim
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 21 and 27. Claim 21 recites the limitation “performing a patterning process on the dielectric structure to form an opening, a contact is the lower dielectric portion being exposed from the opening” in the second paragraph of the claim language.
It is unclear to the examiner as to what is encompassed in a pattering process. It is unclear to the examiner as to what steps, mask, process flow, and materials would be encompassed in performing a patterning process.
Claims 22-30 are rejected for dependence upon a 112(b) rejected instance claim
Regarding claim 27. Claim 27 is rejected for the same analogous reasons as claim 21.
Regarding claim 27. Claim 27 recites the limitation “after depositing the electrode layer on the dielectric structure, the electrode layer is further deposited in the trench so that the trench is partially filled by the electrode layer” in the second paragraph of the claim language.
Applicant’s originally filed specifications in [0025] state the first and third electrodes 252, 256 are simultaneously formed.
It is unclear to the examiner how the electrode layer is further deposited in the trench so that the trench is partially filled by the electrode layer after depositing the electrode layer on the dielectric structure when the claimed limitations are formed at the same time.
Claims 28 are rejected for dependence upon a 112(b) rejected instance claim
Regarding claim 27. Claim 27 recites the limitation "the method" in the last paragraph of the claim language.
It is unclear to the examiner as to what the limitation “the method, after partially removing the electrode layer” would encompass. It is unclear what the method is after partially removing the electrode, when after partially removing the electrode layer is part of the method.
Claims 28 rejected for dependence upon a 112(b) rejected instance claim.
Regarding claim 31. Claim 31 recites the limitation “depositing a dielectric structure on a lower dielectric portion, the dielectric structure having a first dielectric portion and a second dielectric portion disposed to surround the first dielectric portion” in the first paragraph of the claim language.
It is unclear as to the examiner as to how depositing a dielectric structure on a lower dielectric structure has a first dielectric portion and a second dielectric portion disposed to surround the first dielectric portion that is deposited.
It is unclear to the examiner as to what the deposited first dielectric portion and a second dielectric portion disposed to surround the first dielectric portion encompasses.
Claims 32-35 are rejected for dependence upon a 112(a) rejected instance claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 16 is rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Lim (U.S. 2015/0171159).
Regarding claim 16. Lim discloses a method for manufacturing (FIG. 2, and FIG. 9-17) a semiconductor structure (FIG. 3A, item 1), comprising:
forming a transistor (FIG. 3A; [0044]) in a lower dielectric portion (FIG. 3A, items 1600 and 1900);
forming ([0087]) a dielectric structure (FIG. 10, item 271) which is disposed on the lower dielectric portion (FIG. 10, item 100) and which includes a openings (FIG. 11, item 280) which are spaced apart from each other ([0089]);
forming ([0091]) first electrodes (FIG. 12, item 300P) respectively in the openings ([0091]);
forming ([0095]) support features (FIG. 13, item 400P) respectively in the openings ([0095]) and on the first electrodes (FIG. 13, item 300P);
forming (0104]) a capacitance dielectric layer (FIG. 16, item 500) which includes capacitance dielectric portions ([0065]) each covering one of the first electrodes (FIG. 16, item 300) and a corresponding one of the support features (FIG. 16, item 400); and
forming a layer ([0105]) including second electrodes (FIG. 17, item 600) over the capacitance dielectric layer (FIG. 17, item 500), the second electrodes (FIG. 17, item 600) being separated from the first electrodes (FIG. 17, item 300) through the capacitance dielectric portions (FIG. 17, item 500), respectively
Claims 16, 21-26, 29-30 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Park et al (U.S. 2012/0193761).
Regarding claim 16. Park et al discloses a method for manufacturing (FIG. 2, and FIG. 5A-5F) a semiconductor structure, comprising:
forming a transistor (FIG. 5A; [0019]) in a lower dielectric portion (FIG. 5A, item 113);
forming ([0039]) a dielectric structure (FIG. 5B, item 120) which is disposed on the lower dielectric portion and (FIG. 5B, item 115) which includes a openings (FIG. 5C, item 1129) which are spaced apart from each other ([0043]);
forming ([0044]) first electrodes (FIG. 5D, item 130) respectively in the openings ([0045]);
forming ([0048]) support features (FIG. 5D, item 140) respectively in the openings ([0045]) and on the first electrodes (FIG. 5D, item 130);
forming ([0027]-[0028]) a capacitance dielectric layer (FIG. 2, item 170) which includes capacitance dielectric portions (FIG. 2, item 170) each covering one of the first electrodes (FIG. 2, item 132) and a corresponding one of the support features (FIG. 2, item 170); and
forming a layer ([0029]) including second electrodes (FIG. 2, item 180) over the capacitance dielectric layer (FIG. 2, item 170), the second electrodes (FIG. 2, item 180) being separated from the first electrodes (FIG. 2, item 132) through the capacitance dielectric portions (FIG. 2, item 170), respectively
Regarding claim 21. Park et al disclose a method for manufacturing a semiconductor structure (FIG. 2, and FIG. 5A-5F), comprising:
depositing a dielectric structure (FIG. 5B, item 120) on a lower dielectric portion (FIG. 5B, item 115);
performing a patterning process ([0043]) on the dielectric structure (FIG. 5C, item 120a) to form an opening (FIG. 5C, item 129), a contact (FIG. 5B, item 113) in the lower dielectric portion (FIG. 5B, item 115) being exposed ([0043]) from the opening (FIG. 5B, item 129);
depositing an electrode layer (FIG. 5D, item 130) on the dielectric structure (FIG. 5D, item 120) and in the opening (FIG. 5D, item 129) so that the opening (FIG. 5D, item 129) is partially filled ([0045]) by the electrode layer (FIG. 5D, item 130);
partially removing ([0051]) the electrode layer (FIG. 5E, item 132) to leave a first portion of the electrode layer (FIG. 5E, item 132) in the opening (FIG. 5D, item 129), the first portion (FIG. 5E, item 132) of the electrode layer (FIG. 5D, item 130) serving as a first electrode (FIG. 5E, item 132);
after partially removing ([0051]) the electrode layer (FIG. 5F, item 132), depositing a filling material (FIG. 5G, item 150) over the dielectric structure (FIG. 5G, item 120a) and the first electrode (FIG. 5G, item 132) to fill the opening (FIG. 5G, item 132) and removing an excess amount ([0057]) of the filling material (FIG. 5H, item 152) to form a support feature (FIG. 5H, item 144 and 152) on the first electrode (FIG. 5H, item 132) in the opening (FIG. 5H, item 129), the first electrode (FIG. 5G, item 132) having a bottom region (FIG. 5G, bottom of item 132) disposed between the support feature (FIG. 5G, item 144) and the lower dielectric portion (FIG. 5G, item 115), and a first surrounding region (FIG. 5G, sides of item 132) disposed between the support feature (FIG. 5G, item 144) and the dielectric structure (FIG. 5G, item 120a), the first surrounding region (FIG. 5G, sides of item 132) having a lateral surface ([0005]) covered by the dielectric structure (FIG. 5G, item 120a) and a top surface (FIG. 5G, top surface of sides of item 132) exposed ([0005]) from the dielectric structure (FIG. 5F, item 120a);
partially removing ([0057]) the dielectric structure ([0057]) to expose the lateral surface ([0057]) of the first surrounding region ([0057]);
after partially removing ([0057]) the dielectric structure (FIG. 5H, item 170), depositing a capacitance dielectric layer (FIG. 2, item 170) to cover the first electrode (FIG. 2, item 132) and the support feature (FIG. 2, item 1144); and
depositing a second electrode (FIG. 2, item 180) on the capacitance dielectric layer (FIG. 2, item 170) opposite to the first electrode (FIG. 2, item 132)
Regarding claim 22. Park et al discloses all the limitations of the method of claim 21 above.
Park et al further discloses wherein the top surface and the lateral surface of the first surrounding region interface the capacitance dielectric layer ([0006]).
Regarding claim 23. Park et al discloses all the limitations of the method of claim 22 above.
Park et al further discloses wherein the second electrode (FIG. 2, item 180) includes a top region (FIG. 2, top part of item 180) disposed above an upper surface of the support feature (FIG. 2, item 144) opposite to the lower dielectric portion (FIG. 2, item 115), and a second surrounding region (FIG. 2, bottom part of item 180) extending downwardly from an edge of the top region (FIG. 2, top part of item 180) to surround the first surrounding region (FIG. 2, sides of item 132).
Regarding claim 24. Park et al discloses all the limitations of the method of claim 23 above.
Park et al further discloses wherein the top surface of the first surrounding region (FIG. 5E, sides of item 132) is flush with the upper surface of the support feature (FIG. 5E, sides of item 132), and is disposed underneath ([0018], [0027]) the top region of the second electrode (FIG. 2, item 180).
Regarding claim 25. Park et al discloses all the limitations of the method of claim 23 above.
Park et al further discloses wherein the capacitance dielectric portion (FIG. 2, item 170) includes a first region ([0027]-[0028]) disposed between ([0027]-[0028]) the top region ([0027]-[0028]) of the second electrode (FIG. 2, item 180) and the upper surface ([0027]-[0028]) of the support feature (FIG. 2, item 144), and a second region ([0027]-[0028]) extending downwardly ([0027]-[0028]) from an edge of the first region ([0027]-[0028]) and disposed between ([0027]-[0028]) the second surrounding region ([0027]-[0028]) of the second electrode (FIG. 2, item 180) and the first surrounding region ([0027]-[0028]) of the first electrode (FIG. 2, item 132).
Regarding claim 26. Park et al discloses all the limitations of the method of claim 25 above.
Park et al further discloses wherein the top surface ([0051]) of the first surrounding region (FIG. 5E, side of item 132) is flush ([0051]) with the upper surface ([0051]) of the support feature (FIG. 5E, side of item 132), and is connected ([0051]) to the first region of the capacitance dielectric portion ([0006]).
Regarding claim 29. Park et al discloses all the limitations of the method of claim 21 above.
Park et al further discloses wherein the filling material (FIG. 5G, item 150) is a dielectric material ([0055]), an electrically conductive material ([0055]), or a high-k dielectric material ([0055]).
Regarding claim 30. Park et al discloses all the limitations of the method of claim 21 above.
Park et al further discloses wherein the first electrode (FIG. 2, item 132) is electrically connected ([0019]) to a transistor ([0019]) in the lower dielectric portion (FIG. 2, item 115) through the contact (FIG. 2, item 113).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (U.S. 2012/0193761) as applied to claim 16 above, and further in view of Ode (U.S. 2013/0147013).
Regarding claim 17. Park et al disclose all the limitations of the method of claim 16 above.
Park et al further discloses further comprising: forming ([0044]) the first electrodes (FIG. 5D, item 130),
Park et al fails to explicitly disclose prior to forming the first electrodes forming a trench which is disposed in the dielectric structure and which surrounds the openings;
during forming the first electrodes, a third electrode is simultaneously formed in the trench; and
during forming the support features, an isolation feature is simultaneously formed in the trench over the third electrode.
However Ode teaches prior to forming ([0061]) the first electrodes (FIG. 9, item 22) forming a trench (FIG. 8, item 36A) which is disposed in the dielectric structure (FIG. 8, item 20) and which surrounds the openings (FIG. 8, item 36);
during forming ([0065]) the first electrodes (FIG. 9, item 22), a third electrode (FIG. 9, item 22A) is simultaneously formed in the trench (FIG. 8, item 36A); and
during forming ([0065]) the support features (FIG. 9, item 36), an isolation feature ([0037], i.e. FIG. 2A shows peripheral circuit region A1 and end A2 of a memory cell region) is simultaneously formed ([0065]) in the trench (FIG. 8, item 36a) over the third electrode (FIG. 9, item 22A).
Since Park et al and Ode teach capacitor structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method for manufacturing a semiconductor structure as disclosed to modify Park et al with the teachings of prior to forming the first electrodes forming a trench which is disposed in the dielectric structure and which surrounds the openings, during forming the first electrodes, a third electrode is simultaneously formed in the trench, and during forming the support features, an isolation feature is simultaneously formed in the trench over the third electrode as disclosed by Ode. The use of peripheral circuit region A1 and end A2 of a memory cell region in Ode provides for peripheral circuit region is arranged to surround memory cell regions, peripheral circuit region includes a sense amplifier circuit, a word line driving circuit, and an input/output circuit for external devices (Ode, [0036]).
Regarding claim 18. Park et al and Ode discloses all the limitations of the method of claim 17 above.
Park et al discloses wherein, forming the first electrodes (FIG. 5E, item 132) includes: forming an electrode layer (FIG. 5D, item 130) over the dielectric structure (FIG. 5D, item 120a) and in the openings (FIG. 5D, item 129) removing portions ([0051]) of the electrode layer (FIG. 5D, item 130) to form the first electrodes (FIG. 5D, item 130)
Ode further discloses wherein, forming the first electrode (FIG. 9, item 22) includes: forming an electrode layer (FIG. 9, item 22A) in the trench (FIG. 8, item 36A); and removing portions ([0070]; i.e. part of lower electrode 22 on mask film 35 was removed by CMP) of the electrode layer (FIG. 9, item 22) to form the third electrode (FIG. 9, item 22A).
Regarding claim 19. Park et al and Ode discloses all the limitations of the method of claim 18 above.
Ode further discloses wherein: after removing portions ([0070]) of the electrode layer (FIG. 9, item 22A), a portion ([0077]) of the dielectric structure (FIG. 12, item 20) surrounded by the trench (FIG. 12, item 22A) is removed to form a recess ([0077]; i.e. Parts of cover film 19 which are newly exposed by the removal of the part of fourth interlayer insulating film 20 which is located in the memory cell region);
Park et al further discloses a portion ([0043]) of the dielectric structure (FIG. 5C, item 120a) is removed to form a recess (FIG. 5C, item 129) and
forming the capacitance dielectric layer (FIG. 2, item 170) is performed by forming the capacitance dielectric layer (FIG. 2, item 170) over the support features (FIG. 2, item 144) and the first electrodes (FIG. 2, item 132) which are exposed from the recess (FIG. 5C, item 129).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al (U.S. 2012/0193761) and Ode (U.S. 2013/0147013) as applied to claim 19 above, and further in view of Choi et al (U.S. 2017/0186752).
Regarding claim 20. Park et al and Ode discloses all the limitations of the method of claim 19 above.
Park et al and Ode fails to explicitly disclose wherein, after forming the layer including the second electrodes, a top plate is formed over the second electrodes to fill the recess.
However, Choi et al teaches wherein, after forming the layer including the second electrodes (FIG. 13, item 250), a top plate (FIG. 13, item 257) is formed over the second electrodes (FIG. 13, item 250) to fill the recess ([0075]-[0078]).
Since Park et al, Ode and Choi et al teach Capacitor structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of manufacturing a semiconductor structure as disclosed to modify Park et al and Ode with the teachings of wherein, after forming the layer including the second electrodes, a top plate is formed over the second electrodes to fill the recess as disclosed by Choi et al. The use of the upper electrode may serve as a common plate electrode of the capacitor, a thickness ratio of the second upper electrode to the first upper electrode in Choi et al provides for a method of manufacturing a semiconductor device including a capacitor with improved electrical and mechanical reliability (Choi et al, [0006]).
Claims 27, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (U.S. 2012/0193761) as applied to claim 21 above, and further in view of Ode (U.S. 2013/0147013).
Regarding claim 27. Park et al discloses all the limitations of the method of claim 21 above.
Park et al further disclose wherein: In the patterning process ([0043]);
after depositing the electrode layer (FIG. 5D, item 130) on the dielectric structure (FIG. 5D, item 120);
after partially removing ([0051]) the electrode layer (FIG. 5F, item 132),; and
Park et al fails to explicitly disclose a trench is formed in the dielectric structure to surround the opening;
the electrode layer is further deposited in the trench so that the trench is partially filled by the electrode layer
a second portion of the electrode layer is left in the trench, the second portion of the electrode layer serving as a third electrode
the method, after partially removing the electrode layer, further comprises forming an isolation feature in the trench, so that the isolation feature surrounds the support feature.
However Ode teaches a trench (FIG. 8, item 36A) is formed ([0036], [0061]) in the dielectric structure (FIG. 8, item 20) to surround ([0036], [0061]) the opening (FIG. 8, item 36);
the electrode layer (FIG. 9, item 22) is further deposited in the trench (FIG. 9, item 36A) so that the trench is partially filled by the electrode layer (FIG. 9, item 22)
a second portion (FIG. 9, item 22A) of the electrode layer (FIG. 9, item 22) is left in the trench (FIG. 9, item 36A), the second portion (FIG. 9, item 22A) of the electrode layer (FIG. 9, item 22) serving as a third electrode (FIG. 9, item 22A).
the method, after partially removing ([0070]) the electrode layer (FIG. 9, item 22), further comprises forming an isolation feature ([0037], i.e. FIG. 2A shows peripheral circuit region A1 and end A2 of a memory cell region) in the trench (FIG. 8, item 36A), so that the isolation feature surrounds the support feature (FIG. 8, item 36).
Since Park et al and Ode teach capacitor structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method for manufacturing a semiconductor structure as disclosed to modify Park et al with the teachings of a trench is formed in the dielectric structure to surround the opening, the electrode layer is further deposited in the trench so that the trench is partially filled by the electrode layer, a second portion of the electrode layer is left in the trench, the second portion of the electrode layer serving as a third electrode, the method, after partially removing the electrode layer, further comprises forming an isolation feature in the trench, so that the isolation feature surrounds the support feature, as disclosed by Ode. The use of peripheral circuit region A1 and end A2 of a memory cell region in Ode provides for peripheral circuit region is arranged to surround memory cell regions, peripheral circuit region includes a sense amplifier circuit, a word line driving circuit, and an input/output circuit for external devices (Ode, [0036]).
Regarding claim 28. Park et al and Ode discloses all the limitations of the method of claim 27 above.
Ode further discloses wherein:
in depositing ([0078]) the filling material (FIG. 13, item 23), the filling material further fills the trench (FIG. 8, item 36A), after removing ([0079]) the excess amount ([0079]) of the filling material (FIG. 13, item 23), the filling material (FIG. 13, item 23) is formed ([0078]) into the isolation feature (FIG. 13, item 23) in the trench (FIG. 8, item 36A).
Park et al discloses the filling material (FIG. 5G, item 150) is formed into the support feature (FIG. 5H, item 144 and 152) in the opening (FIG. 5H, item 129).
Claims 31-35 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (U.S. 2012/0193761) and Ode (U.S. 2013/0147013).
Regarding claim 31. Park et al discloses a method for manufacturing a semiconductor structure (FIG. 2, and FIG. 5A-5F), comprising:
depositing a dielectric structure (FIG. 5B, item 120) on a lower dielectric portion (FIG. 5B, item 115), the dielectric structure (FIG. 5B, item 120) having a first dielectric portion (FIG. 5B, item 120 in the middle) and a second dielectric portion (FIG. 5B, item 120 on the edges) disposed to surround the first dielectric portion (FIG. 5B, item 120 in the middle);
performing a patterning process ([0043]) on the dielectric structure (FIG. 5C, item 120a) to form openings (FIG. 5C, item 129) in the first dielectric portion (FIG. 5C, item 120 in the middle) and contacts (FIG. 5C, item 113) in the lower dielectric portion (FIG. 5C, item 115) being exposed ([0043]) from the openings (FIG. 5C, item 129), respectively;
depositing a first electrode layer (FIG. 5D, item 130) on the dielectric structure (FIG. 5D, item 120) and in the openings (FIG. 5D, item 129) so that the openings (FIG. 5D, item 129) are partially filled ([0045]) by the first electrode layer (FIG. 5D, item 130);
partially removing ([0051]) the first electrode layer (FIG. 5E, item 132) to leave a first portion ([0051]) of the first electrode layer (FIG. 5E, item 132) in the openings ([0051]), the first portion (FIG. 5E, item 132) of the first electrode layer (FIG. 5E, item 132) including first electrodes (FIG. 5E, item 132) which are respectively in the openings ([0051]);
after partially removing ([0051]) the first electrode layer (FIG. 5F, item 132), depositing a filling material (FIG. 5G, item 150) over the dielectric structure (FIG. 5F, item 120), and the first portion (FIG. 5F, item 132) of the first electrode layer (FIG. 5F, item 132) so as to fill the openings ([0051]);
removing an excess amount ([0054]-[0057]) of the filling material (FIG. 5H, item 152) to form the filling material (FIG. 5H, item 152) into support features (FIG. 5H, item 152), the support features (FIG. 5H, item 152) being respectively formed in the openings ([0054]-[0057]),
after forming the support features (FIG. 5H, item 152), removing ([0054]-[0057]) the first dielectric portion ([0054]-[0057]) to form a recess ([0057]);
after removing ([0057]) the first dielectric portion (FIG. 5H, item), depositing a capacitance dielectric layer (FIG. 2, item 170) to cover the first electrodes (FIG. 2, item 132) and the support features (FIG. 2, item 144), the capacitance dielectric layer (FIG. 2, item 170) having capacitance dielectric portions (FIG. 2, item 132) each of which covers one of the first electrodes (FIG. 2, item 132) and a corresponding one of the support features (FIG. 2, item 144); and
depositing a second electrode layer (FIG. 2, item 180) over the capacitance dielectric layer (FIG. 2, item 170), the second electrode layer (FIG. 2, item 180) including second electrodes (FIG. 2, item 180) so that each of the capacitance dielectric portions (FIG. 2, item 170) is disposed between ([0018]) the one of the first electrodes (FIG. 2, item 132) and a corresponding ([0018]) one of the second electrodes (FIG. 2, item 180).
Park et al fails to explicitly disclose to form a trench along a boundary between the first dielectric portion and the second dielectric portion, so that the first dielectric portion is separated from the second dielectric portion, depositing a first electrode layer on the trench so that the trench are partially filled by the first electrode layer; and to leave a second portion of the first electrode layer on the second dielectric portion, the second portion of the first electrode layer including a surrounding electrode in the trench, a filling material over the dielectric structure, and the second portion of the first electrode layer so as to fill the trench; removing an excess amount of the filling material to form the filling material into an isolation feature the isolation feature being formed in the trench.
However Ode form a trench (FIG. 8, item 36A) along a boundary (FIG. 8, boundary item A1,A2) between the first dielectric portion (FIG. 8, item A1) and the second dielectric portion (FIG. 8, item A2), so that the first dielectric portion (FIG. 8, item A1) is separated from the second dielectric portion (FIG. 8, item A2),
depositing ([0065]) a first electrode layer (FIG. 9, item 22) on the trench (FIG. 9, item 36A) so that the trench (FIG. 9, item 36A) are partially filled ([0065]) by the first electrode layer (FIG. 9, item 22);
and to leave a second portion (FIG. 9, item 22A) of the first electrode layer (FIG. 9, item 22A) on the second dielectric portion (FIG. 9, item 20)
the second portion (FIG. 9, item 22A) of the first electrode layer(FIG. 9, item 22) including a surrounding electrode (FIG. 9, item 22A) in the trench (FIG. 9, item 36A)
a filling material (FIG. 13, item 23) over the dielectric structure (FIG. 13, item 20), and the second portion (FIG. 13, item 22A) of the first electrode layer (FIG. 13, item 22) so as to fill the trench (FIG. 13, item 23);
removing ([0078]-[0079]) an excess amount of the filling material (FIG. 13, item 23) to form ([0078]-[0079]) the filling material ([0078]-[0079]) into an isolation feature (FIG. 13, item 23), the isolation feature (FIG. 13, item 23) being formed in the trench (FIG. 13, item 36A);
Since Park et al and Ode teach capacitor structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method for manufacturing a semiconductor structure as disclosed to modify Park et al with the teachings of to form a trench along a boundary between the first dielectric portion and the second dielectric portion, so that the first dielectric portion is separated from the second dielectric portion, depositing a first electrode layer on the trench so that the trench are partially filled by the first electrode layer, and to leave a second portion of the first electrode layer on the second dielectric portion, the second portion of the first electrode layer including a surrounding electrode in the trench, a filling material over the dielectric structure, and the second portion of the first electrode layer so as to fill the trench, removing an excess amount of the filling material to form the filling material into an isolation feature the isolation feature being formed in the trench as disclosed by Ode. The use of peripheral circuit region A1 and end A2 of a memory cell region in Ode provides for peripheral circuit region is arranged to surround memory cell regions, peripheral circuit region includes a sense amplifier circuit, a word line driving circuit, and an input/output circuit for external devices (Ode, [0036]).
Regarding claim 32. Park et al and Ode disclose all the limitations of the method of claim 31 above.
Ode further discloses wherein a metal pattern (FIG. 8, item 18A) in the lower dielectric portion (FIG. 8, item 20) is exposed from the trench (FIG. 8, item 36A).
Regarding claim 33. Park et al and Ode disclose all the limitations of the method of claim 31 above.
Ode further discloses wherein the second portion (FIG. 9, item 22A) of the first electrode layer (FIG. 9, item 22) further includes a protective portion (FIG. 9, item 21) which covers ([0059]) a top surface ([0059]) of the second dielectric portion (FIG. 9, item 20) opposite to the lower dielectric portion (FIG. 3 and 9, item 9; [0039]) .
Regarding claim 34. Park et al and Ode disclose all the limitations of the method of claim 31 above.
Ode further discloses further comprising removing ([0078]-[0079]) portions of the capacitance dielectric layer (FIG. 13, item 23) and the second electrode layer (FIG. 13, item 24) which are formed on a top surface of the second dielectric portion (FIG. 9, item 20) opposite to the lower dielectric portion (FIG. 3 and 9, item 9; [0039]), so as to expose ([0080]) a top surface (FIG. 2, item 28) of an upper interconnect structure (FIG. 2, item 29) in the second dielectric portion (FIG. 2, item A1 of item 20); and
depositing a dielectric element (FIG. 2, items 26) to cover ([0043]) the second electrode layer (FIG. 2, items 24) and to fill the recess (FIG. 2, item A1 of items 20)
Regarding claim 35. Park et al and Ode disclose all the limitations of the method of claim 34 above.
Ode further discloses wherein: the dielectric element (FIG. 2, items 26) further covers ([0043]) the top surface of the upper interconnect structure (FIG. 2, item 29); and the method further comprises forming contact structures (FIG. 2, items 33 and 27) in the dielectric element (FIG. 2, items 26), the contact structures (FIG. 2, items 33 and 27) being electrically connected (FIG. 2, items 27) to the second electrodes (FIG. 2, items 24) and the upper interconnect structure (FIG. 2, items 29), respectively.
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/S.E.B./Examiner, Art Unit 2815