Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species I in the reply filed on 09/30/2025 is acknowledged.
Claims 3, 6, and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 09/30/2025.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Claim 11 recite:
“a first metal-oxide semiconductor field-effect transistor in the first well region;
a first control circuit connected to a first gate of the first metal-oxide semiconductor field-effect transistor”.
Mapping these limitations to the elected figs. 5-6:
“a first metal-oxide semiconductor field-effect transistor (any of the 4 transistors formed in the wells 28 or 34) in the first well region 28 or 34”.
However, none of the figures show a first control circuit connected to a first gate of the first metal-oxide semiconductor field-effect transistor.
Similarly, none of the figures show a second control circuit connected to a second gate of the second metal-oxide semiconductor field-effect transistor, wherein the second gate is formed in the second well region.
Regarding claim 12:
None of the figures show “wherein the first gate of the first metal-oxide semiconductor field-effect transistor floats to discharge accumulated charge through the first metal-oxide semiconductor field-effect transistor and the second gate of the second metal-oxide semiconductor field-effect transistor floats to discharge accumulated charge through the second metal-oxide semiconductor field-effect transistor”, in context of claim 11.
Note: first metal-oxide semiconductor field-effect transistor is a MOS transistor formed in the first well region and second metal-oxide semiconductor field-effect transistor is a MOS transistor formed in the second well region as cited in claim 11.
Regarding claims 13-14:
None of the figures show “…wherein a first drain/source region of the first metal-oxide semiconductor field-effect transistor is connected to the first well region” and “wherein a first drain/source region of the second metal-oxide semiconductor field-effect transistor is connected to the second well region”, in context of claim 11.
Note: first metal-oxide semiconductor field-effect transistor is a MOS transistor formed in the first well region and second metal-oxide semiconductor field-effect transistor is a MOS transistor formed in the second well region as cited in claim 11.
Therefore, the limitations described above must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 11 recites “a first control circuit connected to a first gate of the first metal-oxide semiconductor field-effect transistor; and a second control circuit connected to a second gate of the second metal-oxide semiconductor field-effect transistor”, wherein “the first metal-oxide semiconductor field-effect transistor in the first well region and the second metal-oxide semiconductor field-effect transistor in the second well region”. However, the disclosure does not have any description of the first and second control circuits connected to the gates of the first and second MOSFETs formed in the first and second wells, respectively.
Instead, in figs. 5-6 and [0044-0045] of Applicant’s PGPUB (US 20240274597 A1), the disclosure describes the first and second control circuits connected to the gates of MOSFETs of the well-PID protection circuits (e.g., 120, 122, 124, 126). The MOSFETs of the well-PID protection circuits are formed in the P substrate 132, not in the first and second well regions (PW1, PW2, NW1, NW2).
Regarding claim 12, the disclosure does not have any description of floating gates formed in the first and second wells, in context of claim 11.
Regarding claims 13-14, the disclosure does not have any description of wherein a first drain/source region of the first metal-oxide semiconductor field-effect transistor is connected to the first well region” and “wherein a first drain/source region of the second metal-oxide semiconductor field-effect transistor is connected to the second well region”, in context of claim 11.
Therefore, claims 11-14 are rejected under this section for failing to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites “a first metal-oxide semiconductor field-effect transistor” “having a drain region connected to one of the p-well/n-well regions” which causes ambiguity in the claim, as it is unclear if it is one of the protection metal-oxide semiconductor field-effect transistors cited in claim 1, which have selected drain/source regions connected to the p-well regions and the n-well regions or a different MOSFET. For examination purpose, they will be interpreted as same.
Claim 8 recites “a first metal-oxide semiconductor field-effect transistor” “having a source region connected to one of the p-well/n-well regions” which causes ambiguity in the claim, as it is unclear if it is one of the protection metal-oxide semiconductor field-effect transistors cited in claim 1, which have selected drain/source regions connected to the p-well regions and the n-well regions or a different MOSFET. For examination purpose, they will be interpreted as same.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chou et al. (US 20060145263 A1; hereinafter “Chou”).
In re claim 11, Chou discloses a circuit (figs. 1-2), comprising:
a substrate 20 (¶6);
a first well region 21 over the substrate 20 (¶6);
a second well region 22 over the substrate 20 (¶6);
a first metal-oxide semiconductor field-effect transistor 15 in the first well region 21 (¶6);
a second metal-oxide semiconductor field-effect transistor 16 in the second well region 22 (¶6);
a first control circuit 13 connected to a first gate 27 of the first metal-oxide semiconductor field-effect transistor 21 (¶4-6); and
a second control circuit 13 connected to a second gate 36 of the second metal-oxide semiconductor field-effect transistor (¶4-6).
In re claim 12, Chou discloses in figs. 1-2, the circuit of claim 11,
wherein the first gate 27 of the first metal-oxide semiconductor field-effect transistor floats to discharge accumulated charge through the first metal-oxide semiconductor field-effect transistor 15 and
the second gate 36 of the second metal-oxide semiconductor field-effect transistor 16 floats to discharge accumulated charge through the second metal-oxide semiconductor field-effect transistor (¶5, 9).
In re claim 13, Chou discloses in figs. 1-2, the circuit of claim 11, wherein a first drain/source region of the first metal-oxide semiconductor field-effect transistor 24 is connected to the first well region 21 and a second drain/source region 23 of the first metal-oxide semiconductor field-effect transistor is connected to the substrate 20 (via substrate contact 26) (¶6).
In re claim 14, Chou discloses in figs. 1-2, the circuit of claim 13, wherein a first drain/source region of the second metal-oxide semiconductor field-effect transistor 33 is connected to the second well region 31 and a second drain/source region 32 of the second metal-oxide semiconductor field-effect transistor is connected to the substrate 20 (via substrate contact 35) (¶6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20240030184 A1; hereinafter “Chen”) in view of Morino et al. (US 20090278204 A1; hereinafter “Morino”).
In re claim 1, Chen discloses a circuit (figs. 1-4), comprising:
a substrate 240, 350, 310 (¶34, 46);
the substrate 310 including n-channel metal-oxide semiconductor field-effect transistors 313, 315 (¶44-45);
n-well regions 311, 312 over the substrate 310 and including p-channel metal-oxide semiconductor field-effect transistors 314, 316 (¶44-45);
drain/source regions 361, 362, 373, 374, 365, 366, 377, 378 of protection metal-oxide semiconductor field-effect transistors 355-358 (¶46-48);
at least one control circuit (VSS or VDD);
first conductive connections (portions of 391 and 383, 384 and 392; hereinafter “CND1”) that connect (e.g., electrically connect through diffusion regions 321, 333, 324, 336) selected drain/source regions 361, 374, 365, 378 to the p-well regions and the n-well regions 311, 312;
second conductive connections that connect selected n-channel metal-oxide semiconductor field-effect transistors 355 and p-channel metal-oxide semiconductor field-effect transistors 356 to one another (portion of 391 that connect FETS 355 and 356; hereinafter “CND2”); and
third conductive connections configured to connect gates of the protection metal-oxide semiconductor field-effect transistors to the at least one control circuit (as shown in fig. 4, gates 345 and 346 are connected to VDD, VSS via third conductive connections; hereinafter “CND3”).
Chen does not expressly disclose n-channel metal-oxide semiconductor field-effect transistors are formed in p-wells.
In the same field of endeavor, Morino discloses a circuit (figs. 21-22) wherein n-channel metal-oxide semiconductor field-effect transistors 200n, 300n are formed in P-wells PW0, PW1 over a substrate Sub (¶174).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Morino into the circuit of Chen and form the nMOSFETs in p-wells in order to enhance isolation between nMOSFETs and pMOSFETs.
In re claim 2, Chen, as modified by Morino, discloses the circuit of claim 1.
Chen further discloses in figs. 1-4, the circuit of claim 1,
wherein a first drain/source region 361 of a first protection metal-oxide semiconductor field-effect transistor 355 is connected to one of the p-well regions or to one of the n-well regions 311 and
a second drain/source region 362 of the first protection metal-oxide semiconductor field-effect transistor 355 is connected to the substrate 350.
In re claim 7, Chen, as modified by Morino, discloses the circuit of claim 1.
Chen further discloses in figs. 1-4, the circuit of claim 1, wherein a first metal-oxide semiconductor field-effect transistor 355 is an n-channel metal-oxide semiconductor field-effect transistor having a drain region connected to one of the p-well/n-well regions (e.g., electrically connect via diffusion regions 321) or the substrate, whichever has a higher voltage.
In re claim 8, Chen, as modified by Morino, discloses the circuit of claim 1.
Chen further discloses in figs. 1-4, the circuit of claim 1, wherein a first metal-oxide semiconductor field-effect transistor is a p-channel metal-oxide semiconductor field-effect transistor 358 having a source region 377 connected to one of the p-well/n-well regions or the substrate 350, whichever has a higher voltage.
In re claim 9, Chen, as modified by Morino, discloses the circuit of claim 1.
Chen does not expressly disclose the circuit comprising at least one of a buried layer and a deep buried layer.
However, Morino further discloses in figs. 21-22, the circuit comprising at least one of a buried layer and a deep buried layer DNW0 (¶181).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Morino into the circuit of Chen to further facilitate discharging of accumulated charges and prevent plasma induced damage (¶181 of Morino).
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, as modified by Morino, as applied to claim 1 above, and further in view of Chou et al. (US 20060145263 A1; hereinafter “Chou”).
In re claim 4, Chen, as modified by Morino, discloses the circuit of claim 1, but does not expressly disclose wherein a gate of one of the protection metal-oxide semiconductor field-effect transistors floats to discharge accumulated charge through the one of the protection metal-oxide semiconductor field-effect transistors and
the at least one control circuit is connected to the gate to bias off the one of the protection metal-oxide semiconductor field-effect transistors during operation of the circuit.
In the same field of endeavor, Chou discloses in figs. 1-2, a circuit
wherein a gate 27 of one of the protection metal-oxide semiconductor field-effect transistors floats to discharge accumulated charge through the one of the protection metal-oxide semiconductor field-effect transistors 15 and
the at least one control circuit 13 is connected to the gate 27 to bias off the one of the protection metal-oxide semiconductor field-effect transistors during operation of the circuit (¶4-5).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chou into the circuit of Chen, as modified by Morino, in order to protect the circuit from plasma induced damages during manufacturing and turned off to avoid interference with the normal operations of the circuit (¶2-5 of Chou).
In re claim 5, Chen as modified by Morino and Chou discloses the circuit of claim 4 outlined above.
Chen further discloses in figs. 1-4, the circuit of claim 1,
wherein a first drain/source region 361 of a first protection metal-oxide semiconductor field-effect transistor 355 is connected to one of the p-well regions or to one of the n-well regions 311 and
a second drain/source region 362 of the first protection metal-oxide semiconductor field-effect transistor 355 is connected to the substrate 350.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, as modified by Morino, as applied to claim 1 above, and further in view of Xu et al. (US 20230411383 A1; hereinafter “Xu”).
In re claim 10, Chen, as modified by Morino, discloses the circuit of claim 1, but does not expressly disclose wherein the at least one control circuit includes one or more of an inverter, a NOR gate, and a NAND gate.
In the same field of endeavor, Xu discloses a circuit (fig. 7) wherein the at least one control circuit 700, 400 connected to a discharge transistor 500 includes one or more of an inverter (e.g., 701), a NOR gate, and a NAND gate (¶98-106).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Xu into the circuit of Chen, as modified by Morino, in order to reduce complexity of the circuit.
Conclusion
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893