DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election of Invention II directed to a method, Claims 18-20 in the response to restriction requirements filed 11/04/25 is acknowledged. With the response, the Applicant cancelled all device claims and added new method Claims 21-37.
Status of Claims
Claims 18-37 are examined on merits herein.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown during intermediate steps of the device manufacturing or the features canceled from the claims:
“first drain electrode” and “second drain electrode” - cited by the method Claim 17: paragraphs 0118-0121 of the published application (US 2024/0395824) state that Figs. 18 show first and second drain electrodes, 112a and 112b, accordingly; however, Figs. 18, as well as following Figs. 19 through 23, show structures comprised two first source electrodes 110a and two second source electrodes 110b and show no elements (drains) with numbers 112a and 112b. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Abstract
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
Abstract of the application is objected to since the current abstract is directed to a device, while the applicant chose (in the Response to Restriction Requirements) a method for examination and cancelled all device claims; accordingly, the abstract shall be modified to include method steps.
Specification
The disclosure is objected to because of the following informalities:
Paragraphs 0094 and 0112 of the published application unnecessary repeats each of Ga2O3 and ZnO - twice (the same typo is repeated by Claim 21).
Paragraphs 0119 and 0125 of the published application identify Ti, Al, Ti/Al/Ti, W, Cu, PdCo – as nitrides or carbides.
Paragraph 0129 has a sentence citing: “Fig. 24A is a further vertical cross-sectional view of semiconductor circuit of Figs. 24A and 24B”, which is unclear.
In spite of understandable method steps illustrated by Figs. 3 through 24, it is unclear how from a structure shown in Figs. 18 (with 110a belonging to a source electrode of a further PMOSFET and 110b belonging to a source electrode of a future NMOSFET) a combined structure of Fig. 24 was created. Do Figs. 3 through Figs. 24 are directed to creation of two sets of invertors (each comprising a single CMOS) and only one of invertors (without electrical connections shown in Figs. 2B and 2C) is shown in Fig. 24D, such that Figs. 24A and 24C are cross-sections of a structure that is split into two parts to create Fig. 24D? If so, this shall be clarified, since currently, the specification allows to conclude that all these method steps are directed to creation of a single circuit comprised one NMOSFET and one PMOSFET, and paragraphs 0129-0130 of the published application, directed to final method steps, state that Fig. 24D is a perspective view of Fig. 24A to Fig. 24C. For a better presentation of what the examiner finds as unclear, Figs. 18 and 25 are shown below.
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Appropriate corrections/clarifications are required.
Claim Objections
Claim 20 is objected to because of the following informalities:
Claim 20 has a recitation (shown with the examiner’ underlying): “Ga2O3, ZnO, GaO, Ga2O3, InO, In2O3, InZnO, ZnO”. Examiner suggests changing the recitation to: “Ga2O3, ZnO, GaO, InO, In2O3, InZnO”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 21-37 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claims 21: Claim 21 recites in line 3: “forming an electrically insulating structure having a slab geometry” and recites in line 7: “forming an etch-stop layer over the electrically insulating structure”. A combination of recitation is unclear, since conflicts with the specification of the application, teaching (Figs. 3-5, paragraphs 0099-0104) that an etch-stop layer 306 is formed prior to formation of an electrically insulating structure 202, since layer 306L (from which layer 306 is created) is disposed on layer 202L (from which structure 202 is created), and both elements, 306 and 202, are formed by etching - an initial step of which creates layer 306 and only after that –creates structure 202, e.g., layer 306 cannot be created on 202 since 202 is created following creation of 306.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, line 3 was interpreted as: “forming a stack of an etch-stop layer disposed over an electrically insulating structure”, while limitation of line 7 was deleted.
In re Claim 31: Lines 4-7 of Claim 31 have a same issue as lines 3 and 7 of Claim 21, which makes Claim 31 unclear and requires appropriate corrections. For this Office Action, the lines 4-7 of Claim 31 were interpreted in a manner similar to lines 3 and 7 of Claim 21.
In re Claims 22-30 and 32-37: Claims 22-30 and 32-37 are rejected under 35 U.S.C. 112(b) due to dependency either on Claim 21 or on Claim 31.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2013/0168771) in view of Shimizu (US 2021/0288158).
In re Claim 18, Wu teaches a method of forming a semiconductor circuit (Abstract), comprising:
forming (Figs. 2-5, paragraphs 0015-0018) an electrically insulating structure 214 (in a center of Fig. 5) having a slab geometry comprising a first surface and a second surface that are parallel to one another and that are each oriented in respective planes that are perpendicular to a thickness direction;
forming (Figs. 10-12, paragraphs 0025-0028, and Figs. 29-31, paragraphs 0056-0062) a p-type semiconductor layer 226 and 824 on the first surface;
forming (Figs. 6-9, paragraphs 0020-0024, and Figs. 29-31, paragraphs 0056-0062) a n-type semiconductor layer 222 and 822 on the second surface;
forming (Figs. 29-30, paragraphs 0059) a gate dielectric layer 812 in contact with the p-type semiconductor layer 226/284 and the n-type semiconductor layer 222/822;
forming a first source electrode and a first drain electrode in contact with the p-type semiconductor layer;
forming a second source electrode and a second drain electrode in contact with the n-type semiconductor layer; and
forming (Figs. 29-30, paragraph 0059) a gate electrode 814 in contact with the gate dielectric layer 812.
Wu does not teach, at least, explicitly, a step of forming a first source electrode and a first drain electrode in contact with the p-type semiconductor layer and does not a step of forming a second source electrode and a second drain electrode in contact with the p-type semiconductor.
Shimizu teaches (Fig. 1, paragraphs 0041-0057 and 0072) metallic a source electrode 12/13 electrically connected to p-type and n-type regions 32 and 30 (with region 32 being a source region) and a metallic drain electrode 14 is electrically connected with a drain region 24.
Wu and Shimizu teach analogous arts directed to field effect transistors, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Wu device and method in view of the Shimizu teaching, since they are from the same field of endeavor, and Shimizu created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Wu device and method by adding source and drain electrodes for first and second transistors (per Shimizu), including steps of forming a first source electrode and a first drain electrode in contact with the p-type semiconductor layer and forming a second source electrode and a second drain electrode in contact with the n-type semiconductor layer, wherein it is desirable using metallic source and drain electrodes for external contacts rather than using semiconductor source and drain regions.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wu/Shimizu in view of Hur et al. (US 20150311341).
In re Claim 19, Wu/Shimizu teaches the method of Claim 18 as cited above, but fails to teach that the method further comprising configuring the semiconductor circuit as an inverter circuit by performing operations comprising:
electrically connecting the first source electrode to a voltage supply and the second source electrode to a ground voltage terminal;
electrically connecting the gate electrode to an input signal terminal; and
electrically connecting the first drain electrode and the second drain electrode to an output signal terminal.
Hur teaches an inverter circuit comprised (Fig. 12, paragraphs 0050, 0144-0145) an electrical connection between a first source electrode to a voltage supply Vdd, an electrical connection between a second source electrode to a ground voltage Vss, an electrical connection of a gate electrode to an input terminal IN, and an electrical connection between first and second drains to an output terminal OUT.
Wu/Shimizu and Hur teach analogous arts directed to devices comprised a PMOS and an NMOS and to methods of manufacturing these devices, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Wu/Shimizu device and method in view of the Hur teaching, since they are from the same field of endeavor, and Hur created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Wu/Shimizu device and method in view of Hur disclosure, including: electrically connecting the first source electrode to a voltage supply and the second source electrode to a ground voltage terminal; electrically connecting the gate electrode to an input signal terminal; and electrically connecting the first drain electrode and the second drain electrode to an output signal terminal, when it is desirable to extend applicability of to-be created device into a field of inverters.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wu/Shimizu in view of Genrikh et al (US 2008/0001184).
In re Claim 20, Wu/Shimizu teaches the method of Claim 18 as cited above, with Shimizu teaching creation of the first and second source and drain electrodes.
Wu further teaches a method comprising:
forming (Figs. 7-9, paragraph 0023) the n-type semiconductor layer 222/822 (as shown for Claim 18);
forming (Figs. 10-12) the p-type semiconductor layer 226/826 (as shown for Claim 18);
forming (Fig. 30) the gate dielectric layer 812 to comprise at least one of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-alumina – Wu teaches most of the above materials in paragraph 0059;
forming (Figs. 4-5) the electrically insulating structure 214 to comprise at least one of AlOx, SiO2, and SiNx – Wu teaches silicon oxide and silicon nitride (paragraph 0018); and
forming one or more of the first source electrode, the first drain electrode, the second source electrode, the second drain electrode to comprise one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti, and Al: Shimizu teaches Al, W or Cu (paragraph 0072).
Wu/Shimizu does not teach that the n-type semiconductor material comprises ) to comprise at least one of amorphous silicon, Al2O5Zn2 doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, Ga2O3, InO, In2O3, InZnO, ZnO, TiOx, and alloys thereof, and does not teach that the p-type semiconductor to comprise at least one of NiO, SnO, and Cu2O.
Genrikh teaches (paragraphs 0034-0035) that a p-type semiconductor includes NiO and an n-type semiconductor includes ZnO, InGaZnO.
Wu/Shimizu and Genrikh teach analogous arts directed to devices comprised a n-type semiconductors and p-type semiconductors, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Wu/Shimizu device and method in view of the Hur teaching, since they are from the same field of endeavor, and Hur created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Wu/Shimizu device and method by substituting the p-type and n-type semiconductor materials with the n-type and p-type semiconductor materials taught by Genrikh, if the manufacturer prefers the n-type and p-type semiconductor materials disclosed by Genrikh. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results. In addition, in accordance with MPEP 2144.07 Art Recognized Suitability for an Intended Purpose, the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
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See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) and/or Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988).
Allowable Subject Matter
Claims 21 and 31, as interpreted, contain allowable subject matter. Claims 22-30 and 32-37 depend either on Claim 21 or on Claim 31.
Reason for Indicating Allowable Subject Matter
Re Claim 21: The prior arts of record, alone or in combination, fail to anticipate or render obvious such combination of limitations of Claim 21, as interpreted as: “forming a stack of an etch-stop layer disposed over an electrically insulating structure” and: “the etch-stop layer is positioned between the n-type semiconductor layer and the p-type semiconductor layer”, in combination with other limitations of the claim.
Re Claim 31: The prior arts of record, alone or in combination, fail to anticipate or render obvious such combination of limitations of Claim 31, as interpreted as: “forming a stack of an etch-stop layer disposed over an electrically insulating structure” and: “the etch-stop layer is positioned between the n-type metal-oxide semiconductor layer and the p-type metal-oxide semiconductor layer”, in combination with other limitations of the claim.
The prior arts of record, in addition to prior arts cited above, also include: Jacob et al. (US 2016/0225676), Liaw (US 2019/0326300), and Liaw (US 2020/0006149).
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440.
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 11/12/25