Prosecution Insights
Last updated: April 19, 2026
Application No. 18/321,116

PACKAGE INCLUDING A DUMMY BAR AND METHODS OF FORMING THE PACKAGE

Non-Final OA §102
Filed
May 22, 2023
Examiner
OH, JAEHWAN
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Limited
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
555 granted / 656 resolved
+16.6% vs TC avg
Moderate +10% lift
Without
With
+10.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
23 currently pending
Career history
679
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
47.4%
+7.4% vs TC avg
§102
36.8%
-3.2% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 656 resolved cases

Office Action

§102
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (U.S. Patent Application Publication 2022/0157777, hereinafter referred to as Yang). As to claim 1, Yang teaches 1. A package, comprising: a first die and a second die in an encapsulant layer; and a dummy bar in the encapsulant layer and adjacent a gap between the first die and the second die. [see 21, 40 in Fig. 2A and 2B for example] As to claim 2, Yang teaches 2. The package of claim 1, wherein the second die is adjacent to the first die in a first direction, the gap extends longitudinally in a second direction perpendicular to the first direction and a center of the dummy bar in the first direction is substantially aligned with a center of the gap in the first direction. [see 21, 40 in Fig. 2A and 2B for example] As to claim 3, Yang teaches 3. The package of claim 2, wherein the dummy bar comprises a rectangular shape in a plan view and includes a long side in the first direction and a short side in the second direction. [see 21, 40 in Fig. 2A and 2B for example] As to claim 4, Yang teaches 4. The package of claim 3, wherein a length of the long side of the dummy bar is in a range from 1mm to 30mm and a length of the short side of the dummy bar is in a range from 0.1mm to 10.0mm. [see 21, 40 in Fig. 2A and 2B for example] As to claim 5, Yang teaches 5. The package of claim 3, wherein a ratio of a length of the encapsulant layer in the first direction to the length of the long side of the dummy bar is in a range from 1.5 to 15. [see 21, 40 in Fig. 2A and 2B for example] As to claim 6, Yang teaches 6. The package of claim 2, wherein the encapsulant layer is in the gap and the dummy bar is adjacent to the encapsulant layer in the second direction. [¶0057] As to claim 7, Yang teaches 7. The package of claim 1, wherein a thickness of the dummy bar is in a range from 10µm to 5000µm. [¶0036] As to claim 8, Yang teaches 8. The package of claim 1, wherein the dummy bar comprises a silicon bar. [¶0040] As to claim 9, Yang teaches 9. The package of claim 1, wherein a ratio of a height of an upper surface of the encapsulant layer to a height of an upper surface of the dummy bar is in a range from 1 to 10. [¶0036] As to claim 10, Yang teaches 10. The package of claim 1, wherein an upper surface of the dummy bar is substantially coplanar with an upper surface of the first die and the second die. [¶0036] As to claim 11, Yang teaches 11. The package of claim 1, further comprising: a package module comprising: a lower module portion including a lower molding layer and a local silicon interconnect (LSI) die in the lower molding layer; and an upper module portion on the lower module portion and including the encapsulant layer and the first die, the second die and the dummy bar in the encapsulant layer. [see 44 in Fig. 4A for example] As to claim 12, Yang teaches 12. The package of claim 11, wherein the dummy bar is mounted on the lower molding layer of the lower module portion and is separated from the first die and the second die in a second direction. [see 40 and 44 in Fig. 4A for example] As to claim 13, Yang teaches 13. The package of claim 11, wherein the LSI die is configured to connect the first die and the second die, and the gap is over the LSI die in a third direction perpendicular to a first direction and a second direction. [see 40 and 44 in Fig. 4A for example] As to claim 14, Yang teaches 14. The package of claim 12, wherein the encapsulant layer contacts the lower molding layer between the dummy bar and the first and second dies and between the dummy bar and an edge of the lower molding layer. [see Fig. 4A for example] As to claim 15, Yang teaches 15. A method of forming a package, the method comprising: attaching a first die and a second die to a surface; attaching a dummy bar to the surface adjacent a gap between the first die and the second die; and forming an encapsulant layer on the first die, the second die and the dummy bar. [see 21, 40 in Fig. 2A and 2B for example] As to claim 16, Yang teaches 16. The method of claim 15, wherein the attaching of the first die and the second die comprises attaching the first die and the second die such that the second die is adjacent to the first die in a first direction and the gap extends longitudinally in a second direction perpendicular to the first direction. [see 21, 40 in Fig. 2A and 2B for example] As to claim 17, Yang teaches 17. The method of claim 16, wherein the attaching of the dummy bar comprises attaching the dummy bar such that a center of the dummy bar in the first direction is substantially aligned with a center of the gap in the first direction, and such that a long side of the dummy bar extends in the first direction and a short side of the dummy bar extends in the second direction. [see 21, 40 in Fig. 2A and 2B for example] As to claim 18, Yang teaches 18. The method of claim 16, wherein the forming of the encapsulant layer comprises forming the encapsulant layer in the gap such that the dummy bar is adjacent to the encapsulant layer in the second direction. [see 21, 40 in Fig. 2A and 2B for example] As to claim 19, Yang teaches 19. The method of claim 15, further comprising: forming a package module including: a lower module portion including a lower molding layer and a local silicon interconnect (LSI) die in the lower molding layer; and an upper module portion on the lower module portion, wherein the attaching of the first die and the second die comprises attaching the first die and the second die to a surface of the lower molding layer, the attaching of the dummy bar comprises attaching the dummy bar to the surface of the lower molding layer, and the forming of the encapsulant layer comprises forming the encapsulant layer on the first die, the second die and the dummy bar in the upper module portion. [see 44 in Fig. 4A for example] As to claim 20, Yang teaches 20. A package, comprising: a package substrate; a package module on the package substrate, comprising: a first die and a second die in an encapsulant layer; and a dummy bar in the encapsulant layer and adjacent a gap between the first die and the second die; and a package lid on the package module and attached to the package substrate. [see 21, 40 in Fig. 2A and 2B for example] Conclusion Claims 1-20 are rejected as explained above. The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAEHWAN OH whose telephone number is (571) 270-5800. The examiner can normally be reached on Monday - Friday 9:00 AM-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAEHWAN OH/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

May 22, 2023
Application Filed
Feb 07, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+10.4%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 656 resolved cases by this examiner. Grant probability derived from career allow rate.

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