DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 30 March 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15 and 17 are rejected under 35 U.S.C. 103 as unpatentable over Chaware et al. (“Chaware” US Patent No. 9,418,909), and Lin et al. (“Lin” US 2019/0067157).
Regarding claim 15, Chaware discloses:
A method of forming a package structure (Figures 1, 2), comprising:
forming a package lid (150, 154) comprising a package lid foot portion (154) and a package lid plate portion (150) on the package lid foot portion (154, see Figure 1), wherein the package lid plate portion (150) comprises a patterned bottom surface (see Figures 1, 2) having a plurality of recessed portions (recesses 164, Figure 1);
attaching a package module (dies 114 and interposer 112) to a package substrate (122, see Figure 1), wherein the package module includes a plurality of dies (114, see Figure 1);
placing a thermal interface material (TIM) layer (“adhesive” 140, provides heat dissipation for the dies, see col. 4, lines 4-14, thus is interpreted as a thermal interface material “TIM”) on the package module (114, 112, TIM 140 is placed on the upper surfaces of dies 114 during manufacturing, see Figure 7 and col. 6, lines 52-54); and
attaching the package lid (150, 154) to the package substrate (122, see Figure 1) such that the package lid plate portion (150) is on the package module (114, 112, see Figure 1) and at least a portion of the TIM layer (140) is disposed in the plurality of recessed portions (164, see Figures 1, 2 and col. 6, lines 61-64).
Chaware does not disclose an encapsulant layer around the plurality of dies, and wherein the attaching of the package lid is performed such that the TIM layer is between the encapsulant layer and an outermost recessed portion of the plurality of recessed portions.
However, Lin discloses in Figure 18 an encapsulant layer (108) around the plurality of dies (70A/B), and wherein the attaching of the package lid (208/212) is performed such that the TIM layer (122/118) is between the encapsulant layer (108) and an outermost recessed portion the plurality of recessed portions (recessed portions here are considered the recessed portions of the package lid 208/212 occupied or filled by the thermal/dummy bumps 118, which are considered a part of the TIM, since these are disposed such that they fill the recessed portions and aid in heat dissipation, see para. [0062], the outermost recessed portions being the leftmost and rightmost recessed portions in Figure 18, if you were to draw a line from the outermost recessed portion to the encapsulant, the line would intersect the TIM layer, thus the TIM layer is therebetween).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lin into the teachings of Chaware to include the encapsulant layer and the configuration thereof for the purpose of covering and protecting the plurality of dies within the package (Lin, para. [0036]).
Regarding claim 17, Lin teaches wherein the encapsulant layer (108) includes an inner portion between the plurality of dies (70A/B, see portion of 108 between the dies in Figure 18), and the attaching of the package lid (208/212) is performed such that the TIM layer (122/118) is between the inner portion of the encapsulant layer (portion of 108 between dies 70A/B) and the plurality of recessed portions (recessed portions of the package lid 208/212 occupied or filled by the thermal/dummy bumps 118).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lin into the teachings of Chaware to include elements as claimed above and as taught by Lin for the purpose of disposing encapsulant between dies which buries the dies and further protects them (Lin, para. [0036]). Further, the combination of the claimed elements above would result with no change in their respective function and the predictable result of heat dissipation through the encapsulant between the dies, because the encapsulant material will transfer heat from the sidewalls of the dies up to the TIM and package lid, thereby further aiding in heat dissipation of the package. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chaware and Lin as applied to claim 15 above, and further in view of Hoffman et al. (“Hoffman” US 2008/0296757).
Regarding claim 16, Chaware discloses wherein the attaching of the package lid (150, 154) to the package substrate (122) comprises pressing the patterned bottom surface of the package lid plate portion (150) onto the TIM layer (140, lid is secured to the die which would involve a placement and pressing technique, as the TIM 140 is flowed into the recesses, see col. 7, lines 1-2) such that the plurality of recessed portions (164) are filled with the TIM layer (140, see Figures 1, 2, and col. 7, lines 1-2).
In the event that Chaware does not disclose a pressing method, which the examiner does not concede, Hoffman discloses in Figure 9 pressing the patterned bottom surface of the package lid plate portion (recesses on bottom surface of 10, see, for example, Figure 9, also called “channels”) onto the TIM layer (20) such that the plurality of recessed portions are filled with the TIM layer (para. [0060]).
It would have been obvious to one having ordinary skill in the art to incorporate the “pressing” teachings of Hoffman into the teachings of Chaware for the purpose of preventing any voids at interfaces of the channels (recesses) and the fluid (Hoffman, para. [0060]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chaware and Lin as applied to claim 15 above, and further in view of Kishi et al. (“Kishi” US 2018/0076107).
Regarding claim 18, Chaware discloses wherein the forming of the package lid (150) comprises forming the plurality of recessed portions (164) to be arranged in staggered array (staggered array of recesses 164 shown in Figure 6) having a plurality of columns (see Figure 6).
Chaware does not explicitly disclose wherein the plurality of recessed portions within a column of the plurality of columns are separated by a distance in a range from 100µm to 1000µm.
Kishi discloses wherein the plurality of recessed portions (61, mislabeled as “11” in Figure 5, as numeral 11 refers to a semiconductor chip, and 62, para. [0032]) within a column of the plurality of columns (cross-section shown in Figure 5 shows a row, the columns extend in/out of the page, as recesses 61 and 62 correspond to recess portions 41 and 42 in a previous embodiment in Figures 1 and 2A, 2A showing an array of the recesses that are equidistant, thus the pitch P1 would also be the pitch between recesses in the same column) are separated by a distance (P1) in a range from 100µm to 1000µm (P1 is disclosed as no more than 0.1mm, which is equal to 100 microns which overlaps with the claimed range).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kishi into the teachings of Chaware to include the plurality of recessed portions within a column of the plurality of columns are separated by a distance in a range from 100µm to 1000µm for the purpose of having a small pitch in order to bond together the patterned surface and the die/semiconductor chip (Kishi, para. [0032]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chaware and Lin as applied to claim 15 above, and further in view of Sikka et al. (“Sikka” US 2020/0303279).
Regarding claim 19, the combination of the teachings of Chaware and Lin discloses wherein the TIM layer (140 of Chaware) includes an outer portion over the encapsulation layer (as incorporated by Lin, which laterally surrounds the dies and is coplanar with a top surface of the dies, where the top surface of the dies and encapsulant is where the TIM layer is disposed over, where “over” interpreted to be used as a function word to “indicate motion or situation in a position higher than or above another”, see a Merriam-Webster definition of “over”, which does not necessarily require that the outer portion of the TIM layer is directly above or vertically overlaps with the encapsulation layer) and having a first thickness within the outermost recessed portion (recessed portions 164 of Chaware is shown in Figure 1, where the outermost one would be at the boundary of region 102 shown in Figure 1, thickness within the recessed portion is shown in Figure 1) and a second thickness less than the first thickness outside the outermost recessed portion (164, see close up portion of Figure 1, where the thickness of TIM 140 is greater within the plurality of recesses, including the outermost thereof, because the depth of the recesses effectively “adds” to the thickness of the TIM at the plurality of recesses, see also annotated Figure 1 below).
Chaware does not disclose wherein the TIM layer comprises a phase-change material layer.
However, Sikka discloses in Figure 1 and para. [0037] wherein the TIM layer (115) comprises a phase-change material layer (see para. [0037].
It would have been obvious to incorporate the teachings of Sikka into the teachings of Chaware to include a PCM layer for the TIM for the purpose of enhancing thermal conductance between two surfaces (Sikka, para. [0037]). Further, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Claims 21-22, 25, and 30-34 rejected under 35 U.S.C. 103 as unpatentable over Chaware et al. (“Chaware” US Patent No. 9,418,909), Hoffman et al. (“Hoffman” US 2008/0296757), and Lin et al. (“Lin” US 2019/0067157).
Regarding claim 21, Chaware discloses a method of making a package structure (Figures 1, 2), comprising:
forming a package lid (150) comprising a bottom surface (162) including a recess array (“engineered features” 180) comprising a plurality of recesses (recesses 164);
attaching a package module (114, 112) to a package substrate (122, see Figure 1), wherein the package modules includes a plurality of dies (114, see Figure 1 which shows multiple dies 114);
placing a thermal interface material (TIM) layer (“adhesive” 140, interpreted to be a TIM layer because the adhesive 140 aids in heat dissipation, see col. 4, lines 4-14) on the package module (114, 112, TIM 140 is placed on upper surfaces of dies 114); and
pressing the package lid (150) onto the TIM layer (140) such that at least a portion of the TIM layer (140) moves into the plurality of recesses (164) of the recess array (the TIM is flowed into the recesses, see col. 7, lines 1-2).
In the event that Chaware does not disclose a pressing method, which the examiner does not concede, Hoffman discloses pressing the package lid (10) onto the TIM layer (20) such that such that at least a portion of the TIM layer (20) moves into the plurality of recesses (“channels”, para. [0060]).
It would have been obvious to one having ordinary skill in the art to incorporate the “pressing” teachings of Hoffman into the teachings of Chaware for the purpose of preventing any voids at interfaces of the channels (recesses) and the fluid (Hoffman, para. [0060]).
Chaware and Hoffman do not disclose an encapsulant layer around the plurality of dies, and wherein the pressing of the package lid is performed such that the TIM layer is between the encapsulant layer and an outermost recess of the plurality recesses. The Examiner notes that the combination of Chaware and Hoffman above does disclose a pressing method of the package lid.
However, Lin discloses in Figure 18 a package lid (208/212), an encapsulant layer (108) around the plurality of dies (70A/B), and wherein the TIM layer (122/118) is between the encapsulant layer (108) and an outermost recess of the plurality of recesses (recesses here are considered the recesses of the package lid 208/212 occupied or filled by the thermal/dummy bumps 118, which are considered a part of the TIM, since these are disposed such that they fill the recesses and aid in heat dissipation, see para. [0062], the outermost recess being the leftmost and rightmost recess in Figure 18, if you were to draw a line from the outermost recess to the encapsulant, the line would intersect the TIM layer, thus the TIM layer is therebetween).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lin into the teachings of Chaware to include the encapsulant layer and the configuration thereof for the purpose of covering and protecting the plurality of dies within the package (Lin, para. [0036]).
Regarding claim 22, Chaware discloses wherein the pressing of the package lid (150) onto the TIM layer (140) is performed such that the TIM layer (140) has a first thickness at the plurality of recesses (164) and a second thickness less than the first thickness outside the plurality of recesses (164, see close up portion of Figure 1, where the thickness of TIM 140 is greater at the plurality of recesses because the depth of the recesses effectively “adds” to the thickness of the TIM at the plurality of recesses, see also annotated Figure 1 below).
Regarding claim 25, Chaware discloses wherein the pressing of the package lid (150, pressing incorporated by Hoffman) onto the TIM layer (140) comprises filling the plurality of recesses (164) with the TIM layer (140, the TIM is flowed into the recesses, see col. 7, lines 1-2).
Regarding claim 30, Chaware discloses wherein the forming of the package lid (150) is performed such that the plurality of recesses (164) comprises at least one of a hexagon shape (see Figure 6, recesses 164 have a hexagonal chape in a plan view), a round shape, and oval shape, a capsule shape, a rounded rectangular shape, a square shape, a rectangular shape, a triangular shape, a trapezoid shape and a diamond shape.
Regarding claim 31, Chaware further discloses attaching the package lid (150) to the package substrate (122) concurrently with the pressing of the package lid (150) onto the TIM layer (140, the package lid is placed on the TIM layer 140 which is the same process of attaching the package lid 150 to the package substrate because the lid 150 is attached to the package substrate 122 through the package module 114, 112).
Regarding claim 32, the combination of Chaware and Lin teaches wherein the encapsulation layer (of Lin, incorporated into Chaware around the plurality of dies, see Figure 1) comprises an outermost portion outside the plurality of dies (see Figure 18 of Lin, left and right portions on sidewalls of the dies) and the attaching of the package lid (150) to the package substrate (122) is performed such that the outermost recess of the plurality of recesses (164 at boundary of region 102) is located over the outermost portion of the encapsulation layer (see Figure 18 of Lin in conjunction with Figure 1 of Chaware, the encapsulation layer would be incorporated into the region laterally surrounding the dies of Chaware, the top surface being coplanar with that of the dies, see Figure 18 of Lin which shows the surfaces being coplanar, and the TIM layer and recesses of the lid are placed/disposed at a greater height in the package than the encapsulation layer, thus, the combination would teach the configuration where the outermost recess, which is at the same height as all other recesses 164, is over the outermost portion of the encapsulation layer, where “over” is being interpreted to be used as a function word to “indicate motion or situation in a position higher than or above another”, see a Merriam-Webster definition of “over”, which does not necessarily require that the outermost recess and outermost portion of the encapsulation vertically overlap, with the outermost recess being above the outermost portion of the encapsulation outer portion, only that the outermost recess is at a position higher than the encapsulation outer portion, which the combination teaches).
Regarding claim 33, Chaware does not explicitly disclose wherein the attaching of the package lid to the package substrate is performed such that a distance between an outer sidewall of the package module and the outermost recess is in a range from 0.5 mm to 1.0 mm.
Chaware does disclose requiring engineered features (in this case, recesses 164) are located exclusively in region 102 shown in Figure 1 in order to reduce manufacturing costs (col. 4, lines 37-42), and that the engineered features (in this case, recesses 164) is a predefined structure with a predefined geometry, height, depth, width, and pitch between structures (col. 4, lines 29-36). Thus, Chaware does contemplate that a distance between the outermost recess and the sidewall of the package module would also be predetermined.
However, it would have been obvious to one having ordinary skill in the art under routine optimization and experimentation that a distance between an outer sidewall of the package module and the outermost recess is in a range from 0.5 mm to 1.0 mm because “[t]he normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages” See MPEP 2144.05(II).
Specifically, one having ordinary skill in the art would be motivated to optimize the distance between the outermost recess and the sidewall of the package module under routine experimentation/optimization because this distance can be tailored according to criteria such as, but not limited to, heat dissipation requirements of the device and manufacturing costs. For example, one having ordinary skill in the art would be able to determine, during routine experimentation, what distance between the sidewall of the package and the outermost recess is most suitable according to decreasing manufacturing costs while simultaneously achieving optimal heat dissipation. Thus, it would have been obvious to one having ordinary skill in the art to determine this optimal distance based on these criteria under routine optimization.
Regarding claim 34, Chaware discloses a method of making a package structure (Figures 1, 2), the method comprising:
forming a package lid (150) comprising a bottom surface (162) including a recess array (164) comprising:
a first plurality of recesses (164, left portion of recesses in Figure 1, i.e. portion of recesses directly over the leftmost die 114) having a first configuration (configuration is that the first plurality of recesses is directly over the left die 114); and
a second plurality of recesses (164, right portion of recesses in Figure 1, i.e. portion of recesses directly over the rightmost die 114) having a second configuration (configuration here is that the second plurality of recesses is over the right die 114) different than the first configuration (configurations are different due to different dispositions within the device);
attaching a package module (112, 114) to a package substrate (122, see Figure 1), wherein the package module (112, 114) has a first heat generating region (left die, 114) and a second heat generating region (right die, 114) different than the first heat generating region (the regions are different in their disposition within the device);
placing a thermal interface material (TIM) layer (140) on the package module (112, 114, the TIM layer 140 is disposed on the dies 114); and
pressing the package lid (150) onto the TIM layer (140, lid is secured to the die which would involve a placement and pressing technique, as the TIM 140 is flowed into the recesses, see col. 7, lines 1-2) such that at least a portion of the TIM layer (140) moves into the plurality of recesses (164, see col. 7, lines 1-2) of the recess array, and such that the first plurality of recesses (164, portion over the leftmost die 114) are over the first heat generating region (left die 114, see Figure 1) and the second plurality of recesses (164, portion over the rightmost die 114) are over the second heat generating region (right die 114, see Figure 1).
In the event that Chaware does not disclose a pressing method, which the examiner does not concede, Hoffman discloses pressing the package lid (10) onto the TIM layer (20) such that at least a portion of the TIM layer (20) moves into the plurality of recesses (“channels”) of the recess array (para. [0060]).
It would have been obvious to one having ordinary skill in the art to incorporate the “pressing” teachings of Hoffman into the teachings of Chaware for the purpose of preventing any voids at interfaces of the channels (recesses) and the fluid (Hoffman, para. [0060]).
Chaware and Hoffman do not disclose an encapsulant layer on a side of the package module, wherein the pressing of the package lid is performed such that the TIM layer is between the encapsulant layer and an outermost recess of the plurality of recesses. The Examiner notes that the combination of Chaware and Hoffman above does disclose a pressing method of the package lid.
However, Lin discloses in Figure 18 a package lid (208/212), an encapsulant layer (108) on a side of the package module (70A/B), and wherein the TIM layer (122/118) is between the encapsulant layer (108) and an outermost recess of the plurality of recesses (recesses here are considered the recesses of the package lid 208/212 occupied or filled by the thermal/dummy bumps 118, which are considered a part of the TIM, since these are disposed such that they fill the recesses and aid in heat dissipation, see para. [0062], the outermost recess being the leftmost and rightmost recess in Figure 18, if you were to draw a line from the outermost recess to the encapsulant, the line would intersect the TIM layer, thus the TIM layer is therebetween).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lin into the teachings of Chaware to include the encapsulant layer and the configuration thereof for the purpose of covering and protecting the plurality of dies within the package (Lin, para. [0036]).
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Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Chaware, Hoffman, and Lin as applied to claim 22 above, and further in view of Ho et al. (“Ho” US 2015/0187679).
Regarding claim 23, Chaware does not explicitly disclose wherein the pressing of the package lid onto the TIM layer is performed such that the first thickness is in a range from 50 µm to 1000 µm.
Ho discloses a first thickness (T’) is in a range from 50 µm to 1000 µm (para. [0033] discloses that T’ in Figure 2C is 150 microns which is within the claimed range).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ho into the teachings of Chaware to include a first thickness in a range of 50 µm to 1000 µm for the purpose of reducing thermal resistance (Ho, para. [0033]).
Regarding claim 24, Chaware does not explicitly disclose wherein the pressing of the package lid onto the TIM layer is performed such that a ratio of a depth of the plurality of recesses to the first thickness of the TIM layer is in a range from 0.2 to 0.8.
Ho discloses a ratio of a depth of the plurality of recesses (D1, Figure 2A, para. [0027], range from 0.05 mm to 2.5 mm) to the first thickness of the TIM layer (T’, 150 microns) is in a range from 0.2 to 0.8 (in the same embodiment where T’=150 microns, D1 is equal to 100 microns, see para. [0033], thus D1/T’ is equal to 100 microns /150 microns = ~0.67, which is within the claimed ratio range).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ho into the teachings of Chaware to include a first thickness in a range of 50 µm to 1000 µm for the purpose of reducing thermal resistance (Ho, para. [0033]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Chaware, Hoffman, and Lin as applied to claim 21 above, and further in view of Ho et al. (“Ho” US 2015/0187679) as evidenced by Hoffman.
Regarding claim 26, Chaware does not explicitly disclose wherein the forming of the package lid is performed such that a width of the plurality of recesses of the recess array is in a range from 100µm to 1000µm.
Ho discloses wherein the forming of the package lid (24’, Figure 2A) is performed such that a width (W1) of the plurality of recesses (25) of the recess array is in a range from 100µm to 1000µm (see para. [0027], Ho discloses that the width of the recesses 25 is in a range of 0.1mm, or 100 microns, and 4mm, which encompasses the claimed width range).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ho into the teachings of Chaware to include a width of the plurality of recessed portions to be in a range from 100µm to 1000µm for the purpose of tuning recess width according to the properties of the TIM (Hoffman, para. [0018]).
Claims 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Chaware, Lin, and Hoffman as applied to claim 21 above, and further in view of Kishi et al. (“Kishi” US 2018/0076107).
Regarding claim 27, Chaware discloses wherein the forming of the package lid (150) is performed such that the plurality of recesses (164) have a staggered arrangement including a plurality of columns (staggered array shown in Figure 6, plurality of columns also shown in Figure 6),
Chaware does not disclose wherein the plurality of recesses within a column of the plurality of columns are separated by a distance in a range from 100µm to 1000µm.
Kishi discloses wherein the plurality of recesses (61, 62) within a column of the plurality of columns (row shown in Figure 5 have columns extending in/out of page, as recesses 61 and 62 correspond to recess portions 41 and 42 in a previous embodiment in Figures 1 and 2A, 2A showing an array of the recesses that are equidistant, thus the pitch P1 would also be the pitch between recesses in the same column) are separated by a distance (P1) in a range from 100µm to 1000µm (P1 is disclosed as no more than 0.1mm, which is equal to 100 microns which overlaps with the claimed range).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kishi into the teachings of Chaware to include the plurality of recessed portions within a column of the plurality of columns are separated by a distance in a range from 100µm to 1000µm for the purpose of having a small pitch in order to bond together the patterned surface and the die/semiconductor chip (Kishi, para. [0032]).
Regarding claim 28, Chaware does not disclose wherein the forming of the package lid is performed such that the column of the plurality of columns is separated from an adjacent column of the plurality of columns by a distance in a range from 100µm to 1000µm.
Kishi discloses the column of the plurality of columns (columns of recesses 61, 62 extend in/out of the page of Figure 5) is separated from an adjacent column of the plurality of columns by a distance in a range from 100µm to 1000µm (P1 is disclosed as no more than 0.1mm, which is equal to 100 microns which overlaps with the claimed range).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kishi into the teachings of Chaware to include forming the column of the plurality of columns to be separated from an adjacent column of the plurality of columns by a distance in a range from 100µm to 1000µm for the purpose of having a small pitch in order to bond together the patterned surface and the die/semiconductor chip (Kishi, para. [0032]).
Claims 29 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Chaware, Hoffman, and Lin as applied to claims 21 and 34 above, respectively, and further in view of Karlicek, Jr. (“Karlicek” US Patent No. 10,410,958).
Regarding claim 29, Chaware does not explicitly disclose wherein the forming of the package lid is performed such that a concentration of the plurality of recesses varies over the bottom surface.
Karlicek discloses wherein the forming of the package lid (3) is performed such that a concentration of the plurality of recesses (spaces between pillars 5) varies (see Figure 7C) over the bottom surface (bottom surface of 3 is shown at the upper surface in Figure 7C).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Karlicek into the teachings of Chaware to include a variation of recess density over the bottom surface of the lid for the purpose of optimizing thermal management (Karlicek, col. 6, lines 45-56).
Regarding claim 35, Chaware does not explicitly disclose wherein the second plurality of recesses comprises one of:
a greater depth than a depth of the first plurality of recesses; or a greater concentration than a concentration of the first plurality of recesses.
Karlicek discloses wherein the second plurality of recesses (recesses are spaces between pillars 5, second plurality is the plurality of recesses that are more tightly concentrated in Figure 7C, the first plurality of recesses are the recesses with a lower concentration) comprises one of:
a greater depth than a depth of the first plurality of recesses; or a greater concentration (see Figure 7C and col. 6, lines 45-56) than a concentration of the first plurality of recesses (see Figure 7C).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Karlicek into the teachings of Chaware to include a second plurality of recesses with a greater concentration than the first plurality of recesses for the purpose of optimizing thermal management (Karlicek, col. 6, lines 45-56).
Response to Arguments
Applicant’s amendments regarding the 112(b) rejection of claim 34 overcomes the rejection, thus the 112(b) rejection of claim 34 has been withdrawn.
Applicant’s arguments regarding Lin that Lin does not disclose the amended claim limitations is not persuasive. Lin clearly shows in Figure 18 the TIM layer being between the outermost recess and the encapsulant (see TIM 122/118, encapsulant 108, and leftmost/rightmost recesses in lid 208/212 occupied by portion 118 of the TIM). If one were to draw a straight line from the leftmost/rightmost recess and the encapsulant, the line would intersect with the TIM layer, thus the TIM layer is therebetween. Thus, as demonstrated above, the combination of Chaware and Lin teaches the amended limitations of independent claims 15
Further, regarding claims 19 and 32 above, the Examiner notes that the definition used to interpret the term “over” is from Merriam-Webster which states a definition of “on” as “used as a function word to indicate motion or situation in a position higher than or above another” where a sample use of this definition is “he towered over his mother”. Thus, the term “over” in claims 19 and 32 does not necessarily require that the outermost recess (for claim 32, or outermost portion of the TIM for claim 19) is directly above or vertically overlaps with the outermost portion of the encapsulant (for claim 32, or the encapsulation layer of claim 19), only that the outermost recess (or outer portion of TIM of claim 19) is at a position higher than the outermost portion of the encapsulant (or encapsulation layer of claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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