DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2, with claims 14-33 indicated by Applicant to read thereon, in the reply filed on 4/20/2026 is acknowledged.
While Examiner acknowledges that Applicant indicated that claims 14-20 read on the elected species 2, claims 14-20 (-especially regarding the phrase “depositing an interfacial layer, a ferroelectric layer, and a top electrode layer stacked over the substrate” which implies sequential steps, it means they are deposited one after the other in that sequence) are drawn to non-elected species 9 and are hereby withdrawn from further consideration therefor. Similarly, claims 21-27 also do not read on the elected species (e.g., regarding the phrases “depositing an interfacial layer comprising a semiconductor material and a ferroelectric layer over the underlying wire” and “patterning the bottom electrode layer, the interfacial layer, and the ferroelectric layer, thereby exposing sidewalls of the interfacial layer or the ferroelectric layer that extend to sidewalls of a bottom electrode”) and are hereby withdrawn from further consideration. And claim 30 does not read on the elected species because at least the elected species fails to show that the etch stop layer contacts the top surface and outer sidewalls of the ferroelectric layer.
Claims 14-27 and 30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/20/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 29 and 32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re claim 29, the phrase “…resulting in the etch stop layer having a lower surface spaced from a top surface of the interfacial layer and sidewalls facing the interfacial layer that are spaced from the outer sidewalls of the interfacial layer” is unclear and indefinite. Furthermore, it does not positively recite the active processing step.
Re claim 32, the phrase “wherein after the etch stop layer is formed, the outer sidewalls of the sidewall spacer structures contact the etch stop layer and the underlying etch stop layer” is unclear and indefinite (i.e., which etch stop layer? the one recited in claim 31 and/or 29) and the phrase “the outer sidewalls of the sidewall spacer structures” lacks antecedent basis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 28-29 and 31-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al., US Pub. No. 2022/0367493 A1.
Re claim 28. Lee et al. disclose a method of forming an integrated device, comprising: forming a transistor 202 (e.g. fig. 2, 3A etc.) on a substrate 102; forming an interconnect structure 204/204a/204b/204c (e.g., fig. 2-4B) over the transistor and comprising a bottom electrode wire 204c (e.g., fig. 2) coupled to the transistor; depositing a ferroelectric layer 112 (e.g., figs 1-5, also see paragraph 25) and an interfacial layer 110 (e.g., figs. 1-4, also see paragraph 25) or 502 (e.g., fig. 5) comprising a material (e.g., TaN, paragraph 33) with a bandgap of less than 3 electron volts (e.g., inherent intrinsic property of the material, TaN) over the bottom electrode wire, wherein one of the ferroelectric layer 112 or the interfacial layer 110/502 is electrically coupled to the bottom electrode wire (e.g., figs. 1-5); forming an electrode 108/114 (e.g., figs. 1-5) overlying the bottom electrode wire and electrically coupled to one of the ferroelectric layer 112 or the interfacial layer 110/502; and removing portions of the interfacial layer 110/502 and the ferroelectric layer 112 extending past outer sidewalls of the electrode 108/114 (e.g., figs. 1-5), see figs. 1-33 and pages 1-15 for more details.
Re claim 29. The method of claim 28, further comprising; forming sidewall spacer structures 406 (e.g., an inner vertical portions of 406, fig. 4A) covering the outer sidewalls of the electrode and outer sidewalls of the interfacial layer (fig. 4A); forming an etch stop layer 406 (e.g., an outer vertical portions and the horizontal portions of 406, fig. 4A) over the electrode, resulting in the etch stop layer 406 having a lower surface spaced from a top surface of the interfacial layer 110 and sidewalls facing the interfacial layer 110 that are spaced from the outer sidewalls of the interfacial layer (fig. 4A).
Re claim 31. The method of claim 29, further comprising forming an underlying etch stop layer 310 (e.g., fig. 4A) before depositing the ferroelectric layer, wherein the sidewall spacer structures 406 are deposited on an upper surface of the underlying etch stop layer 310 (e.g., fig. 4A).
Re claim 32. The method of claim 31, wherein after the etch stop layer is formed, the outer sidewalls of the sidewall spacer structures (e.g., an inner vertical portions of 406, fig. 4A) contact the etch stop layer (e.g., an outer vertical portions and the horizontal portions of 406, fig. 4A) and the underlying etch stop layer 310 (e.g., fig. 4A).
Re claim 33. The method of claim 28, wherein forming the electrode further comprises forming a masking layer 402 (e.g., fig. 4A) over an electrode layer then etching the electrode layer to form the electrode 114 (e.g., fig. 4A), and further comprising: forming a sidewall spacer (e.g., an inner vertical portions of 406, fig. 4A) after removing the portions of the interfacial layer and the ferroelectric layer, wherein the sidewall spacer (e.g., an inner vertical portions of 406, fig. 4A) extends from a bottom surface of the interfacial layer to the masking layer (e.g., fig. 4A).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACK S CHEN/Primary Examiner, Art Unit 2893
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