DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 5, 6, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim(US9929013B2) and Tseng (US20230337417A1).
With respect to Claim 1, Kim teaches in FIG 2, FIG 3, FIG 6 and FIG 7 a method for forming a semiconductor structure, comprising:
forming strip patterns (FIG 2; 120; Col 3 Ln 38-39) over a semiconductor substrate (FIG 1; 100; Col 3 Ln 1-2);
forming a patterned mask layer (FIG 2; 127 and 125; Col 3 Ln 24-27) over the strip patterns (FIG 2; 120; Col 3 Ln 38-39), wherein the patterned mask layer (FIG 2; 127 and 125; Col 3 Ln 24-27) includes first openings corresponding to the strip patterns (FIG 2; 120; Col 3 Ln 38-39),
forming spacers (FIG 3; 135; Col 3 Ln 54-56) to partially fill the first openings;
removing the patterned mask layer (FIG 2 and FIG 3; 127; Col 3 Ln 52-53) to form trenches between the spacers (FIG 3; 135; trenches formed between spacers in FIG 3);
forming a conformal layer (FIG 6; 150; Col 4 Ln 43-46) to cover the spacers (FIG 3; 135; Col 3 Ln 54-56) and partially fill the first openings and the trenches; and
etching the strip patterns (FIG 7; 120) using the conformal layer (FIG 7; 150) and the spacers (FIG 7; 135) as a mask, thereby
Kim does not teach the first openings are arranged in an array in a first direction and a second direction that is perpendicular to the first direction, a first pitch of the first openings in the first direction is smaller than a second pitch of the first openings in the second direction, and a first dimension of at least one of the first openings in the first direction is longer than a second dimension of the at least one of the first openings in the second direction;
teach cutting the strip patterns into island patterns.
Tseng teaches in FIG 5-1 the first openings are arranged in an array in a first direction and a second direction that is perpendicular to the first direction (FIG 5-1 with annotations; first direction and second direction), a first pitch (FIG 5-1 with annotations; First pitch) of the first openings in the first direction is smaller than a second pitch (FIG 5-1 with annotations; second pitch) of the first openings in the second direction (FIG 5-1 with annotations; first pitch is smaller than second pitch), and a first dimension (FIG 5-1 with annotations; first dimension) of at least one of the first openings in the first direction is longer than a second dimension (FIG 5-1 with annotations; second dimension) of the at least one of the first openings in the second direction;
cutting the strip patterns into island patterns (FIG 15-1; 210; ¶ [0039]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Kim, a method for fabricating a semiconductor device comprising of forming a strip pattern over a semiconductor substrate, forming a pattern mask over the strip patterns, forming spacers to partially fill the first openings, removing the patterned mask to form trenches between the spacer, forming a conformal layer to cover the spacers and partially fill the first openings and the trenches and etching the strip patterns using the conformal layer and the spacer mask, and the invention of Tseng, a method to form a fabrication device with the pattern mask with features arranged in an array and the etching step with the strip patterns being cut into island patterns. This would produce a semiconductor fabrication method comprising of a patterned mask forming over strip patterns and the strip patterns being cut into island patterns. The island patterns can be transferred into conductive material to make metallic array patterns for a memory cell Tseng (¶ [0012]).
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With respect to Claim 3, Kim and Tseng teach the method for forming the semiconductor structure as claimed in claim 2.
Kim teaches in FIG 3 and FIG 7 wherein forming the spacers comprises:
forming a spacer layer (FIG 3; 135; Col 3 Ln 54-56) over the patterned mask layer (FIG 3; 125; Col 3 Ln 5-7) and partially filling the first openings(FIG 3; 135; Col 3 Ln 54-56) so that the at least two of the first openings connected are separated by the spacer layer; and
removing a portion of the spacer layer (FIG 7; 135; Col 4 Ln 58-60) over an upper surface of the patterned mask layer, wherein a remaining portion of the spacer layer serves as the spacers (FIG 7; 135C; Col 5 Ln 1-4).
With respect to claim 4, Kim and Tseng teach the method for forming the semiconductor structure as claimed in claim 1.
Kim does not teach wherein after forming the conformal layer to partially fill the trenches, remaining portions of the trenches are formed into second openings which are separated from one another.
Tseng teaches in FIG 4 and FIG 5 wherein after forming the conformal layer (FIG 4; 134; ¶ [0018]) to partially fill the trenches (FIG 5 and FIG 5-1; 134; ¶ [0019]; The etching process may also recess portions of the layer (conformal), remaining portions of the trenches are formed into second openings (FIG 5;
204
2
;
134
A
; ¶ [0020]) which are separated from one another (FIG 5;
204
1
;
134
A
; ¶ [0020]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Kim, a method for fabricating a semiconductor device comprising of forming a strip pattern over a semiconductor substrate, forming a pattern mask over the stripe patterns, forming spacers to partially fill the first openings, removing the patterned mask to form trenches between the spacer, forming a conformal layer to cover the spacers and partially fill the first openings and the trenches and etching the strip patterns using the conformal layer and the spacer mask, and the invention of Tseng, a method to form a fabrication device with the pattern mask with features arranged in an array and the conformal layer to partially fill the trenches with the remaining portions of the trenches forming second openings. This combination would produce a method to fabricate a semiconductor device comprising forming a strip pattern over a semiconductor substrate, forming a pattern mask over the strip patterns, forming spacers to partially fill the first openings, removing the patterned mask to form trenches between the spacer, forming a conformal layer to cover the spacers and partially fill the first openings and the remaining portion of the trenches form into second openings which are separate from one another. A strip pattern is used in one region of the device and another pattern is used in the periphery circuitry region of the device Tseng(¶ [0021]). Having different openings and patterns produced on different areas on the device can enhance and tailor design features for desired applications.
With respect to Claim 5, Kim and Tseng teach the method for forming the semiconductor structure as claimed in claim 4.
Kim does not teach wherein the second openings correspond to the strip patterns, and the second openings are arranged in an array in the first direction and the second direction.
Tseng teaches in FIG 5 and FIG 5-1 wherein the second openings correspond to the strip patterns (FIG 5;
204
1
a
n
d
204
2
; ¶ [0021]), and the second openings are arranged in an array in the first direction and the second direction (FIG 5-1 with annotations; first direction and second direction).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Kim, a method for fabricating a semiconductor device comprising of forming a strip pattern over a semiconductor substrate, forming a pattern mask over the strip patterns, forming spacers to partially fill the first openings, removing the patterned mask to form trenches between the spacer, forming a conformal layer to cover the spacers and partially fill the first openings and the trenches and etching the strip patterns using the conformal layer and the spacer mask, and the invention of Tseng, a method to form a fabrication device with the pattern mask with features arranged in an array and the conformal layer to partially fill the trenches with the remaining portions of the trenches forming second openings corresponding to the strip pattern. This combination would produce a method to fabricate a semiconductor device comprising forming a strip pattern over a semiconductor substrate, forming a pattern mask over the strip patterns, forming spacers to partially fill the first openings, removing the patterned mask to form trenches between the spacer, forming a conformal layer to cover the spacers and partially fill the first openings and the remaining portion of the trenches form into second openings which are separate from one another and correspond to the strip patterns. One strip pattern is used in one region of the device and another is used in the periphery circuitry region of the device Tseng(¶ [0021]) and the array of patterns allows for a structure shape to cover a large area of a surface to enhance device functionality.
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With respect to Claim 6, Kim and Tseng teach the method for forming the semiconductor structure as claimed in claim 4.
Kim does not teach wherein a third pitch of the second openings in the first direction is smaller than a fourth pitch of the second openings in the second direction, and a third dimension of at least one of the second openings in the first direction is longer than a fourth dimension of the at least one of the second openings in the second direction.
Tseng teaches in FIG 5-1 wherein a third pitch of the second openings (FIG 5-1 with annotations; third pitch) in the first direction is smaller than a fourth pitch of the second openings (FIG 5-1 with annotations; fourth pitch)in the second direction, and a third dimension of at least one of the second openings (FIG 5-1 with annotations; third dimension) in the first direction is longer than a fourth dimension of the at least one of the second openings (FIG 5-1 with annotations; fourth dimension) in the second direction.
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Kim, a method for fabricating a semiconductor device comprising of forming a strip pattern over a semiconductor substrate, forming a pattern mask over the strip patterns, forming spacers to partially fill the first openings, removing the patterned mask to form trenches between the spacer, forming a conformal layer to cover the spacers and partially fill the first openings and the trenches and etching the strip patterns using the conformal layer and the spacer mask, and the invention of Tseng, a method to form a fabrication device with the pattern mask with features arranged in an array and the conformal layer to partially fill the trenches with the remaining portions of the trenches forming second openings and have a third pitch, a fourth pitch, a third dimension and a fourth dimension. This combination would produce a method to fabricate a semiconductor device comprising forming a strip pattern over a semiconductor substrate, forming a pattern mask over the strip patterns, forming spacers to partially fill the first openings, removing the patterned mask to form trenches between the spacer, forming a conformal layer to cover the spacers and partially fill the first openings and the remaining portion of the trenches form into second openings which are separate from one another and have a third pitch, a fourth pitch, a third dimension and a fourth dimension . The length of the second openings determine the shape of the imprint of the feature on the substrate surface Tseng(¶ [0017]) affecting the functionality of the semiconductor device.
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With respect to Claim 9, Kim and Tseng teach the method for forming the semiconductor structure as claimed in claim 1.
Kim does not teach wherein the strip patterns have a third pitch in the first direction and a fourth pitch in the second direction, the third pitch is substantially the same as the first pitch, and the fourth pitch is smaller than the second pitch.
Tseng teaches in FIG 2 wherein the strip patterns have a third pitch (FIG 2 with annotations; third pitch) in the first direction and a fourth pitch (FIG 2 with annotations; fourth pitch) in the second direction, the third pitch is substantially the same as the first pitch (FIG 2 with annotations; third pitch and first pitch are the same), and the fourth pitch is smaller than the second pitch (FIG 2 with annotations; fourth pitch is smaller than second pitch).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Kim, a method for fabricating a semiconductor device comprising of forming a strip pattern over a semiconductor substrate, forming a pattern mask over the strip patterns, forming spacers to partially fill the first openings, removing the patterned mask to form trenches between the spacer, forming a conformal layer to cover the spacers and partially fill the first openings and the trenches and etching the strip patterns using the conformal layer and the spacer mask, and the invention of Tseng, a method to form a fabrication device with a pattern mask with features arranged in an array and pitches of a variety of lengths and the etching step with the strip patterns being cut into island patterns . This would produce a semiconductor fabrication method comprising of a patterned mask forming over strip patterns and strip patterns with pitches of a variety of lengths. The strip patterns are the core pattern of the memory cell, effecting the structure and functionality of the semiconductor device Tseng ¶[0017] so the features in the array are influences by the pith of the strip patterns.
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With respect to claim 10, Kim and Tseng teach the method for forming the semiconductor structure as claimed in claim 1.
Kim does not teach further comprising:
performing an etching process on the semiconductor substrate using the island patterns to form active regions.
Tseng teaches further comprising:
performing an etching process (FIG 17; 210 and 112A hard mask; ¶ [0013]) on the semiconductor substrate (FIG 17; 100 and 102; ¶ [0008]) using the island patterns (FIG 17; 210; ¶ [0012]) to form active regions (¶ [0010]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Kim, a method for fabricating a semiconductor device comprising of forming a strip pattern over a semiconductor substrate, forming a pattern mask over the strip patterns, forming spacers to partially fill the first openings, removing the patterned mask to form trenches between the spacer, forming a conformal layer to cover the spacers and partially fill the first openings and the trenches and etching the strip patterns using the conformal layer and the spacer mask, and the invention of Tseng, a method to form a fabrication device with the pattern mask with features arranged in an array and the etching step with the strip patterns being cut into island patterns and an etching process being performed on the semiconductor substrate using the island patterns to form active regions. This would produce a semiconductor fabrication method comprising of a patterned mask forming over strip patterns and the strip patterns being cut into island patterns and etching process performed to form active regions. The memory cell array includes active regions conductive pads, wires and contact plugs Tseng (FIG 17; ¶ [0010]) to store data.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim(US9929013B2) and Tseng (US20230337417A1) as applied to claim 1, 3, 4, 5, 6, 9 and 10 above, and further in view of Kau(US20220328304A1).
With respect to Claim 2, The method for forming the semiconductor structure as claimed in claim 1, further comprising:
Kim and Tseng does not teach performing a trimming process on the patterned mask layer to enlarge the first openings so that at least two of the first openings arranged in the first direction are connected to each other.
Kao teaches in FIG 5B and FIG 6B performing a trimming process (FIG 5B and FIG 6B; 220b; ¶ [0044]) on the patterned mask (340; ¶ [0041]) layer to enlarge the first openings so that at least two of the first openings arranged in the first direction are connected to each other (FIG 5B and FIG 6B; 220b connects the bottom and top of 210; ¶ [0044]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Kim and Tseng, a method to form a fabrication device with the pattern mask and the invention of Kao, performing a trimming process a patterned mask layer to connect two openings This would produce a semiconductor fabrication method comprising of a patterned mask forming over strip patterns and performing a trimming process connect two openings. The trimming process can reduce the size or imprints on the surface to fabricate transistor Kao[0026].
With respect to Claim 7, Kim and Tseng teach the method for forming the semiconductor structure as claimed in claim 1.
Kim and Tseng do not teach wherein forming the patterned mask layer comprises:
performing a lithography process using a photomask, wherein the photomask has patterns which are arranged in an array in the first direction and the second direction, and at least one of the patterns includes a body portion and an extending portion protruding from a side of the body portion.
Kao teach in Fig 2 wherein forming the patterned mask layer comprises:
performing a lithography process using a photomask (FIG 2; 262; ¶ [0024]), wherein the photomask has patterns which are arranged in an array in the first direction (FIG 2 with annotations; first direction) and the second direction (FIG 2 with annotations; second direction), and at least one of the patterns includes a body portion (Fig 2 with Annotation; Body portion) and an extending portion (FIG 2 with Annotation; Extending portion) protruding from a side of the body portion.
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Kim and Tseng, a method to form a fabrication device with the pattern mask and the invention of Kao, performing a lithography process using a photomask with an array and with features including a body portion and an extending portion. This produces a semiconductor fabrication method comprising of a patterned mask forming over strip patterns and performing a lithography process using a photomask with an array and with features including a body portion and an extending portion. The photomask having light reflecting or transmissive regions allows for imprinting features on the photoresist layer Kau¶ [0024].
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With respect to Claim 8, Kim and Tseng teach the method for forming the semiconductor structure as claimed in claim 7.
Kim and Tseng do not teach wherein the extending portion of one of the patterns is connected to the extending portion of another one of the patterns.
Kao teaches wherein the extending portion of one of the patterns is connected to the extending portion of another one of the patterns (Fig 2 with annotations; extending portion).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Kim and Tseng, a method to form a fabrication device with the pattern mask and the invention of Kao, performing a lithography process using a photomask with an array and with features including a body portion and the extending portion of a pattern connecting to the extending portion of another pattern. This produces a semiconductor fabrication method comprising of a patterned mask forming over strip patterns and performing a lithography process using a photomask with an array and with features including a body portion and the extending portion of a pattern connecting to the extending portion of another pattern. The photomask having particular features allows for the features to be imprinted on the photoresist layer Kau¶ [0024] to fabricate the desires structure for the semiconductor device.
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Claim 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng(US20230337417A1) and Kau(US20220328304A1).
With respect to Claim 11, Tseng teaches in FIG 2, FIG 4, FIG 8 and FIG 5 a method for forming a semiconductor structure, comprising:
forming first strip patterns over a semiconductor substrate (FIG 2; 202; ¶ [0018]);
forming a hard mask layer over the first strip patterns (FIG 2; 128, 122, 120, 118, 116; ¶ [0015]);
forming a photoresist material over the hard mask layer (FIG 2; 130; ¶ [0016]);
patterning the photoresist material (FIG 2; 130; ¶ [0016]) using a photomask so that patterns of the photomask are transferred (FIG 2; 130; first lithography process; photomasks are used as templated to pattern photoresist during photolithography) into the photoresist material to form a patterned photoresist material (FIG 2; 130A; ¶ [0016]), and the patterned photoresist material has first openings corresponding to the first strip patterns (FIG 2-130A and FIG 3-202; corresponding positions on substrate surface);
forming spacers along sidewalls of the first openings (FIG 4; 132; ¶ [0018]);
removing the patterned photoresist material (FIG 3; 130; ¶ [0017]);
forming a conformal layer (FIG 4; 134; ¶ [0018]) over the hard mask layer (FIG 2; 128, 126, 124, 122, 120, 118, 116; ¶ [0015]) and along the spacers (FIG 4; 132; ¶ [0018]); and
sequentially etching the hard mask layer (FIG 2; 128, 122, 120, 118, 116; ¶ [0019]), the first strip patterns and the semiconductor substrate (FIG 8; 114; ¶ [0015]; 114 layer made of semiconductor material and pattern etched into surface, as seen in Fig 8) using the conformal layer (FIG 4 and FIG 5; 134; ¶ [0018]) and the spacers as a mask (FIG 4 and FIG 5; 132 and 134; ¶ [0018]).
Tseng does not teach wherein at least one of the patterns of the photomask includes a body portion and an extending portion protruding from a side of the body portion.
Kau teaches in FIG 2 wherein at least one of the patterns of the photomask (FIG 2; 262; ¶ [0024]) includes a body portion (Fig 2 Annotation; Body portion) and an extending portion (FIG 2 Annotation; Extending portion) protruding from a side of the body portion.
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Tseng, a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography and the invention of Kau, using a photomask with features comprised of a body and an extending portion. This combination produces a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography while using a photomask with features comprised of a body and an extending portion. In the case of a transistor or the like, the extending portion feature may be intended to be fabricated to form a polymer gate of the transistor, where wCD2 corresponds to the channel length Kau¶ [0026].
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With respect to Claim 12, Tseng and Kau teach the method for forming the semiconductor structure as claimed in claim 11.
Tseng does not teach wherein a dimension of the extending portions is smaller than an optical proximity correction limit of a lithography process for patterning the photoresist material.
Kau teaches in FIG 2 wherein a dimension of the extending portions is smaller than an optical proximity correction limit of a lithography process for patterning the photoresist material (FIG 2;
W
C
D
2
;
¶ [0027]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Tseng, a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography and the invention of Kau, using a photomask with features comprised of a body and an extending portion wherein a dimension of the extending portion is smaller than an optical proximity correction limit. This combination produces a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography while using a photomask with features comprised of a body and an extending portion wherein a dimension of the extending portion is smaller than an optical proximity correction limit. This extending portion region may be susceptible to damage or delamination, for example by way of photoresist peeling and use a two-mask exposure to trim the feature smaller Kau¶ [0027] is needed to make a more accurate shape.
With respect to Claim 13, Tseng and Kau teach the method for forming the semiconductor structure as claimed in claim 11.
Tseng does not teach wherein the patterns of the photomask are arranged in an array in a first direction and a second direction perpendicular to the first direction, and a first dimension of the body portion in the first direction is smaller than a second dimension of the body portion in the second direction.
Kau teaches in FIG 2 wherein the patterns of the photomask are arranged in an array in a first direction and a second direction perpendicular to the first direction (Fig 2; 262; array (8x1) displayed), and a first dimension of the body portion in the first direction is smaller than a second dimension of the body portion in the second direction (Fig 2 with annotations; Mask 262; see arrows in body 4).
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It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Tseng, a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography and the invention of Kau, using a photomask with features comprised of a body with a smaller portion in the first dimension than the second dimension and an extending portion arranged in an array in a first direction and a second direction perpendicular to the first direction. This combination produces a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography while using a photomask with features comprised of a body with a smaller portion in the first dimension than the second dimension and an extending portion arranged in an array in a first direction and a second direction perpendicular to the first direction. The photomask having light reflecting or transmissive regions allows for imprinting features on the photoresist layer Kau¶ [0024].
With respect to Claim 14, The method for forming the semiconductor structure as claimed in claim 13.
Tseng does not teach wherein a first pitch of the patterns of the photomask in the first direction is shorter than a second pitch of the patterns of the photomask in the second direction.
Kau teaches in FIG 2 wherein a first pitch (FIG 2 with annotations; first pitch) of the patterns of the photomask in the first direction is shorter than a second pitch (FIG 2 with annotations; second pitch) of the patterns of the photomask in the second direction.
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Tseng, a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography and the invention of Kau, using a photomask with features comprised of a body with a smaller portion in the first dimension than the second dimension and an extending portion arranged in an array in a first direction and a second direction perpendicular to the first direction with the first pitch being smaller than the second pitch. This combination produces a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography while using a photomask with features comprised of a body with a smaller portion in the first dimension than the second dimension and an extending portion arranged in an array in a first direction and a second direction perpendicular to the first direction with the first pitch being smaller than the second pitch. The pitch resolution has to be sufficient to properly imprint the image on the photoresist Kau ¶ [0027].
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With respect to Claim 15, Tseng and Kao teach the method for forming the semiconductor structure as claimed in claim 11.
Tseng does not teach wherein the at least one of the first openings of the patterned photoresist material has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is longer than the fourth dimension.
Kao teaches in FIG 2 wherein the at least one of the first openings of the patterned photoresist material has a third dimension (FIG 2 with annotations; Third dimension) in the first direction and a fourth dimension (FIG 2 with annotations; Fourth dimension) in the second direction, and the third dimension is longer than the fourth dimension (FIG 2 with annotations; Third dimension is longer than fourth dimension).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Tseng, a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography and the invention of Kau, using a photomask with features comprised of a body and an extending portion. This combination produces a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography while using a photomask with features comprised of a body and an extending portion with a third dimension in the first direction and a fourth dimension in the second direction. The multiple features dimensions are similar to one and taken along the same direction Kau ¶ [0018] to create a uniform array on the wafer surface.
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With respect to Claim 16, Tseng and Kao teaches The method for forming the semiconductor structure as claimed in claim 11.
Tseng teaches in FIG 5-1 wherein the first strip patterns (FIG 5-1; 204; ¶ [0021]) extend in a third direction (FIG 5-1 with annotations; third direction) that is parallel to neither the first direction (FIG 5-1 with annotations; first direction) nor the second direction (FIG 5-1 with annotations; second direction).
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With respect to Claim 17, Tseng and Kao teach the method for forming the semiconductor structure as claimed in claim 11.
Tseng does not teach further comprising:
performing a trimming process on the patterned photoresist material so that the patterned photoresist material has second strip patterns that are separated from one another.
Kao teaches in FIG 2 and FIG 3 further comprising:
performing a trimming process (FIG 3; 340; ¶ [0043]) on the patterned photoresist material so that the patterned photoresist material (FIG 2; 210; ¶ [0043]) has second strip patterns that are separated from one another (FIG 3; 340; ¶ [0043]; remove remaining portions of photoresist layer).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Tseng, a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography and the invention of Kau, using a photomask with features comprised of a body and an extending portion and performing a trimming process on the photoresist to produce a second strip pattern. This combination produces a method to form a semiconductor memory structure by forming strip patterns over a semiconductor substrate using photolithography while using a photomask with features comprised of a body and an extending portion wherein a dimension of the extending portion and performing a trimming process on the photoresist to produce a second strip pattern. In some suitable embodiments, a separate etching step (not shown) subsequent to the second/trim etching step may be applied to the semiconductor structure or wafer in order to remove those portions of the photoresist layer which remained after the first etching step Kau ¶ [0043] and this can be used to make more precise feature morphologies and complex structures to enhance the performance of the semiconductor device.
With respect to Claim 18, Tseng and Kao teaches the method for forming the semiconductor structure as claimed in claim 11.
Tseng teaches in FIG 2 wherein the patterned photoresist material (FIG 2; 130; ¶ [0016]) is removed to form trenches that are separated from one another (FIG 3; The patterned photoresist layer 130 and the hard mask layer 128 may be entirely consumed in the etching process, or removed by an additional process such as an etching or ashing process; ¶ [0017]; trenches are formed in FIG 3).
With respect to Claim 19, Tseng and Kao teaches the method for forming the semiconductor structure as claimed in claim 18.
Tseng teaches in FIG 4 and FIG 5 wherein the conformal layer (FIG 4; 134; ¶ [0018]) is formed to partially fill the trenches (FIG 5 and FIG 5-1; 134; ¶ [0019]; The etching process may also recess portions of the layer (conformal) so that remaining portions of the trenches are formed into second openings (FIG 5;
204
2
;
134
A
; ¶ [0020]), and the second openings are separated from one another and correspond to the first strip patterns (FIG 5;
204
1
a
n
d
204
2
; ¶ [0021]).
With respect to Claim 20, Tseng and Kao teach the method for forming the semiconductor structure as claimed in claim 19.
Tseng teaches in FIG 5 wherein after forming the conformal layer, at least one of the first openings has a first dimension in a direction (FIG 5 with annotations; First dimension), at least one of the second openings has a second dimension (FIG 5 with annotations; Second dimension) in the direction, the second dimension is the same as the first dimension (FIG 5 with annotations; First dimension and second dimension lengths are the same) and the at least one of the first openings has a different outline than the at least one of the second openings (FIG 5 with annotations; Outline of first opening and outline of second opening).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant disclosure:
Sukegawa(US8541316B2): A technique to form compact holes on the surface of a semiconductor device
Lee(US20120156841A1): A method to form a semiconductor device made of stacked thin films
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BASEEMAH QADEER RUCKER whose telephone number is (571)272-0380. The examiner can normally be reached Monday-Friday 7:30-5:00.
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/B.Q.R./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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