Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 02/02/2026 has been accepted and entered.
Response to Arguments
Applicant’s amendment to independent claim 17, and its respective dependent claims and corresponding arguments, see pages 9-10 of Applicant’s remarks filed 02/02/2026, with respect to the 35 U.S.C. 103 rejection of claim 1 has been fully considered and is persuasive. Takahashi in view of Tojinbara does not teach all of the limitations of amended claim 1 (i.e. “forming an implant isolation region under the floating diffusion region in the opening in the trench isolation layer, the implant isolation region and the floating diffusion region extending along a first sidewall and a second sidewall of the trench isolation layer from the first photodetector to the second photodetector”) and thus and its respective dependent claims.
In view of the amendment, new references have been applied (see below). Claim 17 now stands rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0371838 A1 Takahashi et al in view of US 2022/0392942 A1 Tojinbara and further in view of US 2023/0207595 A1 Um et al.
Applicant’s amendment to independent claim 32, and its respective dependent claims and corresponding arguments, see pages 11-12 of Applicant’s remarks filed 02/02/2026, with respect to the 35 U.S.C. 103 rejection of claim 23 has been fully considered and is persuasive. Takahashi in view of Tojinbara does not teach all of the limitations of amended claim 23 (i.e. “forming an implant isolation region in the first semiconductor substrate along a second side of the first semiconductor substrate, and wherein the implant isolation region is in the gap in the trench isolation layer and extends between the first and second sidewalls of the trench isolation layer from the second side of the first semiconductor substrate to a bottom of the shared floating diffusion region.”) and thus and its respective dependent claims.
In view of the amendment, new references have been applied (see below). Claim 32 now stands rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0371838 A1 Takahashi et al in view of US 2020/0135617 A1 Shen et al and further in view of US 2023/0207595 A1 Um et al.
Status of Claims
Claims 17-36 pending.
Claims 1-16 cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0371838 A1 Takahashi et al (herein “Takahashi”) in view of US 2022/0392942 A1 Tojinbara (herein “Tojinbara”) and further in view of US 2023/0207595 A1 Um et al (herein “Um”).
Regarding Claim 17, Takahashi discloses:
A method for forming an integrated chip (see processing steps shown in Figs. 4-10, and flowchart shown in Fig. 11), the method comprising:
forming a first photodetector (herein #1P, see annotated Fig. 10 below) and a second photodetector (herein #2P, see annotated Fig. 10 below) in a first semiconductor substrate (#104) along a first side (top side with respect to page) of the first semiconductor substrate (#104);
forming a first transfer gate (herein #1G, first gate corresponds to #224 of first photodetector) and a second transfer gate (herein #2G, second gate corresponds to #224 of second photodetector) over the first photodetector (#1P) and the second photodetector (#2P), respectively;
forming a floating diffusion region (#118) in the first semiconductor substrate (#104) between the first photodetector (#1D) and the second photodetector (#2D);
forming a first metal interconnect (herein #1I, first interconnect corresponds to #256 of first photodetector and first transfer gate) over and coupled to the first transfer gate (#1G), a second metal interconnect (herein #2I, second interconnect corresponds to #256 of second photodetector and second transfer gate) over and coupled to the second transfer gate (#2G), and a third metal interconnect (herein #3I, third interconnect corresponds to #256 coupled to diffusion region #118) over and coupled to the floating diffusion region (#118);
forming a trench isolation layer (#258) surrounding the first photodetector (#1D) and the second photodetector (#2D) and extending between the first photodetector (#1D) and the second photodetector (#2D), the trench isolation layer (#258) having an opening (see annotated Fig. 10 below, also see paragraph [0036]: “In some embodiments, one of the BSI structures 258 may extend in the second direction over both the floating diffusion node 118 and the pick-up well contact region 120.” The trench isolation structure may extend over the FD region and the contact region, therefore would have an opening that the FD region and the contact region would be within) therein between the first photodetector (#1D) and the second photodetector (#2D), the first semiconductor substrate (#104) extending through the opening (see Fig. 10B) from the first photodetector (#1D) to the second photodetector (#2D);
Takahashi does not explicitly disclose:
forming a first pixel transistor along a first side of a second semiconductor substrate;
forming a fourth metal interconnect over and coupled to the first pixel transistor; and
bonding the second semiconductor substrate over the first side of the first semiconductor substrate so the third metal interconnect is coupled to the fourth metal interconnect.
forming an implant isolation region under the floating diffusion region in the opening in the trench isolation layer, the implant isolation region and the floating diffusion region extending along a first sidewall and a second sidewall of the trench isolation layer from the first photodetector to the second photodetector;
However, in analogous art, Tojinbara teaches:
See Fig. 17. For convenience, 1st-3rd interconnects are shown/labelled in annotated Tojinbara Fig. 17 below. These correspond to 1st-3rd interconnects in annotated Takahashi Fig. 10.
forming a first pixel transistor (#AMP) along a first side (bottom side with respect to Tojinbara Fig. 17) of a second semiconductor substrate (#200);
forming a fourth metal interconnect (herein #4I, see annotated Fig. 17 below) over and coupled to the first pixel transistor (#AMP); and
bonding the second semiconductor substrate (#200) over the first side (bottom side) of the first semiconductor substrate (#100) so the third metal interconnect (#3I, see annotated Fig. 17 below) is coupled to the fourth metal interconnect (#4I).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Tojinbara to the device/method disclosed by Takahashi and include a second substrate bonded to the first substrate that contains a fourth interconnect which electrically connects the pixel transistor to the diffusion region. Takahashi is silent on how the photodetector device is electrically connected to a larger device, which a person of ordinary skill would then seek out the teachings of Tojinbara. Additionally, by including the electrical connection between the diffusion region and the pixel transistor, the pixel transistor may output a pixel signal of a voltage corresponding to the level of electric charge generated in the photodiode PD, which would be necessary for a functional device. See paragraphs [0048]-[0049] in Tojinbara.
Additionally, in analogous art, Um teaches:
See generally Fig.4 and 5A-5C.
forming an implant isolation region (Fig. 5a, #PIS, includes elements #111, #113, and #115, specifically p-type doped liner (barrier dopant region) #115, [0084]) under the floating diffusion region (#FDa-FDd) in the opening in the trench isolation layer (Fig. 4, #P2b), the implant isolation region (Fig. 4, #P2b) and the floating diffusion region (#FDa-FDd) extending along a first sidewall (see left or right sidewalls in annotated Fig. 4 below) and a second sidewall (see left or right sidewalls in annotated Fig. 4 below) of the trench isolation layer (#P2a) from the first photodetector to the second photodetector;
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider including the isolation structure including barrier dopant region #115 in Um. Including the barrier dopant region may reduce a dark current caused by electron-hole pairs (EHPs) generated by surface defects of a pixel isolation trench formed in the semiconductor substrate 100, see [0084] and [0104].
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Takahashi Fig. 10 – Annotated by Examiner
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Tojinbara Fig. 17 – Annotated by Examiner
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Um Fig. 4 – Annotated by Examiner
Regarding Claim 18, Takahashi in view of Tojinbara and further in view of Um discloses: the method of claim 17.
Takahashi further teaches:
wherein the floating diffusion region (#118) is in the opening (see annotated Fig. 10 above) in the trench isolation layer (#258).
Regarding Claim 19, Takahashi in view of Tojinbara and further in view of Um discloses: the method of claim 17.
Takahashi further teaches:
See Fig. 9. See paragraph [0061].
wherein forming the trench isolation layer (#258) comprises etching a second side (top side with respect to Fig. 9B) of the first semiconductor substrate (#104), opposite the first side (bottom side with respect to Fig. 9B), to form a trench (not shown, see [0061]) in the first semiconductor substrate (#104), and depositing the trench isolation layer (#258) in the trench.
Regarding Claim 20, Takahashi in view of Tojinbara and further in view of Um discloses: the method of claim 17.
Takahashi further teaches:
further comprising:
forming a color filter (#262) and a micro-lens (#264) directly over the first photodetector (#1D) and the second photodetector (#2D);
Takahashi in view of Tojinbara does not explicitly disclose:
bonding a third semiconductor substrate over a second side of the second semiconductor substrate, opposite the first side of the second semiconductor substrate.
However, in analogous art, Tojinbara further teaches:
bonding a third semiconductor substrate (#300) over a second side (bottom side with respect to Fig. 17) of the second semiconductor substrate (#200), opposite the first side (top side with respect to Fig. 17) of the second semiconductor substrate (#200).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Tojinbara to the device/method disclosed by Takahashi in view of Tojinbara and include a third semiconductor substrate bonded to the second semiconductor substrate. Doing so would provide the additional semiconductor material layers and wiring layers in order for the completed device to function, that Takahashi is silent on the formation of. Specifically, additional elements like the logic circuit and booster circuit would be formed in the third semiconductor substrate for completed device operation, see Tojinbara paragraph [0091].
Claim 32-33 and 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0371838 A1 Takahashi et al in view of US 2020/0135617 A1 Shen et al (herein “Shen”) and further in view of US 2023/0207595 A1 Um et al.
Regarding Claim 32, Takahashi discloses:
See annotated Fig. 10 above.
A method of forming an integrated chip (see processing steps shown in Figs. 4-10, and flowchart shown in Fig. 11), the method comprising:
forming a shared floating diffusion region (#118) in a first semiconductor substrate (#104) along a first side of the first semiconductor substrate;
forming a first photodetector (#1D) and a second photodetector (#2D) in the first semiconductor substrate (#104), wherein the shared floating diffusion region (#118) is between the first photodetector (#1D) and the second photodetector (#2D); and
forming a trench isolation layer (#258) around the first photodetector (#1D), around the second photodetector (#2D), and between the first photodetector (#1D) and the second photodetector (#2D),
Takahashi does not explicitly disclose:
forming an implant isolation region in the first semiconductor substrate along a second side of the first semiconductor substrate;
wherein the first semiconductor substrate extends laterally from the first photodetector to the second photodetector through a gap in the trench isolation layer that is delimited by a first sidewall and a second sidewall of the trench isolation layer, and wherein the shared floating diffusion region is in the gap in the trench isolation layer and between the first and second sidewalls of the trench isolation layer.
However, in analogous art, Shen teaches:
See Figs. 12. See also paragraph [0056], specifically “Back-side isolation structures 330, 332 are disposed over and between the photodetectors 350a, 350b.” Under this description, and based on the plan view shown in Fig. 12, the FD region #342 shown sits in a cutout region of the backside isolation structure, with the claimed sidewalls lying on the front and back surfaces with respect to the page of the FD region.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Shen to the device/method disclosed by Takahashi and form the backside dielectric trench such that it fully extends to the top surface of the neighboring photodetectors like shown in Shen Fig. 12. Doing so would electrically isolate the neighboring photodetectors with the exception of the substrate material directly below the floating diffusion region, and the floating diffusion region. Additionally, paragraph [0061] of Takahashi states the semiconductor substrate may be etched using a mask in order to selectively remove material; therefore, this combination would result in the claimed limitation of the floating diffusion region and the semiconductor substrate being limited by the sidewalls of the backside isolation structure.
Additionally, in analogous art, Um discloses:
See generally Fig.4 and 5A-5C.
forming an implant isolation region (Fig. 5a, #PIS, includes elements #111, #113, and #115, specifically p-type doped liner (barrier dopant region) #115, [0084]) in the first semiconductor substrate between the first photodetector and the second photodetector;
and wherein the implant isolation region (Fig. 5a, isolation region includes #PIS, #103, #105, specifically see p-type doped liner (barrier dopant region) #115, [0084]) is in the gap in the trench isolation layer and extends between the first and second sidewalls of the trench isolation layer (see top-down view in Fig. 4) from the second side of the first semiconductor substrate (Fig. 5a, #100b) to a bottom of the shared floating diffusion region (##FDa-d).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider including the isolation structure including barrier dopant region #115 in Um. Including the barrier dopant region may reduce a dark current caused by electron-hole pairs (EHPs) generated by surface defects of a pixel isolation trench formed in the semiconductor substrate 100, see [0084] and [0104].
Regarding Claim 33, Takahashi in view of Shen and further in view of Um discloses: the method of claim 32.
Takahashi further discloses:
further comprising:
forming a first transfer gate (#226, first gate corresponds to #224 of first photodetector) over the first photodetector (#1D) and a second transfer gate (#226, second gate corresponds to #224 of second photodetector) over the second photodetector (#2D), wherein the first photodetector (#1D), the shared floating diffusion region (#118), and the first transfer gate (#226) partially form a first transfer transistor (#224, first transistor corresponds to first photodetector), and wherein the second photodetector (#2D), the shared floating diffusion region (#118), and the second transfer gate (#226, second gate corresponds to #224 of second photodetector) partially form a second transfer transistor (#224, second gate corresponds to second photodetector).
Regarding Claim 37, Takahashi in view of Shen and further in view of Um discloses: the method of claim 32.
Takahashi further discloses:
wherein the implant isolation region has a first doping type (p-type, feature combined from Um, see Um [0084], see above), and wherein the shared floating diffusion region has a second doping type (n-type, see Takahashi [0020]) different than the first doping type.
Regarding Claim 38, Takahashi in view of Shen and further in view of Um discloses: The method of claim 32,
Um further discloses:
wherein a sidewall of the trench isolation layer (#P2b) extends along a side of the shared floating diffusion region (see top-down view in Fig. 4) and a side of the implant isolation region (#115) from the second side of the first semiconductor substrate (#100b) to the first side of the first semiconductor substrate (#100a).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Um to the device disclosed by Takahashi in view of Shen and further in view of Um and include the isolation structure as taught by Um that extends from the bottom surface of the substrate to the top surface of the substrate in order to isolate adjacent photodetector structures. Doing so would be a simple substitution of parts for the purposes of electrical isolation of one known isolation structure for another. Accordingly, the surrounding trench isolation layer #P2b as seen from a top down view in Fig. 4 would contact the side surfaces of the isolation pillar that includes the doped region and the floating diffusion region, which therefore reads on the claim as presented.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0371838 A1 Takahashi et al in view of US 2020/0135617 A1 Shen et al and further in view of US 2023/0207595 A1 Um et al and further in view of US 2022/0392942 A1 Tojinbara.
Regarding Claim 34, Takahashi in view of Shen and further in view of Um discloses: the method of claim 33.
Takahashi further discloses:
forming a first metal interconnect (see annotated Fig. 10 above, currently referenced as third interconnect due to the other independent claims, for consistency through this document the same element number will be assigned, thus herein #3I) coupled to the shared floating diffusion region (#118);
Takahashi in view of Shen and further in view of Um does not explicitly disclose:
forming a first pixel transistor along a second semiconductor substrate;
forming a second metal interconnect coupled to the first pixel transistor; and
bonding the second semiconductor substrate and the first semiconductor substrate so that the first pixel transistor is coupled to the shared floating diffusion region by the first metal interconnect and the second metal interconnect.
However, in analogous art, Tojinbara teaches:
See Fig. 17. For convenience, 1st-3rd interconnects are shown/labelled in annotated Tojinbara Fig. 17 below. These correspond to 1st-3rd interconnects in annotated Takahashi Fig. 10.
forming a first pixel transistor (#AMP) along a second semiconductor substrate (#200);
forming a second metal interconnect (see annotated Fig. 10 above, currently referenced as fourth interconnect due to the other independent claims, for consistency through this document the same element number will be assigned, thus herein #4I) coupled to the first pixel transistor (#AMP); and
bonding the second semiconductor substrate (#200) and the first semiconductor substrate (#100) so that the first pixel transistor (#AMP) is coupled to the shared floating diffusion region (#FD) by the first metal interconnect (#3I) and the second metal interconnect (#4I).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Tojinbara to the device/method disclosed by Takahashi in view of Shen and further in view of Um and include a second substrate bonded to the first substrate that contains a fourth interconnect which electrically connects the pixel transistor to the diffusion region. Takahashi in view of Shen and further in view of Um is silent on how the photodetector device is electrically connected to a larger device, which a person of ordinary skill would then seek out the teachings of Tojinbara. Additionally, by including the electrical connection between the diffusion region and the pixel transistor, the pixel transistor may output a pixel signal of a voltage corresponding to the level of electric charge generated in the photodiode PD, which would be necessary for a functional device. See paragraphs [0048]-[0049] in Tojinbara.
Allowable Subject Matter
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 22: The following is a statement of reasons for the indication of allowable subject matter: The prior art of record as considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations. The prior art fails to teach or suggest the claimed limitations, namely: “wherein the opening in the trench isolation layer is delimited by the first sidewall and the second sidewall of the trench isolation layer, wherein the floating diffusion region extends laterally along a top of the implant isolation region from beside the first transfer gate to beside the second transfer gate.”
Regarding Claim 23, Takahashi discloses:
Note, See annotated Fig. 10 above. Same notations for photodetectors, transfer gates, and interconnects used herein.
A method for forming an integrated chip (see processing steps shown in Figs. 4-10, and flowchart shown in Fig. 11), the method comprising:
forming a first photodetector (#1D) and a second photodetector (#2D) in a first semiconductor substrate (#104);
forming a first transfer gate (#1G) over the first photodetector (#1D) and a second transfer gate (#2G) over the second photodetector (#2D);
forming a floating diffusion region (#118) in the first semiconductor substrate (#104) according to the first transfer gate (#1G) and the second transfer gate (#2G) so the floating diffusion region (#118) is beside the first transfer gate (#1G) and the second transfer gate (#2G);
forming a first metal interconnect (#1I) over and coupled to the first transfer gate (#1G), a second metal interconnect (#2I) over and coupled to the second transfer gate (#2G), and a third metal interconnect (#3I) over and coupled to the floating diffusion region (#118);
forming a trench isolation layer (#258) extending around and between the first photodetector (#1D) and the second photodetector (#2D), wherein the floating diffusion region (#118) extends laterally between a first sidewall and a second sidewall (see paragraph [0036], Takahashi discloses “In some embodiments, one of the BSI structures 258 may extend in the second direction over both the floating diffusion node 118 and the pick-up well contact region 120.” Under this description, although not explicitly shown in Fig. 10, the FD region would be surrounded by the trench isolation structure, thus would be between a first and second sidewall of the trench isolation structure) of the trench isolation layer (#258) from the first photodetector (#1D) to the second photodetector (#2D);
Takahashi does not explicitly disclose:
forming an implant isolation region in the first semiconductor substrate between the first photodetector and the second photodetector;
forming a first pixel transistor along a second semiconductor substrate;
forming a fourth metal interconnect over the second semiconductor substrate and coupled to the first pixel transistor; and
bonding the second semiconductor substrate and the first semiconductor substrate so the floating diffusion region is coupled to the first pixel transistor through the third metal interconnect and the fourth metal interconnect.
However, in analogous art, Tojinbara teaches:
See Fig. 17. For convenience, 1st-3rd interconnects are shown/labelled in annotated Tojinbara Fig. 17 above. These correspond to 1st-3rd interconnects in annotated Takahashi Fig. 10.
forming a first pixel transistor (#AMP) along a second semiconductor substrate (#200);
forming a fourth metal interconnect (#4I) over the second semiconductor substrate (#200) and coupled to the first pixel transistor (#AMP); and
bonding the second semiconductor substrate (#200) and the first semiconductor substrate (#100) so the floating diffusion region (#FD) is coupled to the first pixel transistor (#FD) through the third metal interconnect (#3I) and the fourth metal interconnect (#4I).
Additionally, in analogous art, Um discloses:
See generally Fig.4 and 5A-5C.
forming an implant isolation region (Fig. 5a, #PIS, includes elements #111, #113, and #115, specifically p-type doped liner (barrier dopant region) #115, [0084]) in the first semiconductor substrate between the first photodetector and the second photodetector;
depositing a trench isolation layer (Fig. 4, #P2b) on the sides of the floating diffusion region (#FDa-FDd) and the sides of the implant isolation region (#115), wherein the trench isolation layer extends around and between the first photodetector and the second photodetector (see top view in Fig. 4 and cross-sectional view in Fig. 5A);
The cited prior art fails to disclose the following limitation in combination with the other claimed limitations:
exposing sides of the floating diffusion region and sides of the implant isolation region;
Therefore, the cited prior art references alone, or in combination with each other, fail to disclose, teach, or suggest, every limitation of the invention as claimed. Thus, claim 23 is allowed, and subsequent dependent claims 24-31 and 39 are allowed at least for their dependency on claim 23.
Citation of Pertinent Prior Art
US 2025/0294905 A1 – Kuo et al
US 2024/0072090 A1 – Chung et al
US 2023/0268372 A1 – Hsu et al
US 2022/0336506 A1 – Lee
US 2022/0013554 A1 – Mun et al
US 2018/0090534 A1 – Kim et al
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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