DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 19-39 are under consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19 and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hook et al (US 2024/0379657).
With respect to Claim 1, Hook et al a method for manufacturing a semiconductor structure (Figures 1-2, paragraphs 9-10, adjacent) comprising: forming a base structure having a first base region (Figure 1, 12) and a second base region (Figure 2, 12); forming a diode device (Figure 1, above 12) on the first base region, the diode device being formed with a first base feature (Figure 1, 16L, 14 and 16R) formed in the first base region, a second feature (Figure 1, 28L, 26 and 28R) formed over the first feature,
a third feature (Figure 1, 24, 20, 24) disposed between the first feature and the second feature, the first feature (Figure 1, n-doped and p-doped, paragraph 14) having a conductivity type opposite to a conductivity type of the second feature (Figure 1, p-doped and n-doped, paragraph 14), a third feature (Figure 1, 24) having a dopant concentration lower (Figure 1, 24, insulator doping is zero) than a dopant concentration of each of the first feature and the second feature; and forming a semiconductor device (Figure 2) on the second base region (Figure 2, 12), the semiconductor device including source/drain features having a conductivity type (p or n, paragraphs 46-47 ) as the second feature. See Figures 1-2 and corresponding text, especially paragraphs 14-29, 34-37 and 46-47.
With respect to Claim 21, Hook et al discloses a method for manufacturing a semiconductor structure (Figures 1-2, paragraphs 9-10, adjacent), comprising: forming (formation of element is inherent if element is present) a first semiconductor stack (stacked layers on 12, Figure 1) and a second semiconductor stack (stacked layers on 12, Figure 2) respectively on a first base region and a second base region (first and second bases are adjacent, paragraphs 9-10), each of the first semiconductor stack and the second semiconductor stack including first semiconductor layers and second semiconductor layers which are disposed to alternate with the first semiconductor layers (Figures 1, 2, layers 16, 28, 38 and 50), the first semiconductor layers being made of a first semiconductor material, the second semiconductor layers being made of a second semiconductor material different from the first semiconductor material; performing a diode-forming process on the first semiconductor stack to form a diode device (Figure 1), which includes a first feature formed in the first base region and a second feature over the first feature, the first feature and the second feature having two different conductivity types (Figure 1, 16L and 28R); and performing a transistor – forming process on the second semiconductor stack to form a transistor (Figure 2). See Figures 1-2 and corresponding text, especially paragraphs 14-29 and 34-37.
Allowable Subject Matter
Claims 20 and 22-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 29-38 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to Claims 29-38, the cited prior art does not disclose inter alia “ forming a first sacrificial gate feature and a second sacrificial gate feature respectively on the first semiconductor stack and the second semiconductor stack; performing a diode-forming process on two portions of the semiconductor stack to form two diode devices, the two portions of the first semiconductor stack being disposed at two opposite sides of the first sacrificial gate feature, each of the two devices including a first feature formed in the first base region and a second feature formed over the first feature, a conductivity type of the first feature being different from a conductivity type of the second feature”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6.
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AGG
November 25, 2025
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812