DETAILED ACTION
This action is responsive to the application No. 18/321,411 filed on May 22, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I and Modification A corresponding to claims 1-6 and 8, in the reply filed on January 20, 2026 is acknowledged. Claims 7 and 9 are withdrawn from consideration.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 6, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Toida (JP 2019-212824, citations from machine translation), of record.
(Re Claim 1) Toida teaches a manufacturing method of chips in which a wafer segmented into a plurality of regions by a plurality of planned dividing lines set in a lattice manner is divided to manufacture the chips (Fig. 1, wafer with dividing lines, ¶8), the manufacturing method comprising:
a groove forming step of holding the wafer including a first surface and a second surface by a holding table and forming grooves having a depth smaller than a thickness of the wafer along the planned dividing lines on a side of the first surface of the wafer (grooves formed by saw blade in Fig. 3 while wafer on table 13, ¶¶21-23);
a first protective film coating step of coating the first surface of the wafer and side surfaces of the grooves with a first protective film after the groove forming step ; and a dividing step of dividing the wafer along the planned dividing lines after the first protective film coating step, wherein plasma etching is executed for the wafer from the side of the first surface in the dividing step (next a Bosch etch process is performed wherein a cycle of isotropic etching, followed by a passivation step, then an anisotropic etch step is performed to break through the passivation in the bottom of the trench, and then the cycle is repeated until the wafer is etched through, the passivation layer forming step forms the passivation on all exposed surfaces and meets the protective film forming step, ¶¶24-35, see Figs. 5-13).
(Re Claim 3) further comprising: a protective film removal step of removing parts that coat bottom surfaces of the grooves in the first protective film to expose the bottom surfaces of the grooves by executing plasma etching for the wafer from the side of the first surface after the first protective film coating step and before the dividing step (¶¶24-35, see Figs. 5-13).
(Re Claim 4) further comprising: a plasma etching step of executing plasma etching for the wafer from the side of the first surface in a state in which the grooves are exposed after the groove forming step and before the first protective film coating step (first etch step, Fig. 7, ¶24).
(Re Claim 6) wherein, in the dividing step, the wafer is divided along the planned dividing lines by executing the plasma etching for the wafer until the grooves reach the second surface of the wafer (Fig. 11).
(Re Claim 8) wherein the grooves are formed by causing an annular cutting blade to cut into the wafer in the groove forming step (Fig. 3, saw blades 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Toida as applied above, and further in view of Wang et al. (US 2022/0059359).
(Re Claim 2) Toida teaches using the Bosch etch process (¶¶24-35, Figs. 5-13) wherein each cycle includes a first isotropic etch, followed by a passivation film coating step, followed by an anisotropic etch step to break through the passivation in the bottom of the trench, and then the cycle repeats. Thus, during the Bosch process, a second protective film coating step of coating the side surfaces and bottom surfaces of the grooves with a second protective film, an anisotropic plasma etching step of executing anisotropic plasma etching for the wafer from the side of the first surface to expose the bottom surfaces of the grooves, and an isotropic plasma etching step of executing isotropic plasma etching for the wafer from the side of the first surface to etch the bottom surfaces of the grooves.
Toida is silent regarding the second protective film thinner than the first protective film. It is noted in Toida’s Bosch etching, the backside of the substrate is etched (Fig. 11, 101), and Toida must account for this thickness loss by adjusting other processes (¶61) which adds complexity to the process as this requires some form of feedback and/or feedforward control is required. In related art, Wang similarly discloses a Bosch etch process wherein a first protective layer 120 is formed considerably thicker than the subsequent protective layers 132 formed during the Bosch cycles (¶¶6-8, 17, 24, 31-32, 46). This first protective layer 120 is thick enough to survive the entire process and protects the horizontal backside of the workpiece during the process while the thinner protective layers 132 formed during the Bosch deposition cycles, in particular on the horizontal backside surface, may be consumed during the anisotropic etch steps. While Wang recognizes the thicker layer is beneficial for reducing undercut and improving CD (¶17), a PHOSITA would recognize the clear advantages of simply protecting the backside of the wafer to avoid unintended thickness loss during the etching. Furthermore, this would substantially reduce loading effects thereby maintaining high etch rates in the grooves. Thus a PHOSITA would find it obvious to incorporate Wang’s thicker protective layer 120 in Toida’s process following the groove formation step to eliminate thickness loss thereby simplifying the process as no feedback and/or feedforward control would be required while having the added benefit of reducing or eliminating loading effects.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Toida as applied above, and further in view of Bhardwaj et al. (US 6,051,503), Wu et al. (J. Appl. Phys. 108, 051101 (2010)), and Craigie et al. (J. Vac. Sci. Technol. B 20(6), 2002).
(Re Claim 2) Toida teaches using the Bosch etch process (¶¶24-35, Figs. 5-13) wherein each cycle includes a first isotropic etch, followed by a passivation film coating step, followed by an anisotropic etch step to break through the passivation in the bottom of the trench, and then the cycle repeats. Thus, during the Bosch process, a second protective film coating step of coating the side surfaces and bottom surfaces of the grooves with a second protective film, an anisotropic plasma etching step of executing anisotropic plasma etching for the wafer from the side of the first surface to expose the bottom surfaces of the grooves, and an isotropic plasma etching step of executing isotropic plasma etching for the wafer from the side of the first surface to etch the bottom surfaces of the grooves.
Toida is silent regarding the second protective film thinner than the first protective film. A PHOSITA would recognize the Bosch etching disclosed will naturally form thinner protective films the deeper the etched trench as discussed below. Alternatively, in order to control trench profile, one may deliberately form subsequent protective films thinner as discussed below. Related art from Wu recognizes the aspect ratio influences the etching and deposition (pp. 8-9, Section E. ARDE), and the higher the aspect ratios (i.e. when etching a deeper feature), the slower the etching and deposition at the bottom of the trench. This is due to the reduced mass transport caused by the higher and higher aspect ratio features formed during the Bosch etching during the etching. This will naturally cause the polymer deposition step to form thinner and thinner layers the deeper the trench is etched. Thus Toida’s subsequent protective films will be slightly thinner. Related art from Craigie teaches the sidewall profile can be controlled by the amount of the polymer layer formed by either depositing for longer durations or increasing the flow of the deposition gas (Fig. 2). Related art from Wu also recognizes the profile dependence on the duration of the individual etching and passivation steps (see pp. 7-8 Section D. Profile). Related art from Bhardwaj discloses a Bosch etch process wherein the deposition gas flow is reduced (and therefore the polymer thickness) for each cycle (see Fig. 20). In view of the prior art, a PHOSITA would recognize as Toida’s Bosch etching continues through the wafer, it will naturally form thinner films as discussed by Wu. Further noting, Toida does not disclose changing or adjusting the cycles during the Bosch etching. Additionally, one could deliberately reduce the deposition cycle flow or duration to decrease the amount of deposition to control the sidewall profile as desired according to Creigie and Bhardwaj.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Toida as applied above, and further in view of Brunnbauer et al. (US 2016/0211178) and Obata et al. (US 2017/0133269).
(Re Claim 5) wherein the grooves are formed in such a manner that an aspect ratio B/A of a width A of the grooves and a depth B of the grooves becomes equal to or higher than 1 in the groove forming step.
Toida is silent with respect to the groove dimensions, however Toida’s Fig. 4 shows the bottom portion 302 of the groove having approximately a 1:1 aspect ratio. Alternatively, the upper portion has a width approximately equal to the entire depth, so based on Fig. 4, a PHOSITA would find an approximately 1:1 aspect ratio obvious as this is what the figure fairly suggests. Alternatively, a PHOSITA may be motivated to look to related art to teach approximate dimensions based on standard wafer thicknesses and conventional dicing blade thicknesses. For a standard 8”-12” silicon wafer, the thickness is between ~725 to ~775 µm. According to Brunnbauer (¶69) and Obata (¶12), dicing blades are typically in a range of ~10-50 µm thick. When considering conventional wafer and blade thicknesses, and that Toida’s groove depth is between 1/3-1/2 of the wafer thickness (Fig. 4), when using a 50 µm blade (thickest, worst case scenario) for a depth of 1/3 (conservative, worst case estimate), for an 8” wafer this results in an aspect ratio of ~4.8, and obviously well within the claimed range.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related Bosch etching, plasma and blade dicing processes.
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898