Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) presented have been considered but are moot because of the new ground of rejection as a result of the amendment to the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 11 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zang et al. [US PGPUB 20180366553] (hereinafter Zang).
Regarding claim 11, Zang teaches a method for forming a semiconductor structure, comprising:
forming a dummy gate structure (106A/B, Para 57, Fig. 6) over an active region (region under gate structure, Fig. 6);
forming a gate spacer layer (114, Para 27) alongside the dummy gate structure (Fig. 6);
removing the dummy gate structure (Para 29, Fig. 7);
forming a gate dielectric layer (120A, Para 30) along the gate spacer layer (Fig. 7);
forming a gate electrode layer (120B/C, Para 83/84) over the gate dielectric layer (Fig. 7);
recessing the gate spacer layer (Fig. 14);
recessing the gate dielectric layer (Fig. 14);
forming a lining layer (132, Fig. 14) surrounding a portion of the gate electrode layer protruding from the gate dielectric layer (Fig. 14) and over the gate spacer layer (Fig. 14), wherein the lining layer comprises a dielectric material (Para 33).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Zang in view of Tomida [US PGPUB 20210233998].
Regarding claim 12, Zang teaches a method for forming a semiconductor structure wherein a dielectric constant of the lining layer is less than 20 (wherein lining 132 is silicon nitride, Para 33).
Zang does not specifically disclose that a dielectric constant of the gate dielectric layer is greater than 20.
However, it is noted that Zang teaches that a dielectric constant of the gate dielectric layer is greater than 10 (Para 30).
In view of such teaching by Zang, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to consider other gate dielectric layer as the gate dielectric layer of the device in as much as the dielectric constant of the gate dielectric layer is greater than 10.
Referring to the invention of Tomida, Tomida teaches various material for a gate dielectric layer, wherein in an instance, High-k material such as hafnium oxide is used (where hafnium oxide has dielectric constant greater than 20).
In view of such teaching by Tomida, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Zang comprise the teachings of Tomida at least based on the rationale of relying on teachings and/or suggestion (as disclosed by Zang) which would have led one of ordinary skill to modify the prior art reference reference teachings to arrive at the claimed invention (MPEP 2143.I.G). In another instance, a person having ordinary skills in the art before the effective filing date of the claimed invention would have been motivated to select other material such as hafnium oxide at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B) –wherein hafnium oxide is known to help mitigate short-channel effects and reduces leakage current.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Zang in view of Chen.
Regarding claim 16, Zang teaches a semiconductor structure, comprising:
a substrate (102, Para 21);
a gate stack (120A-C, Para 30), wherein the gate stack comprises a gate electrode layer (120B-C, Para 30) and a gate dielectric layer (120A, Para 30) surrounding and in direct contact with a lower portion of the gate electrode layer (Fig. 14); and
a lining layer (132, Fig. 14) surrounding and in direct contact with an upper portion of the gate electrode layer (Fig. 14), wherein a dielectric constant of the lining layer is lower than a dielectric constant of the gate dielectric layer (wherein lining layer 132 is silicon nitride (Para 33) and gate dielectric layer is a dielectric material with dielectric constant great than 10, Para 30/37), wherein the lining layer comprises a dielectric material (Para 33).
Zang does not specifically disclose a plurality of nanostructures over a substrate; and
a gate stack above a topmost one of the nanostructures.
However, it noted that Zang discloses the present invention being related to nanowire device.
In view of such teaching by Zang, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Zang implemented in nanostructure device at least based on the rationale of applying a known technique to a known device (method, or product) ready for improvement to yield predictable results (MPEP 2143.I.D).
Referring to the invention of Chen, Chen teaches a plurality of nanostructures (55N, Para 56) over a substrate (Fig. 16B); and
a gate stack (112/114, Para 57) above a topmost one of the nanostructures (Fig. 16B).
In view of such teaching by Zang, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Zang implemented in nanostructure device at least based on the rationale of applying a known technique to a known device (method, or product) ready for improvement to yield predictable results (MPEP 2143.I.D).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zang in view Chen and further in view of Hwang et al. [US PGPUB 20240145567] (hereinafter Hwang).
Regarding claim 20, Zang teaches the limitation of claim 16 upon which it depends.
Zang does not specifically disclose a semiconductor structure wherein the upper portion of the gate electrode layer surrounded by the lining layer is narrower than the lower portion of the gate electrode layer surrounded by the gate dielectric layer.
Referring to the invention of Hwang, Hwang teaches a semiconductor structure wherein the gate structure of the semiconductor structure has different shapes (Figs. 22-25), wherein in an instance (Fig. 23) an upper portion of the gate electrode layer (300) is narrower than a lower portion of the gate electrode layer (Fig. 23).
In view of such teaching by Hwang, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Zang comprise the teachings of Hwang at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B).
Allowable Subject Matter
Claims 1 and 3-10 allowed.
Claims 13-15, 17-19 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1 and 3-10 are allowed because all prior arts on record on record either singularly or in combination fail to anticipate or render obvious a method for forming a semiconductor structure, comprising:
recessing the gate dielectric layer to expose the gate electrode layer, wherein after recessing the gate dielectric layer, a top surface of the gate dielectric layer is lower than a top surface of the gate electrode layer; (as claimed in claim 1), in combination with the rest of claim limitations as claimed and defined by the Applicant.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ISMAIL A MUSE/Primary Examiner, Art Unit 2812