DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prosecution Reopened
Upon further search and consideration the indicated allowability of claims 1-6, 8, and 22 is withdrawn in view of the newly discovered reference(s) US 20210098377 A1. Rejections based on the newly cited reference(s) follow. This Office action is therefore Non-Final.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Hyo-Jin Kim et al. (US 20210098377 A1; hereinafter Kim) in view of Fu-Hsiang Su et al. (US 20200043787 A1; hereinafter Su).
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Regarding Claim 1, Kim teaches a semiconductor structure (see annotated Fig. 5), comprising:
a first gate structure (in view of Fig. 4; 280; ¶0019; labeled 280L in annotated Fig. 5 for clarity);
a second gate structure (in view of Fig. 4; 280; labeled 280R in annotated Fig. 5 for clarity);
a source/drain contact (metal silicide 320 which contacts source/drain 210; ¶0036, ¶0019) disposed between the first gate structure (280L) and the second gate structure (280R) along a direction (1st direction);
a first gate spacer (160 in view of Fig. 1; ¶0029; labeled in the annotated Fig. 5 as 160L) disposed between the first gate structure (280L) and the source/drain contact (320);
a second gate spacer (160 in view of Fig. 1; ¶0029; labeled in the annotated Fig. 5 as 160R) disposed between the second gate structure (280R) and the source/drain contact (320);
an etch stop layer (ESL) (capping layer 290 made of a nitride which may provide etch stopping relative to oxide layer 300; ¶0035) over the source/drain contact (320) and the second gate spacer (160R) (wherein ESL 290 is disposed at a level “over” that of 320);
a first dielectric layer (300+360; ¶0020) over the ESL (290);
a second dielectric layer (400) over the first dielectric layer (300+360);
a butted contact (394 and 334 directly adjacent to the right; hereinafter 394+334) spanning over the first gate structure (280L) and the source/drain contact (320), the butted contact (394+334) being in contact with the source/drain contact (320) (they are in electrical and physical contact); and
a gate contact (392+414; ¶0046 ¶0058) extending through the second dielectric layer (400), the first dielectric layer (300+360) and the ESL (290),
wherein the second dielectric layer (400) is disposed directly on a top surface of the butted contact (top of 394+334) (as shown in annotated Fig. 5).
Kim does not expressly disclose wherein the first gate structure comprises a first cap layer thereon and the second gate structure comprises a second cap layer thereon, wherein the butted contact is in contact with the first cap layer, and wherein the gate contact contacts the second cap layer.
In the same field of endeavor, Su teaches a similar device in Fig. 1J comprising a cap layer (114; ¶0017; and/or dielectric cap layer 124; ¶0020) on a first gate structure (110c; ¶0023) and a second gate structure (110a) in a semiconductor device, wherein the top of the cap layers (114/124) are coplanar with the top of the gate spacers (112+136; ¶0018 ¶0030).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the cap layer(s) of Su on the gate structures of Kim in order to provide protection for the gate structure and/or provide work function modulation for the gates of the semiconductor device.
Kim modified to include the cap layers of Su would result in the butted contact (394+334) being in contact with the first cap layer, and the gate contact (392+414) being in contact with the second cap layer.
Regarding Claim 2, modified Kim teaches the semiconductor structure of claim 1, wherein the source/drain contact (320) comprises cobalt and is free of a barrier layer (as shown in Fig. 5 and comprises cobalt; ¶0036).
Regarding Claim 3, modified Kim teaches the semiconductor structure of claim 1, wherein the first cap layer and the second cap layer comprise fluorine-free tungsten (tungsten; Su ¶0017).
Regarding Claim 4, modified Kim teaches the semiconductor structure of claim 1, wherein the butted contact (394+334) comprises: a barrier layer (barrier pattern covering sidewall and lower surface of the metal fill; ¶0039 and ¶0049) interfacing the first gate spacer (Su; 114) and the source/drain contact (334); and a metal fill (¶0039 ¶0049) disposed over the barrier layer, wherein the metal fill is spaced apart from the first gate spacer (116L) and the source/drain contact (320) by the barrier layer.
Regarding Claim 5, modified Kim teaches the semiconductor structure of claim 1, wherein a top surface of the butted contact (top of 394+334) and a top surface of the first dielectric layer (top of 300+360) are coplanar.
Regarding Claim 6, modified Kim teaches the semiconductor structure of claim 1, further comprising: a dielectric capping layer (Su; Fig. 1J; 124; ¶0020) disposed over the first cap layer (Su; 114).
Regarding Claim 8, modified Kim teaches the semiconductor structure of claim 1, wherein the butted contact (394+334) comprises:
an upper portion (394) disposed in the ESL (290) and the first dielectric layer (300+360); and a lower portion (334) extending downward from the upper portion through the first cap layer (as modified by Su; 124), wherein the lower portion (334) comprises a first width along the direction (1st direction),
wherein the upper portion (394) comprises a second width along the direction (1st direction),
wherein the first width (of 334) is less than the second width (of 394).
Modified Kim does not expressly disclose wherein the first width (of 334) is between about 10 nm and about 25 nm, and wherein the second width (of 394) is larger and between about 14 nm and about 40 nm. However the general proportions of Kim satisfy the claim, and the device scale is established in view of Su ¶0026 to be in the 14-22nm range for the gate contacts.
Absent any evidence of unexpected results or criticality, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the widths of the portions of the butted contact to be within those of the claimed ranges in order to scale down the device while ensuring adequate separation between the lower portion of the butted contact and the next adjacent gate structure. MPEP 716.02.
Regarding Claim 22, modified Kim teaches the semiconductor structure of claim 4, wherein the barrier layer comprises titanium nitride (Kim; ¶0039 ¶0049), wherein the metal fill comprises tungsten (Kim; ¶0039 ¶0049).
Allowable Subject Matter
Claims 10-12, 14-20, and 23 are allowed.
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 10, the prior art of record teaches the limitations of previously
presented claim 10 (see previous Office action). However, the references of the Prior
Art of record and considered pertinent to the applicant's disclosure and to the
examiner’s knowledge does not teach or render obvious, at least to the skilled artisan,
the instant invention regarding: further comprising the limitations of previously presented
claim 13, including: a third active region extending lengthwise along the first direction; a
third gate segment extending lengthwise along the second direction and wrapping over
a first channel region of the third active region; a fourth gate segment extending
lengthwise along the second direction and wrapping over a second channel region of
the third active region; and a third source/drain contact extending lengthwise along the
second direction and disposed between the third gate segment and the fourth gate
segment, wherein the third gate segment and the first gate segment are aligned along
the second direction, wherein the fourth gate segment and the second gate segment
are aligned along the second direction”. For at least this reason claims 11-12, 14-15,
and 23 would also be allowed based on their dependency from claim 13.
Regarding Claim 16, the closest prior art (Chen; Fig. 18A) teaches a structure,
comprising:
an active region (5) extending lengthwise along a first direction and comprising a
first channel region (under left gate 10), a second channel region (under middle gate
10), and a source/drain region (50) disposed between the first channel region and the
second channel region (Fig. 18A);
a source/drain feature (50+55) disposed over the source/drain region;
a first gate structure disposed over the first channel region (left 10);
a second gate structure disposed over the second channel region (middle gate
10);
a metal cap layer over the first gate structure;
a dielectric capping layer (20) over the metal cap layer;
a first gate spacer (30) disposed along and in contact with sidewalls of the first
gate structure, the metal cap layer and the dielectric capping layer;
a second gate spacer (30) disposed along and in contact with a sidewall of the
second gate structure (middle gate 10)
a contact etch stop layer (CESL) disposed along and in contact with the first gate
spacer, the second gate spacer and a top surface of the source/drain feature;
a first interlayer dielectric layer (ILD) (40) over the CESL;
a source/drain contact (66) extending through the first ILD and the CESL to
contact the source/drain feature (50) by way of a silicide feature (55);
an etch stop layer (ESL) (72) disposed over and interfacing a top surface of the
CESL, a top surface of the first ILD layer (40), a top surface of the first gate spacer (30),
a top surface of the second gate spacer (30), and a top surface of the dielectric capping layer (20);
a second ILD layer (70) over the ESL (72);
a local interconnect structure (83) comprising:
a lower portion extending through the dielectric capping layer (20) to contact the
metal cap layer, and
an upper portion over the lower portion and a top surface of the source/drain
contact (66);
a third ILD layer (90) disposed on a top surface of the local interconnect structure
and the second ILD layer; and
a gate contact (67) extending through the third ILD, the second ILD, and ESL
toward the second gate structure (down),
wherein top surfaces of the gate contact (67+83G+88G) and the third ILD layer
(90) are coplanar,
wherein a top surface of the upper portion is coplanar with a top surface of the
second ILD layer.
However, the references of the Prior Art of record and considered pertinent to the
applicant's disclosure and to the examiner’s knowledge does not teach or render
obvious, at least to the skilled artisan, all the limitations of the instant invention in their
entirety (the individual limitations may be found just not in combination with proper
motivation); further including: a metal cap layer over the first gate structure, a dielectric
capping layer (20) over the metal cap layer, a first gate spacer (30) disposed along and
in contact with sidewalls of the first gate structure, the metal cap layer and the dielectric
capping layer, a contact etch stop layer (CESL) disposed along and in contact with the
first gate spacer, the second gate spacer and a top surface of the source/drain feature;
an etch stop layer (ESL) (72) disposed over and interfacing a top surface of the CESL, a
lower portion extending through the dielectric capping layer (20) to contact the metal
cap layer; a third ILD layer (90) disposed on a top surface of the local interconnect structure and the second ILD layer; and wherein a top surface of the upper portion is
coplanar with a top surface of the second ILD layer.
For at least these reasons, claims 17-20 are also allowed based on their
dependence from claim 16.
Regarding Objected to dependent claim 21, modified Kim teaches the semiconductor structure of claim 1. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including: wherein the ESL (290) interfaces a top surface of the first gate spacer and the second gate spacer, wherein the first dielectric layer interfaces a top surface of the ESL, wherein the second dielectric layer interfaces a top surface of the first dielectric layer, wherein the first dielectric layer and the second dielectric layer share a same composition.
Conclusion
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898