Prosecution Insights
Last updated: April 18, 2026
Application No. 18/322,045

ELECTRONIC DEVICE

Final Rejection §103§112
Filed
May 23, 2023
Examiner
YAP, DOUGLAS ANTHONY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
3y 3m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
43 granted / 49 resolved
+19.8% vs TC avg
Moderate +12% lift
Without
With
+12.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
48 currently pending
Career history
97
Total Applications
across all art units

Statute-Specific Performance

§103
50.9%
+10.9% vs TC avg
§102
25.2%
-14.8% vs TC avg
§112
21.2%
-18.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 49 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see Remarks, filed 04 March 2026, with respect to the rejections of claims 1, 13, and 17 under 35 U.S.C. § 102 and/or 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Son (US 2022/0418082 A1). Please see 35 U.S.C. § 103 rejections below of claims 1, 13, and 17. In summary, this application is not placed in a condition for an allowance. Specification The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Claims 1, 13, 17 and 23 have been amended to include: a first edge, a second edge, a third edge, and a fourth edge of ceiling wall, a first supporting wall, a second supporting wall, a third supporting wall, and a fourth supporting wall of the shielding unit under each of these respective edges, a first corner, a second corner, a third corner, and a fourth corner of the ceiling wall a first peripheral region, a second peripheral region, a third peripheral region, and a fourth peripheral region all belonging to the magnetic memory element, and two opposite portions of the semiconductor chip are exposed from the third supporting wall. None of these new terminologies introduced in the amendment are defined in the specifications. For the purpose of compact prosecution, the examiner has produced an annotated Figure, see Drawings Objections below, to locate where these claim artifacts are found in the disclosure. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference signs of new claim artifacts as described in the amended claims and are listed in the Objections to Specifications (see above). For the purpose of compact prosecution, the examiner has annotated Figures 1 and 2 of the instant application to locate where these claim artifacts are found. PNG media_image1.png 679 699 media_image1.png Greyscale PNG media_image2.png 584 829 media_image2.png Greyscale Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 20 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 20 recites the limitation "the magnetic material.” There is insufficient antecedent basis for this limitation in the claim since the reference of a magnetic material has been removed in the amended parent claim 17. For the purpose of compact prosecution, the examiner will use the definition of “a magnetic material” as written in the previous claim 17. Claim 26 recites the limitation "the first direction" in the clause “the second direction being different from the first direction.” There is insufficient antecedent basis for this limitation in the claim. Neither claim 25 nor parent claim 17 defines “a first direction.” For the purpose of compact prosecution, the examiner will use the definition of “a first direction” as written in claim 25. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-5, 8-11, 17, 20-22 and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 2016/0322562 A1) in view of Son (US 2022/0418082 A1). Regarding claim 1, Jang teaches an electronic device (Figs. 1-24: magneto-resistive chip package 200 and various embodiments) comprising: a printed circuit board (102); a semiconductor chip mounted (108) and electrically connected to the printed circuit board (using wires 112), and including a magnetic memory element (110, see ¶ [0080]); and a shielding unit (118) including a magnetic material (118a or 118b, see ¶ [0074]-[0075] and Figs. 4A & 4B), and mounted to the printed circuit board (Figs. 2-3, 10, 13, 15-24 shows 118 having a base 104 that is mounted on 102; see also ¶ [0078] ) to at least partially cover the magnetic memory element (the abovementioned figures show 118 having a top cover 116 that covers 110; see ¶ [0086]-[0087] ) so as to reduce interference from an external magnetic field on the magnetic memory element (¶ [0004, ¶ [0074]), the shielding unit including a ceiling wall (116) having a first edge (top right edge), a second edge adjacent (bottom right edge) to the first edge, a third edge (bottom left edge) opposite the first edge, and a fourth edge (top left edge) opposite the second edge; and a plurality of supporting walls (COL). However, Jang does not teach the electronic device wherein the supporting walls comprises of a first supporting wall, a second supporting wall, a third supporting wall, and a fourth supporting wall, which extend in an upright direction to connect respectively to the first edge, the second edge, the third edge, and the fourth edge, wherein the first supporting wall and the second supporting wall extend respectively along the first edge and the second edge, and are connected to each other at a first corner between the first edge and the second edge, wherein the third supporting wall extends along the third edge, and is spaced apart from a second corner between the second edge and the third edge, and a third corner between the third edge and the fourth edge, and wherein the fourth supporting wall extends along the fourth edge, and is spaced apart from the third corner and a fourth corner between the first edge and the fourth edge. Son, in the same field of invention, teaches an electronic device having a shielding unit (12, see Fig. 12; this is an embodiment of shielding unit 6 in Figs. 6-9 and ¶ [0096] ) further comprising: a first supporting wall (W1, see examiner Fig. 1; ¶ [0121]: W1 is part of support structure 1221 ), a second supporting wall (W2; ¶ [0121]: W2 is part of support structure 1221), a third supporting wall (W3, with W3 analogous to a third portion 63 in Fig. 6; ¶ [0099] explains that third portion 63 disposed on and connected to conductive pads 81 of PCB 441; hence W3 is a supporting wall ), and a fourth supporting wall (W4, with W4 analogous to another third portion 63 in Fig. 6; ¶ [0099] explains that third portion 63 disposed on and connected to conductive pads 81 of PCB 441; hence W4 is a supporting wall), which extend in an upright direction (along the z-axis) to connect respectively to the first edge (E1), the second edge (E2), the third edge (E3), and the fourth edge (E4), wherein the first supporting wall and the second supporting wall extend respectively along the first edge (W1 extends along the y-axis) and the second edge (W2 extends along the x-axis), and are connected to each other at a first corner (C1) between the first edge and the second edge, wherein the third supporting wall extends along the third edge (W3 extends along the y-axis), and is spaced apart from a second corner (C2) between the second edge and the third edge, and a third corner (C3) between the third edge and the fourth edge, and wherein the fourth supporting wall extends along the fourth edge (W4 extends along the x-axis), and is spaced apart from the third corner and a fourth corner (C4) between the first edge and the fourth edge. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Son into the device of Jang to add a first support wall, a second supporting wall, a third supporting wall and a fourth supporting wall to the first edge, the second edge, the third edge, and the fourth edge, respectively, in the manner described above. The ordinary artisan would have been motivated to modify Jang in the manner set forth above for at least the purpose of using the shielding unit as a shielding unit of a camera module in a cell phone (Son ¶ [0094]-[0097] ) that uses multiple electronic components (71-74, ¶ [0096]; any of these components are analogous to the magnetic memory element since Son in ¶ [0035]-[0036] teaches a cell phone comprising memory modules ), wherein the first wall and second walls (these walls together form an L-shaped unit) of the shielding unit are unit to improve the rigidity and to reduce the mechanical stress of the shielding unit (¶ [0106]) while the third wall and fourth walls are used as grounding connections of the shielding unit (¶ [0099], ¶ [0210] ). PNG media_image3.png 497 716 media_image3.png Greyscale Examiner Figure 1. Taken from Son Fig. 12. Regarding claim 2, the electronic device according to claim 1, wherein the ceiling wall (116, see Jang Fig. 3) is made of the magnetic material (116 is part of 118, with 118 having 118a that is a magnetic material layer; see Jang ¶ [0074] and ¶ [0086] ), and is disposed on the magnetic memory element opposite to the printed circuit board (ceiling wall 116 is disposed on top of 110, with PCB 102 disposed on the bottom on 110). Regarding claim 3, the electronic device according to claim 2, wherein the first supporting wall, the second supporting wall, the third supporting wall, and the fourth supporting wall support the ceiling wall so as to permit the ceiling wall to be disposed over the magnetic memory element (see Son Fig. 6 where any one of the electronic components 71-74 are analogous to the magnetic memory element of Jang). Regarding claim 4, the electronic device according to claim 3, wherein at least one of the first supporting wall, the second supporting wall, the third supporting wall, and the fourth supporting wall is made of the magnetic material (COL/106 is part of 118, with 118 having magnetic material layers 118a or 118b; see Jang ¶ [0074]-[0075], ¶ [0078] and Fig. 4A or 4B). Regarding claim 5, the electronic device according to claim 3, wherein at least one of the first supporting wall, the second supporting wall, the third supporting wall, and the fourth supporting wall is made of a non-magnetic material (COL/106 is part of 118, with 118 having a non-magnetic layers 118c; see Jang ¶ [0074]-[0076] and Fig. 4B). Regarding claim 8, the electronic device according to claim 1, wherein the printed circuit board has a top surface (Jang Fig. 2: top surface of 102) on which the semiconductor chip and the shielding unit are mounted, the shielding unit occupies an area (the surface area of the top surface of 102 under 116 corresponds to the area the entire 118 occupies on 102) on the top surface of the printed circuit board, the occupied area of the shielding unit ranging from a first value (the surface area of 102 under 104) to a second value (surface area of the top surface of 102 under 116), when the occupied area of the shielding unit is the first value, the shielding unit is configured to permit the semiconductor chip to be fitted thereinside (the first value equals to the surface area of 102 under 104, since chip 110 is on top of 104 and 104 is a part of 118), and when the occupied area of the shielding unit is the second value, the occupied area of the shielding unit is a surface area (surface area of the top surface of 102 under 116) of the top surface of the printed circuit board (the second value equals to the surface area of the top surface of 102 under 116). Regarding claim 9, the electronic device according to claim 1, wherein the semiconductor chip is spaced apart from the shielding unit (Jang Fig. 2 shows chip 108 spaced apart from wall 106 of the shielding unit 118 along the horizontal axis). Regarding claim 10, the electronic device according to claim 1, wherein the semiconductor chip abuts the shielding unit (Jang Fig. 2 and ¶ [0080]: adhesive 107 may be omitted; hence chip 108 abuts, i.e., directly contacts, base 104 of the shielding unit 118). Regarding claim 11, the electronic device according to claim 1, wherein the magnetic memory element is a magnetic random access memory (Jang ¶ [0081]). Regarding claim 17, Jang teaches an electronic device (Figs. 1-3, 9-24: magneto-resistive chip package 200 and various embodiments) comprising: a printed circuit board (102); a semiconductor chip mounted (108) and electrically connected to the printed circuit board (using wires 112), and including a magnetic memory element (110, see ¶ [0080]); and a shielding unit (118) mounted to the printed circuit board (Figs. 2-3, 10-11, 13, 15-24 shows 118 having a base 104 that is mounted on 102; see also ¶ [0078] ) to cover the magnetic memory element (the abovementioned figures show 118 having a top cover 116 that covers 110; see ¶ [0086]–[0087] ), so as to reduce interference from an external magnetic field on the magnetic memory element (¶ [0004], ¶ [0074]), the shielding unit including a ceiling wall (116) having a first edge (top right edge), a second edge adjacent (bottom right edge) to the first edge, a third edge (bottom left edge) opposite the first edge, and a fourth edge (top left edge) opposite the second edge; and a plurality of supporting walls (COL). However, Jang does not teach the electronic device wherein the shielding unit partially covers the magnetic memory element such that the plurality of supporting wall comprises of a first supporting wall, a second supporting wall, a third supporting wall, and a fourth supporting wall, which extend in an upright direction to connect respectively to the first edge, the second edge, the third edge, and the fourth edge, wherein the first supporting wall and the second supporting wall extend respectively along the first edge and the second edge, and are connected to each other at a first corner between the first edge and the second edge, wherein the third supporting wall and the fourth supporting wall extend respectively along the third edge and the fourth edge, and are spaced apart from each other, wherein the magnetic memory element has a first peripheral region facing the first supporting wall, a second peripheral region facing the second supporting wall, a third peripheral region facing the third supporting wall, and a fourth peripheral region facing the fourth supporting wall, and wherein a spaced-apart distance between the first peripheral region and the first supporting wall is smaller than a spaced-apart distance between the third peripheral region and the third supporting wall, and a spaced-apart distance between the fourth peripheral region and the fourth supporting wall. Son, in the same field of invention, teaches a shielding unit (12, see Fig. 12; this is an embodiment of shielding unit 6 in Figs. 6-9 and ¶ [0096] ) partially covers the magnetic memory element (72; ¶ [0100]: 72 is an electronic component; ¶ [0035], [0036]: device 101 may include memory 101 and/or memories 132/134; hence 72 is analogous to the magnetic memory element of Jang) such that the shielding unit includes a first supporting wall (W1, see Examiner Fig. 1 in claim 1 rejection above; ¶ [0121]: W1 is part of support structure 1221 ), a second supporting wall (W2; ¶ [0121]: W2 is part of support structure 1221), a third supporting wall (W3, with W3 analogous to a third portion 63 in Fig. 6; ¶ [0099] explains that third portion 63 disposed on and connected to conductive pads 81 of PCB 441; hence W3 is a supporting wall ), and a fourth supporting wall (W4, with W4 analogous to another third portion 63 in Fig. 6; ¶ [0099] explains that third portion 63 disposed on and connected to conductive pads 81 of PCB 441; hence W4 is a supporting wall), which extend in an upright direction (along the z-axis) to connect respectively to the first edge (E1), the second edge (E2), the third edge (E3), and the fourth edge (E4), wherein the first supporting wall and the second supporting wall extend respectively along the first edge (W1 extends along the y-axis) and the second edge (W2 extends along the x-axis), and are connected to each other at a first corner (C1) between the first edge and the second edge, wherein the third supporting wall and the fourth supporting wall extend respectively along the third edge and the fourth edge (W3 extends along the y-axis; W4 extends along the x-axis), and are spaced apart from each other (W3 and W4 are spaced apart along the x-axis), wherein the magnetic memory element has a first peripheral region (surface of 72 facing W1) facing the first supporting wall, a second peripheral region (surface of 72 facing W2) facing the second supporting wall, a third peripheral region (surface of 72 facing W3) facing the third supporting wall, and a fourth peripheral region (surface of 72 facing W4) facing the fourth supporting wall, and wherein a spaced-apart distance (D1, see Examiner Fig. 2 below) between the first peripheral region and the first supporting wall is smaller than a spaced-apart distance (D3) between the third peripheral region and the third supporting wall, and a spaced-apart distance (D4) between the fourth peripheral region and the fourth supporting wall. PNG media_image4.png 641 531 media_image4.png Greyscale Examiner Fig. 2. Taken from Son Fig. 6 with the shielding unit 12 in Fig. 12 superimposed on the PCB 441. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Son into the device of Jang to add a first support wall, a second supporting wall, a third supporting wall and a fourth supporting wall to the first edge, the second edge, the third edge, and the fourth edge, respectively, with the structural relationships with respect to their corresponding edges and with respect to corresponding peripheral regions of the magnetic memory, are added as described in the manner above. The ordinary artisan would have been motivated to modify Jang in the manner set forth above for at least the purpose of using the shielding unit as a shielding unit of a camera module in a cell phone (Son ¶ [0094]-[0097] ) that uses multiple electronic components (71-74, ¶ [0096]; any of these components are analogous to the magnetic memory element since Son in ¶ [0035]-[0036] teaches a cell phone comprising memory modules ), wherein the first wall and second walls (these walls together form an L-shaped unit) of the shielding unit are unit to improve the rigidity and to reduce the mechanical stress of the shielding unit (¶ [0106]) while the third wall and fourth walls are used as grounding connections of the shielding unit (¶ [0099], ¶ [0210] ). The person of ordinary skill would also be motivated to position the respective supporting walls of the shielding unit with respect to the magnetic memory element in the manner as described above for the purpose of adding more than one electronic components (71, 73-74) to the camera units that are commonly shielded by the shielding unit (see Fig. 6 and ¶ [0160] ). Regarding claim 20, the electronic device according to claim 17, wherein the magnetic material (COL/106 and 116 is part of 118, with 118 having magnetic material layers 118a or 118b; see ¶ [0074]-[0075] and Figs. 4A or 4B) is one of silicon steel, manganese zinc, cobalt iron, nickel iron, and combinations thereof (Jang ¶ [0075]: “magnetic conductive layer may be formed of, for example, a high permeability material including NixFe1-x or NixMoyFe1-x-y. The magnetic conductive layer may be formed by adding another material, such as copper (Cu) or cobalt (Co), to the above-stated material. The magnetic non-conductive layer may include, for example, a ferrite layer, such as a MnZn-ferrite layer or a NiZn-ferrite layer,” emphasis added). Regarding claim 21, the electronic device according to claim 17, wherein a first length (length of W1; see Examiner Fig. 1 in claim 1 rejection above) is a length of the first supporting wall along the first edge; a second length (length of W2) is a length of the second supporting wall along the second edge; a third length (length of W3) is a length of the third supporting wall along the third edge; a fourth length (length of W4) is a length of the fourth supporting wall along the fourth edge; and at least one of the first length and the second length is greater than one of the third length and the fourth length (as shown in Examiner Fig. 1, the lengths of W1 and/or W2 are longer than the lengths of W3 and/or W4). Regarding claim 22, the electronic device according to claim 17, wherein a length of the first supporting wall (length of W1; see Examiner Fig. 1 in claim 1 rejection above) along the first edge is smaller than a length of the first edge (length of E1), and a portion of the semiconductor chip is exposed from the first supporting wall (due to the opening at the right of W1). Regarding claim 24, the electronic device according to claim 17, wherein the third supporting wall is spaced apart from the second supporting wall (Examiner Fig 1, as shown in claim 1 rejection above, shows W3 spaced apart from W2 along the y-axis), and the fourth supporting wall is spaced apart from the first supporting wall (Examiner Fig. 1 shows W4 spaced apart from W1 along the y-axis). Regarding claim 25, the electronic device according to claim 17, wherein the first peripheral region (surface of 72 facing W1, see Examiner Fig. 2 in claim 17 rejection above) is spaced apart (D1) from the first supporting wall (W1) along a first direction (D1 extends along the x-axis), and the third peripheral region (surface of 72 facing W3 is spaced apart (D3) from the third supporting wall along the first direction (D3 extends along the x-axis), the first supporting wall extends along the first edge to entirely cover the first peripheral region along the first direction (Examiner Fig. 2 shows the entire surface that faces W1 is covered by W1; also note that Examiner Fig. 1 shows W1 longer than what is illustrated in Examiner Fig. 2), and the third supporting wall extends along the third edge to partially cover the first peripheral region along the first direction (Examiner Fig. 2 shows W3 having openings to the left and right of it; hence it is partially covering the surface of 72 facing W3). Regarding claim 26, the electronic device according to claim 17, wherein a spaced-apart distance (D2, see Examiner Fig. 2 in claim 17 above) between the second peripheral region and the second supporting wall is smaller than the spaced-apart distance (D3) between the third peripheral region and the third supporting wall, and the spaced-apart distance (D4) between the fourth peripheral region and the fourth supporting wall, the second peripheral region is spaced apart from the second supporting wall along a second direction (D2 extends along the y-axis), and the fourth peripheral region is spaced apart from the fourth supporting wall along the second direction (D4 extends along the y-axis), the second direction being different from the first direction (x-axis; see 35 U.S.C. § 112 (b) rejection above), the second supporting wall extends along the second edge to entirely cover the second peripheral region along the second direction (Examiner Fig. 2 shows W2 extending along x-axis to cover completely the surface of 72 that faces W2; also note that Examiner Fig. 1 shows W2 longer than what is illustrated in Examiner Fig. 2), and the fourth supporting wall extends along the fourth edge to partially cover the fourth peripheral region along the second direction (Examiner Figs. 1& 2 shows W4 having openings to the left and right of it; hence it is partially covering the surface of 72 facing W4). Claims 13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Tuttle (US 6,625,040 B1) and further in view of Graham (US 2016/0064141 A1) and Son (US 2022/0418082 A1). Regarding claim 13, Tuttle teaches an electronic device (10) comprising: a printed circuit board (20); a semiconductor chip (12) mounted and electrically connected (using 14 and 15) to the printed circuit board, and including a magnetic memory element (Col. 2, Lns 55-57: “integrated circuits 12 which, in turn, include internal electromagnetic structures, such as MRAM cells”); and a shielding unit (33) made of a magnetic material (Col. 3, Lns 26-37), and mounted to the printed circuit board (Figs. 2-4 show 33 mounted on 20) to at least partially cover the magnetic memory element so as to reduce interference from a magnetic field (Col. 1, Ln 60: external magnetic fields) from the magnet on the magnetic memory element (Col. 2, Lns 65-66). However, Tuttle does not teach the electronic device comprising of a magnet disposed to be spaced apart from the printed circuit board. Graham, in the same field of invention, teaches an electronic device (Fig. 2: 101) comprising of a magnet (208) disposed to be spaced apart (208 is vertically spaced apart from 213) from the printed circuit board (213). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Graham into the device of Tuttle to provide a magnet spaced apart from the printed circuit board. The ordinary artisan would have been motivated to modify Tuttle in the manner set forth above for at least the purpose of using the magnet as an alignment magnet (Graham ¶ [0027]) that aligns the transmit coils (202) of the electronic device with the receive coils (218) of a second device (102) in order to enable an inductive power transmission system (100, see Graham Fig. 1 and ¶ [0025]), which effectively acts as a wireless charging pads for smart phones, wearable devices, etc. (¶ [0025]). Tuttle further teaches the shielding unit comprising of a ceiling wall (top horizontal surface of 33) having a first edge, a second edge adjacent to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge (since 33 is a three-dimensional object having a U-shaped cavity, then the ceiling wall has all these four edges) and a first supporting wall, a second supporting wall, a third supporting wall, and a fourth supporting wall, which extend in an upright direction to connect respectively to the first edge, the second edge, the third edge, and the fourth edge (33 is illustrated in Figs. 1-4 to be a U-shaped lid having vertical walls; each of the four vertical walls correspond to the claimed first, second, third, and fourth supporting walls). However, Tuttle in view of Graham does not teach the electronic device wherein the first supporting wall and the second supporting wall extend respectively along the first edge and the second edge, and are connected to each other at a first corner between the first edge and the second edge, wherein the third supporting wall and the fourth supporting wall extend respectively along the third edge and the fourth edge, and are spaced apart from each other, wherein a spaced-apart distance between the semiconductor chip and the first supporting wall is smaller than a spaced-apart distance between the semiconductor chip and the third supporting wall, and a spaced-apart distance between the semiconductor chip and the fourth supporting wall, and wherein a spaced-apart distance between the semiconductor chip and the second supporting wall is smaller than the spaced-apart distance between the semiconductor chip and the third supporting wall, and the spaced-apart distance between the semiconductor chip and the fourth supporting wall. Son, in the same field of invention, teaches an electronic device having a shielding unit (12, see Fig. 12; this is an embodiment of shielding unit 6 in Figs. 6-9 and ¶ [0096] ), wherein the first supporting wall (W1, see Examiner Fig. 1 in claim 1 rejection above; ¶ [0121]: W1 is part of support structure 1221 ) and the second supporting wall (W2; ¶ [0121]: W2 is part of support structure 1221) extend respectively along the first edge (E1) and the second edge (E2), and are connected to each other at a first corner (C1) between the first edge and the second edge, wherein the third supporting wall (W3, with W3 analogous to a third portion 63 in Fig. 6; ¶ [0099] explains that third portion 63 disposed on and connected to conductive pads 81 of PCB 441; hence W3 is a supporting wall ) and the fourth supporting wall (W4, with W4 analogous to another third portion 63 in Fig. 6; ¶ [0099] explains that third portion 63 disposed on and connected to conductive pads 81 of PCB 441; hence W4 is a supporting wall) extend respectively along the third edge (E3) and the fourth edge (E4), and are spaced apart from each other, wherein a spaced-apart distance (D1, see Examiner Fig. 2 in claim 17 rejection above) between the semiconductor chip (72) and the first supporting wall is smaller than a spaced-apart distance (D3) between the semiconductor chip and the third supporting wall, and a spaced-apart distance (D4) between the semiconductor chip and the fourth supporting wall, and wherein a spaced-apart distance (D2) between the semiconductor chip and the second supporting wall is smaller than the spaced-apart distance between the semiconductor chip and the third supporting wall (D3), and the spaced-apart distance between the semiconductor chip and the fourth supporting wall (D4). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Son into the device of Jang to add a first support wall, a second supporting wall, a third supporting wall and a fourth supporting wall to the first edge, the second edge, the third edge, and the fourth edge, respectively, with their structural relationships described in the manner described above and with their respectively distances from the semiconductor chip added in the manner as described above. The ordinary artisan would have been motivated to modify Jang in the manner set forth above for at least the purpose of using the shielding unit as a shielding unit of a camera module in a cell phone (Son ¶ [0094]-[0097] ) that uses multiple electronic components (71-74, ¶ [0096]; any of these components are analogous to the magnetic memory element since Son in ¶ [0035]-[0036] teaches a cell phone comprising memory modules ), wherein the first wall and second walls (these walls together form an L-shaped unit) of the shielding unit are unit to improve the rigidity and to reduce the mechanical stress of the shielding unit (¶ [0106]) while the third wall and fourth walls are used as grounding connections of the shielding unit (¶ [0099], ¶ [0210] ). The person of ordinary skill would also be motivated to position the respective supporting walls of the shielding unit with respect to the semiconductor device in the manner as described above for the purpose of adding more than one electronic components (72-74) to the camera units that are commonly shielded by the shielding unit (see Fig. 6 and ¶ [0160] ). Regarding claim 15, the electronic device according to claim 13, wherein the printed circuit board has a top surface (Tuttle Figs. 2-4: top surface of 20) on which the semiconductor chip and the shielding unit are mounted, the shielding unit occupies an area (area of the top surface of 20 enclosed by 33) on the top surface of the printed circuit board, the occupied area of the shielding unit ranging from a first value (value of the area of the top surface of 20 enclosed by 33 minus the area of the top surface of 20 occupied by 12, as shown in Tuttle Figs. 2-4) to a second value (the hypothetical area of the top surface of 20 occupied by 33 with the components 12 removed ), when the occupied area of the shielding unit is the first value, the shielding unit is configured to permit the semiconductor chip to be fitted thereinside (Tuttle Figs. 2-4 show the top surface area of 20 allows 12 to be fitted inside the cavity of 33), and when the occupied area of the shielding unit is the second value, the occupied area of the shielding unit is a surface area of the top surface of the printed circuit board (as shown in Figs. 2-4, the hypothetical area occupied by 33 with components 12 removed is the area of the top surface of 20). Regarding claim 16, the electronic device according to claim 13, wherein the magnetic memory element is a magnetic random access memory (Tuttle Col. 2, Lns 55-57: “integrated circuits 12 which, in turn, include internal electromagnetic structures, such as MRAM cells”). Allowable Subject Matter Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 23, Jang in view of Son teaches the electronic device according to claim 17, wherein a length of the third supporting wall (length of W3; see Examiner Fig. 1 in claim 1 rejection above) along the third edge is smaller than a length of the third edge (length of E3). However, no prior art of record was found to anticipate or render obvious: two opposite portions of the semiconductor chip are exposed from the third supporting wall. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS YAP/Assistant Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

May 23, 2023
Application Filed
Dec 01, 2025
Non-Final Rejection — §103, §112
Mar 04, 2026
Response Filed
Apr 06, 2026
Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+12.2%)
3y 3m
Median Time to Grant
Moderate
PTA Risk
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