DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-13 in the reply filed on December 12, 2025 is acknowledged. Claims 1-13 are examined infra:
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The term “substantially” in Claims 2, 5, 11, and 13 is a relative term which renders the claim indefinite. The limitation “a top surface of the mask structure is substantially coplanar with a top surface of the gate structure/contact” is not defined by these claims, the specification (¶ 0076) does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Regarding Claims 2, 5, 11, and 13, it is not known what exactly are the bounds, what are would read on 'substantially coplanar' vs not be close enough to read on that. What is the line between not substantially coplanar and being substantially coplanar?
Appropriate correction is required. These claims will be examined as best understood.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-8, and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (“Cheng”), US 20230123987.
Regarding Claim 1, Kim discloses a semiconductor device (100a; Figs. 2J, 3J-1, 3J-2; ¶ 0067), comprising:
channel layers (108; Figs. 2J, 3J-1; ¶ 0099) stacked vertically apart (Figs. 2J, 3J-1; ¶ 0032 “108 are vertically stacked to form a stacked nanostructures structure”) along a first direction (X; Fig. 2J; ¶ 0067) over a substrate (102; Fig. 3J-1; ¶ 0032);
a mask structure (107; Fig. 3J-1; ¶ 0099) disposed over and apart from the channel layers (Fig. 3J-1) along the first direction (Figs. 2J, 3J-1);
a gate structure (182, 184, 186; Fig. 3J-2; ¶ 0097-0098) laterally extending (Fig. 3J-2; ¶ 0097-0098) along a second direction (Y; Fig. 2J; ¶ 0067) perpendicular to the first direction disposed (Fig. 2J; ¶ 0067), wherein the gate structure wraps around the channel layers (Fig. 3J-2; ¶ 0092 “layers 108 are surrounded by the gate structure 186”, 0097-0098) and laterally surround the mask structure (Fig. 3J-2; ¶ 0098); and
a source/drain pattern (158; 3J-1; ¶ 0078) in contact with the channel layers (Fig. 3J-1; ¶ 0080).
Regarding Claim 2, Cheng discloses wherein a top surface of the mask structure is substantially coplanar with a top surface of the gate structure (Fig. 3J-2; ¶ 0098 “the portion of the gate dielectric layer 182 and the portion of the gate electrode layer 184 which are above the hard mask layer 107 are removed”).
Regarding Claim 6, Cheng discloses further comprising a dielectric layer (156; Fig. 3J-1; ¶ 0075) disposed over the substrate (Fig. 3J-1) and in contact with the gate structure and the source/drain pattern (Fig. 3J-1; ¶ 0075, 0092).
Regarding Claim 7. Cheng discloses a semiconductor device (100a; Figs. 2J, 3J-1, 3J-2; ¶ 0067), comprising:
first channel layers (middle 108; Figs. 2J, 3J-1; ¶ 0099) stacked along a vertical direction (Figs. 2J, 3J-1; ¶ 0032 “108 are vertically stacked to form a stacked nanostructures structure”) over a substrate (102; Fig. 3J-1; ¶ 0032), extending along a first lateral direction (X; Fig. 2J; ¶ 0067);
second channel layers stacked (rightmost 108; Figs. 2J, 3J-1; ¶ 0099) along the vertical direction (Figs. 2J, 3J-1; ¶ 0032 “108 are vertically stacked to form a stacked nanostructures structure”) over the substrate (102; Fig. 3J-1; ¶ 0032), extending along the first lateral direction (X; Fig. 2J; ¶ 0067);
a dielectric layer (156; Fig. 3J-1; ¶ 0075) disposed over the substrate (Fig. 3J-1);
first (left 182, 184, 186; Fig. 3J-2; ¶ 0097-0098) and second gate structures (right 182, 184, 186; Fig. 3J-2; ¶ 0097-0098), separately arranged (Fig. 3J-2) along a second lateral direction (Y; Fig. 2J; ¶ 0067) by the dielectric layer (Figs. 2J, 3J-1, 3J-2), and respectively extending along the second lateral direction (Y; Fig. 2J; ¶ 0067 the gate structures extend along the second lateral direction), the second lateral direction perpendicular to the first lateral direction (Fig. 2J; ¶ 0067), wherein the first gate structure wraps around the first channel layers (left side of Fig. 3J-2; ¶ 0092 “layers 108 are surrounded by the gate structure 186”, 0097-0098), and the second gate structure wraps around the second channel layers (right side of Fig. 3J-2; ¶ 0092 “layers 108 are surrounded by the gate structure 186”, 0097-0098);
a first source/drain pattern (158 between the first channel layers and the second channel layers; Fig. 3J-1; ¶ 0078) in contact with the first channel layers (Fig. 3J-1; ¶ 0080);
a second source/drain pattern (rightmost 158; Fig. 3J-1; ¶ 0078) in contact with the second channel layers (Fig. 3J-1; ¶ 0080); and
mask structures (107; Fig. 3J-1; ¶ 0099) respectively disposed over and apart from the first channel layers and the second channel layers (Fig. 3J-1), and embedded in the first gate structure and the second gate structure (Fig. 3J-2; ¶ 0098).
Regarding Claim 8, Cheng discloses wherein the first source/drain pattern and the second source/drain pattern are laterally separated from each other by the dielectric layer (Fig. 3J-1 the first source/drain pattern and the second source/drain pattern are laterally separated by the dielectric layer 156 located between the first source/drain pattern and the second source/drain pattern; ¶ 0092 “156 are between the gate structure 186 and the S/D structures 158”).
Regarding Claim 12, Cheng discloses wherein the mask structures respectively are separated apart from a topmost first channel layer (Fig. 3J-2 the first channel layer that is vertically closest to the left mask structure 107) of the first channel layers (Fig. 3J-2) and a topmost second channel layer (Fig. 3J-2 the second channel layer that is vertically closest to the right mask structure 107) of the second channel layers (Fig. 3J-2) by the first gate structure (Fig. 3J-2 left gate structure 182, 184 is located vertically between the left mask structure 107 and the topmost first channel layer) and the second gate structure (Fig. 3J-2 right gate structure 182, 184 is located vertically between the right mask structure 107 and the topmost second channel layer).
Regarding Claim 13, Cheng discloses wherein top surfaces of the mask structures are substantially coplanar with a top surface of the first gate structure (Fig. 3J-2 a top surface of first gate structure 182 and 184 are substantially coplanar with the top surface of the left mask structure 107; ¶ 0098 “the portion of the gate dielectric layer 182 and the portion of the gate electrode layer 184 which are above the hard mask layer 107 are removed”) and a top surface of the second gate structure (Fig. 3J-2 a top surface of second gate structure 182 and 184 are substantially coplanar with the top surface of the right mask structure 107; ¶ 0098 “the portion of the gate dielectric layer 182 and the portion of the gate electrode layer 184 which are above the hard mask layer 107 are removed”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (“Cheng”), US 20230123987 in view of Liaw, US 2022/0302135.
Regarding Claim 3, Cheng does not disclose further comprising a contact located right above and in contact with the source/drain pattern.
Liaw discloses further comprising a contact (260; Fig. 9D; ¶ 0041) located right above and in contact with (Fig. 9D; ¶ 0041) the source/drain pattern (230; Fig. 9D; ¶ 0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheng to have further comprising a contact located right above and in contact with the source/drain pattern, as taught by Liaw, in order to improve access to the source/drain pattern (Liaw ¶ 0041) to optimize the reliability and performance of the device (Liaw ¶ 0041).
Regarding Claim 4, Cheng does not disclose wherein the contact is in contact with a top surface of the source/drain pattern without being contact with a side surface of the source/drain pattern.
Liaw discloses wherein the contact is in contact with a top surface of the source/drain pattern (Fig. 9D; ¶ 0041 noting the etching and planarization processes) without being contact with a side surface of the source/drain pattern (Fig. 9D; ¶ 0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheng to have wherein the contact is in contact with a top surface of the source/drain pattern without being contact with a side surface of the source/drain pattern, as taught by Liaw, in order to enhance the connection to the source/drain pattern (Liaw ¶ 0041) to optimize the reliability and performance of the device (Liaw ¶ 0041).
Regarding Claim 5, as best understood (noting the ¶ 112(b) rejection supra), Cheng does not disclose wherein a top surface of the mask structure is substantially coplanar with a top surface of the contact.
Liaw discloses wherein a top surface (Fig. 9B in the Z direction) of the mask structure (250; Fig. 9B; ¶ 0039) is substantially coplanar (Fig. 9B) with a top surface (Fig. 9B in the Z direction) of the contact (260; Fig. 9B; ¶ 0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheng to have wherein a top surface of the mask structure is substantially coplanar with a top surface of the contact, as taught by Liaw, in order to facilitate optimal formation of the additional interconnection structures over the top of the mask structure and contact (Liaw ¶ 0042), thereby improving the reliability and performance of the device (Liaw, ¶ 0041).
Regarding Claim 9, Cheng does not disclose further comprising contacts respectively located right above and in contact with the first source/drain pattern and the second source/drain pattern.
Liaw discloses further comprising contacts (260; Fig. 9D; ¶ 0041) respectively located right above and in contact with (Fig. 9D; ¶ 0041) the first source/drain pattern (left 230; Fig. 9D; ¶ 0041) and the second source/drain pattern (right 230; Fig. 9D; ¶ 0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheng to have further comprising contacts respectively located right above and in contact with the first source/drain pattern and the second source/drain pattern, as taught by Liaw, in order to improve access to the source/drain pattern (Liaw ¶ 0041) to optimize the reliability and performance of the device (Liaw ¶ 0041).
Regarding Claim 10, Cheng does not disclose wherein the dielectric layer is located between the contacts.
Liaw discloses wherein the dielectric layer (232; Fig. 9D; ¶ 0031 “interlayer dielectric (ILD) layer 232”) is located between the contacts (Fig. 9D dielectric layer 232 is located between contacts 260).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheng to have wherein the dielectric layer is located between the contacts, as taught by Liaw, in order to electrically isolate the contacts (Liaw ¶ 0031) to optimize the reliability and performance of the device (Liaw ¶ 0041).
Regarding Claim 11, as best understood (noting the ¶ 112(b) rejection supra), Cheng does not disclose wherein a top surface of the mask structure is substantially coplanar with a top surface of the contact.
Liaw discloses wherein a top surface (Fig. 9B in the Z direction) of the mask structure (250; Fig. 9B; ¶ 0039) is substantially coplanar (Fig. 9B) with a top surface (Fig. 9B in the Z direction) of the contact (260; Fig. 9B; ¶ 0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheng to have wherein a top surface of the mask structure is substantially coplanar with a top surface of the contact, as taught by Liaw, in order to facilitate optimal formation of the additional interconnection structures over the top of the mask structure and contact (Liaw ¶ 0042), thereby improving the reliability and performance of the device (Liaw, ¶ 0041).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang et al., US 2023/0066323, discloses a semiconductor device with a mask structure over channel layers, a gate structure wrapped around the channel layers, and a source/drain pattern in contact with the channel layers. Kao et al., US 20230061815, discloses a semiconductor structure with a mask structure over channel layers, a gate structure, and a source/drain patten in contact with the channel layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rose Keagy whose telephone number is (571) 270-3455. The examiner can normally be reached Mon-Fri. 8am-5pm (CT).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818