DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species I (Figs. 1A-1C) on which claims 1-20 are readable in the reply filed on 08/25/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9978751 (Wang et al) in view of US 20120043612 (Baldwin).
Concerning claim 1, Wang discloses a method of making a semiconductor device (Figs. 3 and 4A), the method comprising: forming an active device region (310) in a substrate (410); forming a first transistor in the active device region, the first transistor comprising a first channel region a first source region and a first drain region (Fig. 4A and col. 6 lines 15-45); and forming a guard ring region (320 and 330) outside the active device region (Fig. 4A); forming a second transistor in the guard ring region, the second transistor comprising a second channel region a second source region and a second drain region (col. 6 lines 15-45).
Wang does not disclose wherein the second channel region comprises a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region. However, Baldwin discloses a semiconductor device (Fig. 3a, [0026]-[0029], and [0042]) that includes an active area (26) with transistors (30p, 30n, and 31p) formed in the active area and a guard region (28) formed outside the active area and surrounding it. Baldwin discloses each of transistors have source and drain regions of eSiGe structures, despite guard ring 28 of single-crystal silicon (and thus not eSiGe). This construction of guard ring 28 as doped single-crystal silicon carries out the desired function of a guard ring in decoupling noise, absorbing electrostatic discharge energy, and capturing ionic contamination, etc., without adversely affecting circuit performance. It is recognized, according to this invention, that enhancement of carrier mobility in the silicon adjacent to guard ring does not provide significant benefit to the function of guard ring, certainly not to the extent that such enhancement assists transistor drive. In addition, guard ring 28 may be constructed with less than full p+ dopant concentration of the eSiGe source and drain regions of transistors 30p, 31p, as its function as a guard structure is not strongly dependent on its dopant concentration. As such, the construction of guard ring 28 without use of eSiGe technology does not degrade circuit performance. Meanwhile, transistors 30p, 31p within the bounds of guard ring 28 are constructed to include eSiGe source and drain regions, and thus attain the benefit of the enhanced carrier mobility in the channel provided by that technology and by realizing guard ring as a doped region at the surface of the single-crystal silicon, the vulnerability of the integrated circuit to defects caused by concentration of crystal lattice strain at the corners of guard ring is eliminated in this arrangement. No additional chip area is required by this improved construction and neither circuit functionality nor guard ring utility is compromised by this construction. Additionally the construction is completed in the conventional manner, by way of the formation and patterning of the appropriate overlying metal conductors, interlevel dielectric or insulator films, and contacts and vias to provide electrical connection among the overlying conductors, and between those conductors and active or conductive elements including guard ring 28, source and drain regions of transistor 30p as formed in eSiGe structures 45, gate element 38, and the like. ([0028]-0029] and [0042]). As disclosed in applicant’s specification in [0033] the thermal conductivity of the Si material guard region has a higher thermal conductivity than the SiGe material of the active region. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention such that the guard region (second channel region) comprises a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region as disclosed by Baldwin in order to attain the benefit of enhanced carrier mobility in the active region and still attain the guard region benefits of decoupling external noise from reaching the protected devices interior of the guard ring and providing a large junction area for purposes of dissipating energy from electrostatic discharge (ESD) events.
Continuing to claim 2, Wang in view of Baldwin discloses further comprises electrically connecting the first source region to the second source region (Baldwin [0042]).
Considering claim 3, Wang in view of Baldwin discloses wherein forming the first transistor comprises forming a fin field effect transistor (FinFET) (Wang col. 6 lines 15-45).
Referring to claim 4, Wang in view of Baldwin discloses further comprising forming a source contact structure over the first source region and the second source region (Baldwin [0042]).
Regarding claim 5, Wang in view of Baldwin discloses wherein forming the source contact structure comprises forming the source contact structure as a continuous layer (Baldwin [0042]).
Pertaining to claim 6, Wang in view of Baldwin discloses further comprising forming a first gate structure over the first channel region (Wang col. 6 lines 15-45).
As to claim 7, Wang in view of Baldwin discloses further comprising forming a second gate structure over the second channel region (Wang col. 6 lines 15-45).
Concerning claim 8, Wang in view of Baldwin discloses wherein forming the second transistor comprises forming the second transistor spaced from the first transistor in a first direction parallel to a top surface of the substrate (Wang Fig. 3 and 4A).
Continuing to claim 9, Wang in view of Baldwin discloses wherein forming the second transistor comprises forming the second transistor (Wang Fig. 3).
Wang in view of Baldwin does not disclose it comprises forming the second source region offset from the first source region in a second direction, and the second direction is perpendicular to the first direction. However, Baldwin discloses a source region configuration in which the second source (31p) is formed offset from the first source region (30p) (Fig. 3a). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See MPEP 2144.04 IV B. Therefore absent evidence that the particular configuration is significant, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Wang in view of the teachings of Baldwin.
Considering claim 10, Wang in view of Baldwin discloses wherein forming the second transistor comprises forming the second source region aligned with the first channel region in the first direction (Wang Fig. 3 and 4A).
Referring to claim 11, Wang discloses a method of forming a semiconductor device, the method comprising (Figs. 3 and 4A): forming a first transistor in an active device region, wherein the first transistor comprises a first channel region (Figs. 3 and 4A and col. 6 lines 15-45), forming a second transistor in a guard ring region, wherein the second transistor comprises a second channel region (Figs. 3 and 4A and col. 6 lines 15-45).
Wang does not disclose a thermal conductivity of the second channel region is greater than a thermal conductivity of the first channel region. However, Baldwin discloses a semiconductor device (Fig. 3a, [0026]-[0029], and [0042]) that includes an active area (26) with transistors (30p, 30n, and 31p) formed in the active area and a guard region (28) formed outside the active area and surrounding it. Baldwin discloses each of transistors have source and drain regions of eSiGe structures, despite guard ring 28 of single-crystal silicon (and thus not eSiGe). This construction of guard ring 28 as doped single-crystal silicon carries out the desired function of a guard ring in decoupling noise, absorbing electrostatic discharge energy, and capturing ionic contamination, etc., without adversely affecting circuit performance. It is recognized, according to this invention, that enhancement of carrier mobility in the silicon adjacent to guard ring does not provide significant benefit to the function of guard ring, certainly not to the extent that such enhancement assists transistor drive. In addition, guard ring 28 may be constructed with less than full p+ dopant concentration of the eSiGe source and drain regions of transistors 30p, 31p, as its function as a guard structure is not strongly dependent on its dopant concentration. As such, the construction of guard ring 28 without use of eSiGe technology does not degrade circuit performance. Meanwhile, transistors 30p, 31p within the bounds of guard ring 28 are constructed to include eSiGe source and drain regions, and thus attain the benefit of the enhanced carrier mobility in the channel provided by that technology and by realizing guard ring as a doped region at the surface of the single-crystal silicon, the vulnerability of the integrated circuit to defects caused by concentration of crystal lattice strain at the corners of guard ring is eliminated in this arrangement. No additional chip area is required by this improved construction and neither circuit functionality nor guard ring utility is compromised by this construction. Additionally the construction is completed in the conventional manner, by way of the formation and patterning of the appropriate overlying metal conductors, interlevel dielectric or insulator films, and contacts and vias to provide electrical connection among the overlying conductors, and between those conductors and active or conductive elements including guard ring 28, source and drain regions of transistor 30p as formed in eSiGe structures 45, gate element 38, and the like. ([0028]-0029] and [0042]). As disclosed in applicant’s specification in [0033] the thermal conductivity of the Si material guard region has a higher thermal conductivity than the SiGe material of the active region. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention such that the guard region (second channel region) comprises a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region as disclosed by Baldwin in order to attain the benefit of enhanced carrier mobility in the active region and still attain the guard region benefits of decoupling external noise from reaching the protected devices interior of the guard ring and providing a large junction area for purposes of dissipating energy from electrostatic discharge (ESD) events.
Regarding claim 12, Wang in view of Baldwin discloses wherein forming the first transistor comprises doping the first channel region to have a first dopant concentration, and forming the second transistor comprises doping the second channel region to have a second dopant concentration less than the first dopant concentration (Baldwin [0027]).
Pertaining to claim 13, Wang in view of Baldwin discloses wherein forming the first transistor comprises forming the first channel region comprising SiGe (Baldwin [0028]).
As to claim 14, Wang in view of Baldwin discloses wherein forming the second transistor comprises forming the second channel region comprising Si (Baldwin [0028]).
Concerning claim 15, Wang in view of Baldwin discloses wherein forming the second transistor comprises forming an inactive device (Wang col. 5 lines 34-59).
Claim(s) 16, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160290873 (Horng et al) in view of US 8823610 (Miyazawa).
Considering claim 16, Horng discloses a method of making a semiconductor device, the method comprising (Fig. 1): forming an active device region (102) in a substrate (106) (Fig. 1 and [0016]); forming a transistor in the active device region, the transistor comprising a channel region and a source/drain (S/D) region ([0025]); defining a second device region (104) in the substrate ([0029]); forming a device in the passive second device region ([0029]); and forming a contact structure (158) overlying the S/D region ([0017]); and forming an interconnect layer (154) electrically coupling the contact structure and a first terminal of the device, wherein a second terminal of the device is floating ([0019] and [0031]).
Horng does not disclose a channel region is between the first terminal and the second terminal. However Miyazawa discloses a semiconductor device configuration in which a transistor us formed in an active region and a second device is formed in a second device region with a first and second terminal with a channel region between the first and second terminal (Claim 10). Miyazawa discloses that such configuration is capable of compensating characteristics of transistors and enhance the flexibility of operational design by compensating Vth compensation and by applying a reverse bias in one operation process in such an electronic device (col. 1 lines 38-43). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Horng in view of Miyazawa in order to achieve the advantages disclosed by Miyazawa for such configuration.
Continuing to claim 19, Horng in view of Miyazawa discloses wherein forming the device comprises forming the device on an opposite side of the S/D region from the channel region (Fig. 1).
Considering claim 20, Horng in view of Miyazawa discloses forming a second device on an opposite side of the transistor from the device; and electrically connecting the S/D region to the second device (Fig. 1).
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160290873 (Horng et al) in view of US 8823610 (Miyazawa), as applied to claim 16 above, and further in view of US 20120043612 (Baldwin).
Continuing to claim 17, Horng in view of Miyazawa discloses forming the device.
Horng in view of Miyazawa does not disclose forming a doped well in the second device region; and forming a highly doped well in the doped well. However, Baldwin discloses a semiconductor device (Fig. 3a, [0026]-[0029], and [0042]) that includes an active area (26) with transistors (30p, 30n, and 31p) formed in the active area and a guard region (28) formed outside the active area and surrounding it. Baldwin discloses each of transistors have source and drain regions of eSiGe structures, despite guard ring 28 of single-crystal silicon (and thus not eSiGe). This construction of guard ring 28 as doped single-crystal silicon carries out the desired function of a guard ring in decoupling noise, absorbing electrostatic discharge energy, and capturing ionic contamination, etc., without adversely affecting circuit performance. It is recognized, according to this invention, that enhancement of carrier mobility in the silicon adjacent to guard ring does not provide significant benefit to the function of guard ring, certainly not to the extent that such enhancement assists transistor drive. In addition, guard ring 28 may be constructed with less than full p+ dopant concentration of the eSiGe source and drain regions of transistors 30p, 31p, as its function as a guard structure is not strongly dependent on its dopant concentration. As such, the construction of guard ring 28 without use of eSiGe technology does not degrade circuit performance. Meanwhile, transistors 30p, 31p within the bounds of guard ring 28 are constructed to include eSiGe source and drain regions, and thus attain the benefit of the enhanced carrier mobility in the channel provided by that technology and by realizing guard ring as a doped region at the surface of the single-crystal silicon, the vulnerability of the integrated circuit to defects caused by concentration of crystal lattice strain at the corners of guard ring is eliminated in this arrangement. No additional chip area is required by this improved construction and neither circuit functionality nor guard ring utility is compromised by this construction. Additionally the construction is completed in the conventional manner, by way of the formation and patterning of the appropriate overlying metal conductors, interlevel dielectric or insulator films, and contacts and vias to provide electrical connection among the overlying conductors, and between those conductors and active or conductive elements including guard ring 28, source and drain regions of transistor 30p as formed in eSiGe structures 45, gate element 38, and the like. ([0028]-0029] and [0042]). As disclosed in applicant’s specification in [0033] the thermal conductivity of the Si material guard region has a higher thermal conductivity than the SiGe material of the active region. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention such that the guard region (second channel region) a doped well and forming a highly doped well in the doped well as disclosed by Baldwin in order to attain the benefit of enhanced carrier mobility in the active region and still attain the guard region benefits of decoupling external noise from reaching the protected devices interior of the guard ring and providing a large junction area for purposes of dissipating energy from electrostatic discharge (ESD) events.
Referring to claim 18, Horng in view of Miyazawa and Baldwin discloses wherein forming the interconnect layer comprises electrically connecting the contact structure to the highly doped well (Horng [0019] and [0031] and Baldwin [0028]-[0029]).
Response to Arguments
Applicant's arguments filed 02/25/26 have been fully considered but they are not persuasive. Applicant argues that Baldwin explicitly states that the asserted guard ring is "located within" the asserted active region, in direct contrast to the recited claim language. Further, Baldwin fails to teach or suggest any transistors within element 28. Figure 3A of Baldwin includes only contacts 35 within element 28. Thus, Baldwin fails to teach or suggest the existence of a second channel to permit a comparison of the thermal conductivities. The examiner disagrees. As can be seen in Fig. 3b the active area has a defined region and the region 28 is clearly shown to be formed outside of this region and surrounding it. Therefore the arguments are not found to be persuasive. Additionally, Baldwin discloses in this embodiment of the invention (Figs. 3a -3c), as is typical for eSiGe p-channel MOS transistor formation, an additional source/drain implant is also performed to increase the dopant concentration of these eventual source/drain regions. Therefore the examiner believes that the prior art has established that the channel region is disclosed as a SiGe region which is different from the Si regions of the active region. Therefore the arguments are not found to be persuasive and the rejection stands.
Applicant’s arguments, see page 6, filed 02/25/26, with respect to the rejection(s) of claim(s) 16, 19, and 20 under 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 8823610 (Miyazawa).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 05/31/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
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