DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/14/2025.
Applicant’s election without traverse of Invention I, Method Embodiment 2 in the reply filed on 10/14/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 32 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. (US 2022/0113199 A1, hereinafter Su ‘199).
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With respect to Claim 32 Su ‘199 discloses a method for manufacturing a semiconductor structure (Fig 1-9 of Su ‘199), comprising:
forming a first stack (leftmost stack, as shown in annotated Fig 5 of Su’199, Para [0019], hereinafter ST1) and a second stack (second stack, as shown in annotated Fig 5 of Su’199, Para [0019], hereinafter ST2) on a base structure (214, Fig 5 of Su ‘199, Para [0036]), a middle recess (Fig 1-2 and Para [0022] of Su ‘199 disclose recesses formed for epitaxial regions on sides of stack, middle recess hereby MR and disclosed in annotated Fig 5 of Su ‘199) being formed between the first stack (ST1) and the second stack (ST2), a left recess (Fig 1-2 and Para [0022] of Su ‘199 disclose recesses formed for epitaxial regions on sides of stack, left recess hereby LR and disclosed in annotated Fig 5 of Su ‘199) being formed at a left side (disclosed in annotated Fig 5 of Su ‘199) of the first stack (ST1), a right recess (Fig 1-2 and Para [0022] of Su ‘199 disclose recesses formed for epitaxial regions on sides of stack, right recess hereby RR and disclosed in annotated Fig 5 of Su ‘199) being formed at a right side (disclosed in annotated Fig 5 of Su ‘199) of the second stack (ST2), each of the first stack (ST1) and the second stack (ST2) including semiconductor regions (208, Fig 4 of Su ‘199, Para [0020]) and dielectric regions (206, Fig 4 of Su ‘199, Para [0021]) which are disposed to alternate (disclosed in Fig 4 of Su ‘199) with the semiconductor regions (208) in a first direction (Z direction as shown Fig 4);
growing two first epitaxial portions (222 and 224, Fig 4, Para [0029]) respectively in the left recess (LR) and the right recess(RR)(regions disclosed in annotated Fig 5 of Su ‘199); and
growing a second epitaxial portion (232, Fig 5 of Su ‘199, Para [0029]) in the middle recess (MR)(region disclosed in annotated Fig 5 of Su ‘199), the second epitaxial portion (232) having a conductivity type (n-type, Para [0029]) opposite to a conductivity type (p-type, Para [0029]) of the two first epitaxial portions (222 and 224)(conductivity types disclosed in Para [0029]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2018/0261593 A1, hereinafter Cheng ‘593) in view of Su ‘199 in further view of Cheng et al. (US 2018/0102359 A1, hereinafter Cheng ‘359) in view of the following arguments.
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With respect to Claim 15 Cheng ‘593 discloses a method for manufacturing a semiconductor structure (Fig 1-12), comprising:
forming a base structure (101/102, Fig 1, Para [[0032 and 0033]);
But Cheng ;593 fails to explicitly disclose forming a first portion on the base structure, the first portion being made of a first semiconductor material; forming a second portion on the base structure and spaced apart from the first portion in a first direction, the second portion being made of a second semiconductor material which has a conductivity type opposite to a conductivity type of the first semiconductor material; and forming a first stack on the base structure and between the first portion and the second portion, the first stack including first semiconductor regions spaced apart from each other in a second direction different from the first direction, and first dielectric regions disposed to alternate with the first semiconductor regions in the second direction such that each of the first semiconductor regions and the first dielectric regions extends between the first portion and the second portion, the first semiconductor regions having a dopant concentration which is lower than a dopant concentration of each of the first portion and a dopant concentration of the second portion.
Nevertheless, in a related endeavor (Fig 1-9 of Su ‘199), Su ‘199 teaches forming a first portion (222, Fig 5 of Su ‘199, Para [0029]) on the base structure (214, Fig 5 of Su ‘199, Para [0036]), the first portion being (222) made of a first semiconductor material (SiGe, Fig 5 of Su ‘199, Para [0022]);
forming a second portion (232, Fig 5 of Su ‘199, Para [0029]) on the base structure (214) and spaced apart (disclosed in Fig 5 of Su ‘199) from the first portion (222) in a first direction (X direction as shown in Fig 5 of Su ‘199), the second portion (232) being made of a second semiconductor material (silicon, Fig 5 of Su ‘199, Para [0022]) which has a conductivity type (n-type, Para [0029]) opposite to a conductivity type (p-type, Para [0029]) of the first semiconductor material (222); and
forming a first stack (leftmost stack, as shown in annotated Fig 5 of Su’199, Para [0019], hereinafter ST1) on the base structure (214) and between (disclosed in annotated Fig 5 of Su ‘199) the first portion (222) and the second portion (232), the first stack (ST1) including first semiconductor regions (208, Fig 4 of Su ‘199, Para [0020]) spaced apart from each other (arrangement disclosed in Fig 4 of Su ‘199) in a second direction (Z direction as shown in Fig 5 of Su ‘199) different from the first direction (X direction), and first dielectric regions (206, Fig 4 of Su ‘199, Para [0021]) disposed to alternate (disclosed in Fig 4 of Su ‘199) with the first semiconductor regions (208) in the second direction (Z direction) such that each of the first semiconductor regions (208) and the first dielectric regions (206) extends between (arrangement disclosed in Fig 4 of Su ‘199) the first portion (222) and the second portion (232),
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Su ‘199’s forming a first portion on the base structure, the first portion being made of a first semiconductor material; forming a second portion on the base structure and spaced apart from the first portion in a first direction, the second portion being made of a second semiconductor material which has a conductivity type opposite to a conductivity type of the first semiconductor material; and forming a first stack on the base structure and between the first portion and the second portion, the first stack including first semiconductor regions spaced apart from each other in a second direction different from the first direction, and first dielectric regions disposed to alternate with the first semiconductor regions in the second direction such that each of the first semiconductor regions and the first dielectric regions extends between the first portion and the second portion, the first semiconductor regions having a dopant concentration which is lower than a dopant concentration of each of the first portion and a dopant concentration of the second portion into Cheng ‘593’s method. Cheng ‘593 teaches (Para [0005 and 0006]) that both diodes, specifically a BJT, and FET devices are made on a single wafer that contains nanosheet gate stack structures with n and p doped regions between the gate stacks. Su ‘199 teaches another method for creating a BJT diode using gate stack structures with n and p dope regions between the gate stacks. The person having ordinary skill in the art would recognize that the method to create a BJT device of Su ‘199 and the method to create the BJT structure of Chen ‘359 are alternative methods to create a BJT and therefore that there will not be any unexpected results in substituting one BJT for another BJT. Further the person having ordinary skill in the art would be motivated to modify Cheng ‘593 in the manner set forth above, at least, because, as disclosed in Para [0002] Su ‘199’s method of creating a BJT can “improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs)”.
As incorporated, the method of Su ‘199 would be used to create the BJT of Cheng ‘593 on the substrate (101/102).
But Cheng ‘593 as modified by Su ‘199 fails to explicitly disclose the first semiconductor regions having a dopant concentration which is lower than a dopant concentration of each of the first portion and a dopant concentration of the second portion.
Nevertheless, in a related endeavor (Fig 1-9 of Cheng ‘359), Cheng ‘359 teaches the first semiconductor regions (402, Fig 7 of Cheng ‘359, Para [0032]) having a dopant concentration (doping concentration of 2E18cm-3, Para [0032]) which is lower than a dopant concentration (doping concentration of 2E21cm-3, Para [0032]) of each of the first portion (left S/D, Fig 7 of Cheng ‘359, Para [0032]) and a dopant concentration of the second portion (right S/D, Fig 7 of Cheng ‘359, Para [0032])(Para [0032] teaches first semiconductor regions doping concentration of 2E18cm-3 and S/D regions having a doping concentration of 2E21cm-3).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Cheng ‘359’s the first semiconductor regions having a dopant concentration which is lower than a dopant concentration of each of the first portion and a dopant concentration of the second portion into Cheng ‘593 as modified by Su ‘199’s method. Cheng ‘593 teaches a diode and transistor structure and that the semiconductor regions should be doped but is silent as to the specific concentrations. Cheng ‘359 also teaches a diode and transistor structure, that the semiconductor regions should be doped and provides concentrations for the doping of those semiconductor regions. Therefore one using Cheng ‘593 would be motivated to look for the diode/transistor doping concentrations at the current level of skill in the art. Cheng ‘359 provides, in an analogous structure to Cheng ‘593, doping concentrations for the semiconductor regions. So, the ordinary artisan would have been motivated to modify Cheng ‘593 as modified by Su ‘199 in the manner set forth above, at least, because Cheng ‘359’s teaching of semiconductor doping concentrations would simplify the manufacturing process by using known concentrations to make the diode/transistor structure.
As incorporated, the method of creating doping concentrations of the first semiconductor region being lower than the first and second portions taught by Cheng ‘359 would be used in the first semiconductor region (208), the first portion (222) and second portion (232) of Cheng ‘593 as modified by Su ‘199.
With respect to Claim 16 Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359 discloses all limitation of the method as claimed in claim 15, and Su ‘199 discloses further comprising:
forming a third portion (224, Fig 5 of Su ‘199, Para [0023]) on the base structure (214) such that the second portion (232) is disposed between and spaced apart (232 disposed between and spaced apart from 222 and 224 disclosed in Fig 5 of Su ‘199) from the first portion (222) and the third portion (224) in the first direction (X direction as shown in Fig 5 of Su ‘199), the third portion (224) being made of a third semiconductor material (SiGe, Fig 5 of Su ‘199, Para [0022]) which has a conductivity type (p-type) the same as the conductivity type (p-type) of the first semiconductor material (222)(Para [0023 discloses 222 and 224 as having same conductivity type); and
forming a second stack (second stack, as shown in annotated Fig 5 of Su’199, Para [0019], hereinafter ST2) on the base structure (214) and between the second portion (232) and the third portion (224), the second stack (ST2) including of second semiconductor regions (208 of ST2, Fig 4 of Su ‘199, Para [0020]) spaced apart from each other (arrangement disclosed in Fig 4 of Su ‘199) in the second direction (Z direction as shown in Fig 5 of Su ‘199), and second dielectric regions (206 of ST2, Fig 4 of Su ‘199, Para [0021]) disposed to alternate (arrangement disclosed in Fig 4 of Su ‘199) with the second semiconductor regions (208 of ST2) in the second direction (Z direction) such that each of the second semiconductor regions (208 of ST2) and the second dielectric regions (206 of ST2) extends between (disclosed in Fig 4 of Su ‘199) the second portion (232) and the third portion (224),
But Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359 the second semiconductor regions having a dopant concentration which is lower than the dopant concentration of the second portion and a dopant concentration of the third portion.
Cheng ‘359 teaches in (Fig 1-9 of Cheng ‘359), semiconductor regions (402, Fig 7 of Cheng ‘359, Para [0032]) having a dopant concentration (doping concentration of 2E18-3, Para [0032]) which is lower than a dopant concentration (doping concentration of 2E21-3, Para [0032]) of each of the first portion (left S/D, Fig 7 of Cheng ‘359, Para [0032]) and a dopant concentration of the second portion (right S/D, Fig 7 of Cheng ‘359, Para [0032])(Para [0032] teaches first semiconductor regions doping concentration of 2E18cm-3 and S/D regions having a doping concentration of 2E21cm-3).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Cheng ‘359’s the semiconductor regions having a dopant concentration which is lower than a dopant concentration of each of the first portion and a dopant concentration of the second portion into Cheng ‘593 as modified by Su ‘199’s method. Cheng ‘593 teaches a diode and transistor structure and that the semiconductor regions should be doped but is silent as to the specific concentrations. Cheng ‘359 also teaches a diode and transistor structure, that the semiconductor regions should be doped and provides concentrations for the doping of those semiconductor regions. Therefore one using Cheng ‘593 would be motivated to look for the diode/transistor doping concentrations at the current level of skill in the art. Cheng ‘359 provides, in an analogous structure to Cheng ‘593, doping concentrations for the semiconductor regions. So, the ordinary artisan would have been motivated to modify Cheng ‘593 as modified by Su ‘199 in the manner set forth above, at least, because Cheng ‘359’s teaching of semiconductor doping concentrations would simplify the manufacturing process by using known concentrations to make the diode/transistor structure.
As incorporated, the method of creating doping concentrations of the semiconductor region being lower than the epitaxial portions of a diode as taught by Cheng ‘359 would be used in the second semiconductor region (208 of ST2), the second portion (232) and third portion (224) of Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359.
With respect to Claim 18 Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359 discloses all limitations of the method as claimed in claim 16, and Su ‘199 discloses further comprising forming two dummy gate structures (first two gate structures shown in Fig 1 and Para [0021] disclose dummy gate structures are formed prior to the formation of gate structures 210 shown in Fig 3 of Su ‘199. Further Fig 3 of Su ‘199 discloses two gate structures, here in DG1 and DG2) over the first stack (ST1) and the second stack (ST2)(Para [0021] discloses dummy gate areas formed over the stacks), respectively, the two dummy gate structures (DG1 and DG2) being each elongated (disclosed in Fig 3 of Su ‘199) in a third direction (Y direction as shown in Fig 3 of Su ‘199) different from the first direction (X direction) and the second direction (Z direction).
With respect to Claim 19 Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359 discloses all limitations of the method as claimed in claim 15, and Su ‘199 further discloses wherein formation of the first stack (ST1) includes
forming a preformed stack (Fig 1 and Para [0019] of Su ‘199 disclose a preformed stack) including the first semiconductor regions (208) and preformed semiconductor regions (SiGe regions disclosed in Para [0019]) disposed to alternate (disclosed in Para [0019]) with the first semiconductor regions (208) in the second direction (Z direction as shown in Fig 4 of Su ‘199, layers 206 occupy the space where the preformed regions were), the preformed semiconductor regions (SiGe regions disclosed in Para [0019]) being made of a material different from a material (Para [0019] of Su ‘199 discloses preformed sacrificial layers as SiGe) of the first semiconductor regions (208)(Para [0020] disclose 208 as silicon), and
replacing the preformed semiconductor regions (SiGe regions disclosed in Para [0019]) with the first dielectric regions (206)(disclosed in Fig 1 and Para [0019-0020] of Su ‘199), respectively.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng ‘593 in view of Su ‘199, in view of Cheng ‘359 and in further view of Zang et al. (US 9,847,391 B1, hereinafter Zang ‘391), in view of the following arguments.
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With respect to Claim 17 Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359 discloses all limitations of the method as claimed in claim 16, but Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359 fails to explicitly disclose further comprising forming three isolation portions, each of which is disposed between the base structure and a corresponding one of the first portion, the second portion and the third portion, and each of which is configured to entirely separate the corresponding one of the first portion, the second portion and the third portion from the base structure.
Nevertheless, in a related endeavor (Fig 1-8 of Zang ‘391), Zang ‘391 teaches further comprising forming three isolation portions (36, Fig 8 of Zang ‘391, Col 4, Lines 40-43)(Fig 8 shows two regions but Col 7, Lines 13-25 disclose the method is for a wafer of chips, therefore additional isolation portions are present), each of which is disposed between the base structure (10/11/12/13/21/14, Fig 8 of Zang ‘391, Col 7, Lines 4-12) and a corresponding one of the first portion (left 40, as shown on annotated Fig 8 of Zang ‘391, Col 6, Line 11), the second portion (second 40 as shown on annotated Fig 8 of Zang ‘391) and the third portion (third 40) (Fig 8 shows two portions but Col 7, Lines 13-25 disclose the method is for a wafer of chips, therefore additional portions are present), and each of which is configured to entirely separate (Fig 8 and Col 6, Lines 10-11 disclose isolation portion 36 under each epitaxial portion) the corresponding one of the first portion (left 40), the second portion (second 40) and the third portion (third 40) from the base structure (10/11/12/13/21/14).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Zang ‘391’s teaching of forming three isolation portions, each of which is disposed between the base structure and a corresponding one of the first portion, the second portion and the third portion, and each of which is configured to entirely separate the corresponding one of the first portion, the second portion and the third portion from the base structure into Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359’s method. The ordinary artisan would have been motivated to modify Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359 in the manner set forth above, at least, because as taught by Zang ‘391 in Col 6, Lines 10-12, the isolation regions interrupt the continuity of the p-n junction which one of ordinary skill in the art would recognize that providing isolation regions between the conductive areas would reduce parasitic capacitance.
As incorporated, the method of an isolation region under each epitaxial portion as taught by Zang ‘391 would be used in under the portions (222, 232, 224) of Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359.
Claims 21-25 and 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng ‘593 in view of Su ‘199 in view of Zang ‘391, in view of the following arguments.
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With respect to Claim 21 Cheng ‘593 discloses a method for manufacturing a semiconductor structure (Fig 1-12), comprising:
forming a first patterned structure (207, Fig 12, Para [0038]) and a second patterned structure (206, Fig 12, Para [0038]) respectively on a first part (area of 207 as shown in Fig 12) and a second part (area of 206 as shown in Fig 12) of a base structure (101/102, Fig 12, Para [0032 and 0033]), each of the second patterned structure (206) including
a stack (203, Fig 2, Para [0038]) including semiconductor regions (105, Fig 2, Para [0034]) and regions (104, Fig 3, Para [0034]) which are disposed to alternate (disclosed in Fig 11) with the semiconductor regions (105) in a first direction (first direction shown in annotated Fig 11 of Cheng ‘593), and
the two source/drain portions (504) having a conductivity type (n-type, Para [0044]) the same as the conductivity type of the first epitaxial portion (1001, Fig 10, Para [0055] discloses 1001 as n-type).
But Cheng ‘593 fails to explicitly disclose the second patterned structure stack including a dielectric region and the first patterned structure including semiconductor regions and dielectric regions which are disposed to alternate with the semiconductor regions in a first direction, a first recess and a second recess which are respectively disposed at two opposite sides of the stack in a second direction different from the first direction; growing a first epitaxial portion in the first recess of the first patterned structure; growing a second epitaxial portion in the second recess of the first patterned structure, the second epitaxial portion having a conductivity type opposite to a conductivity type of the first epitaxial portion; and
Nevertheless, in a related endeavor (Fig 1-9 of Su ‘199), Su ‘199 teaches a dielectric region (206, Fig 4 of Su ‘199, Para [0021]) in a gate stack (206/208, Fig 4 of Su ‘199, Para [0020]) and the first patterned structure (1000, Fig 5 of Su ‘199, Para [0029]) including semiconductor regions (208, Fig 4 of Su ‘199, Para [0020] and dielectric regions (206, Fig 4 of Su ‘199, Para [0021]) which are disposed to alternate with the semiconductor regions (208) in a first direction (X direction as shown in Fig 5 of Su ‘199) and
a first recess and a second recess (Fig 1-2 and Para [0022] of Su ‘199 disclose recesses formed for epitaxial regions on sides of stack, hereby FR and SR respectively) which are respectively disposed at two opposite sides (disclosed in Fig 4 of Su ‘199) of the stack (206/208, Fig 4 of Su ‘199, Para [0022]) in a second direction (Z direction as shown in Fig 4 of Su ‘199) different from the first direction (X direction as shown in Fig 4 of Su ‘199);
growing a first epitaxial portion (222, Fig 5 of Su ‘199, Para [0029]) in the first recess (FR) of the first patterned structure (1000)(disclosed in Fig 4 of Su ‘199);
growing a second epitaxial portion (232, Fig 5 of Su ‘199, Para [0029]) in the second recess (SR) of the first patterned structure (1000), the second epitaxial portion (232) having a conductivity type (n-type, Para [0029]) opposite to a conductivity type (p-type, Para [0029]) of the first epitaxial portion (222).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Su ‘199’s the second patterned structure stack including a dielectric region and the first patterned structure including semiconductor regions and dielectric regions which are disposed to alternate with the semiconductor regions in a first direction, a first recess and a second recess which are respectively disposed at two opposite sides of the stack in a second direction different from the first direction; growing a first epitaxial portion in the first recess of the first patterned structure; growing a second epitaxial portion in the second recess of the first patterned structure, the second epitaxial portion having a conductivity type opposite to a conductivity type of the first epitaxial portion into Cheng ‘593’s method. Cheng ‘593 teaches (Para [0005 and 0006]) that both diodes, specifically a BJT, and FET devices are made on a single wafer that contains nanosheet gate stack structures with n and p doped regions between the gate stacks. Su ‘199 teaches another method for creating a BJT diode using gate stack structures with n and p dope regions between the gate stacks. The person having ordinary skill in the art would recognize that the method to create a BJT device of Su ‘199 and the method to create the BJT structure of Chen ‘359 are alternative methods to create a BJT and therefore that there will not be any unexpected results in substituting one BJT for another BJT. Further the person having ordinary skill in the art would be motivated to modify Cheng ‘593 in the manner set forth above, at least, because, as disclosed in Para [0002] Su ‘199’s method of creating a BJT can “improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs)”. The person of ordinary skill in the art would be further motivated to modify Cheng ‘593 to include the second patterned structure stack including a dielectric region as the dielectric region would provide electrical insulation between the semiconductor regions of the stack which will improve electrical performance.
As incorporated, the method of Su ‘199 of the first patterned structure (1000), as described above would be used to create the BJT of Cheng ‘593. And the dielectric regions (206) of Su ‘199 would be incorporated in the first stack (203) of Cheng ‘593.
But Cheng ‘593 as modified by Su ‘199 fails to explicitly disclose the second patterned structure including a first recess and a second recess which are respectively disposed at two opposite sides of the stack in a second direction different from the first direction; and growing two source/drain portions respectively in the first recess and the second recess of the second patterned structure.
Nevertheless, in a related endeavor (Fig 1-8 of Zang ‘391), Zang ‘391 teaches the second patterned structure (50, Fig 5 of Zang ‘391, Col 4, Line 56) including a first recess (left trench 32, Fig 3 of Zang ‘391, Col 4, Lines 17-18) and a second recess (second trench 32, Fig 3 of Zang ‘391, Col 4, Lines 17-18) which are respectively disposed at two opposite sides of the stack (stack of 16/18, Fig 3 of Zang ‘391, Col 3, Lines 29-31) in a second direction (second direction shown in annotated Fig 3 of Zang ‘391) different from the first direction (first direction shown in annotated Fig 3 of Zang ‘391); and growing two source/drain portions (left 40 and right 40, Fig 5 of Zang ‘391, Col 4, Line 56) respectively in the first recess (left trench 32) and the second recess (second trench 32) of the second patterned structure (50).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Zang ‘391’s the second patterned structure including a first recess and a second recess which are respectively disposed at two opposite sides of the stack in a second direction different from the first direction; and growing two source/drain portions respectively in the first recess and the second recess of the second patterned structure into Cheng ‘593 as modified by Su ‘199’s method. Cheng ‘593 discloses a method for a FET structure and Zang ‘391 also teaches a method for a FET structure. Therefore the ordinary artisan would recognize that the structure of the FET of Zang ‘391 could be used as the FET method in the method of Cheng ‘593 as modified by Su ‘199. The ordinary artisan would have been further motivated to modify Cheng ‘593 as modified by Su ‘199 in the manner set forth above, at least, because recessing a the trench in the stack creates a defined area for the growth of the epitaxial region would assure good contact of the epitaxial structure with the sidewalls of the stack.
As incorporated, the method of first and second recess disposed on opposite sides of the stack and then growing epitaxial source/drain portions in the recess taught by of Zang ‘391 would be to create the source/drain regions (504) of the second patterned structure (206) of Cheng ‘593 as modified by Su ‘199.
With respect to Claim 22 Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 discloses all limitations of the method as claimed in claim 21, but Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 fails to explicitly disclose wherein the first epitaxial portion is grown simultaneously with the two source/drain portions.
But Cheng ‘593 discloses wherein the first epitaxial portion (504’, Fig 7 of Cheng ‘593, Para [0043]) is grown simultaneously with the two source/drain portions (504, Fig 7 of Cheng ‘593, Para [0043]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Cheng 593’s further teaching of the first epitaxial portion is grown simultaneously with the two source/drain portions into Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391’s method. The ordinary artisan would have been motivated to modify Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 in the manner set forth above, at least, because this process of depositing epitaxial portions of the two devices at the same time would save production process time.
As incorporated, Cheng ‘593’s further teaching of the first epitaxial portion is grown simultaneously with the two source/drain portions would be used to grow the first epitaxial portion (222 of Su ‘199 as incorporated in Cheng ‘593) at the same time as the source/drain regions (504) Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391.
With respect to Claim 23 Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 discloses all limitations of the method as claimed in claim 21, and Su ‘199 further discloses wherein during growing the first epitaxial portion (222), the second recess (SR) of the first patterned structure (1000) is protected by a first patterned mask layer (Para [0023] of Su ‘199 discloses a photomask used over the area of the second epitaxial portion, which would be the second recess, when the first epitaxial region is formed).
With respect to Claim 24 Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 discloses all limitations of the method as claimed in claim 23, and Su ‘199 further discloses wherein during growing the second epitaxial portion (232), the first epitaxial portion (222) is protected by a second patterned mask layer (Para [0023] of Su ‘199 discloses a second photomask used over the area of the first epitaxial portion when the second epitaxial region is formed).
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With respect to Claim 25 Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 discloses all limitations of the method as claimed in claim 21, and Cheng ‘593 discloses of the first patterned structure (207), but Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 fails to explicitly disclose further comprising: prior to growing the first epitaxial portion and the second epitaxial portion, forming two isolation portions respectively in the first recess and the second recess, each of the two isolation portions including a dielectric material.
Nevertheless, in a related endeavor (Fig of Zang ‘391), Zang ‘391 teaches further comprising: prior to growing (Col 4, Lines 41-43 and Lines 56-60 disclose isolation portions formed prior to epitaxial portions) the first epitaxial portion (left 40, as shown on annotated Fig 8 of Zang ‘391, Col 6, Line 11) and the second epitaxial portion (second 40 as shown on annotated Fig 8 of Zang ‘391), forming two isolation portions (first and second 36, Fig 8 of Zang ‘391, Col 4, Lines 40-43) respectively in the first recess (left 32, Fig 3 of Zang ‘391, Col 4, lines 40-41) and the second recess (second 32, Fig 3 of Zang ‘391, Col 4, lines 40-41) of, each of the two isolation portions (left and second 32) including a dielectric material (silicon dioxide in 32 disclosed in Col 4, Lines 44-45 of Zang ‘391).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Zang ‘391’s teaching of prior to growing the first epitaxial portion and the second epitaxial portion, forming two isolation portions respectively in the first recess and the second recess, each of the two isolation portions including a dielectric material into Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359’s method. The ordinary artisan would have been motivated to modify Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359 in the manner set forth above, at least, because as taught by Zang ‘391 in Col 6, Lines 10-12, the isolation portions interrupt the continuity of the p-n junction which one of ordinary skill in the art would recognize providing isolation portions between the conductive areas will reduce parasitic capacitance.
As incorporated, the method of forming an isolation portion under each epitaxial portion before growing the epitaxial portions as taught by Zang ‘391 would be used in under the portions (222, 232, 224) of Cheng ‘593 as modified by Su ‘199 and further modified by Cheng ‘359.
With respect to Claim 27 Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 discloses all limitations of the method as claimed in claim 21, but Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 fails to explicitly disclose wherein a dopant concentration of the semiconductor regions is lower than a dopant concentration of the first epitaxial portion and a dopant concentration of the second epitaxial portion.
Nevertheless, in a related endeavor (Fig 1-9 of Cheng ‘359), Cheng ‘359 teaches wherein a dopant concentration (doping concentration of 2E18cm-3, Para [0032]) of the semiconductor regions (402, Fig 7 of Cheng ‘359, Para [0032]) is lower than a dopant concentration (doping concentration of 2E21cm-3, Para [0032]) of the first epitaxial portion (left S/D, Fig 7 of Cheng ‘359, Para [0032]) and a dopant concentration (doping concentration of 2E21cm-3, Para [0032]) of the second epitaxial portion (left S/D, Fig 7 of Cheng ‘359, Para [0032]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Cheng ‘359’s the first semiconductor regions having a dopant concentration which is lower than a dopant concentration of each of the first portion and a dopant concentration of the second portion into Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391’s method. Cheng ‘593 teaches a diode and transistor structure and that the semiconductor regions should be doped but is silent as to the specific concentrations. Cheng ‘359 also teaches a diode and transistor structure, that the semiconductor regions should be doped and provides concentrations for the doping of those semiconductor regions. Therefore one using Cheng ‘593 would be motivated to look for the diode/transistor doping concentrations at the current level of skill in the art. Cheng ‘359 provides, in an analogous structure to Cheng ‘593, doping concentrations for the semiconductor regions. So, the ordinary artisan would have been motivated to modify Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 in the manner set forth above, at least, because Cheng ‘359’s teaching of semiconductor doping concentrations would simplify the manufacturing process by using known concentrations to make the diode/transistor structure.
As incorporated, the method of creating doping concentrations of the semiconductor regions being lower than the first and second epitaxial portions taught by Cheng ‘359 would be used in the first semiconductor region (208), the first portion (222) and second portion (232) of Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391.
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With respect to Claim 28 Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 discloses all limitations of the method as claimed in claim 21, and Cheng ‘593 discloses further comprising: and,
forming two second ILD portions (first and second portion of 1207 as shown in annotated Fig 12 of Cheng ‘593, Para [0063]) respectively on the two source/drain portions (504).
Su ‘199 teaches further comprising: forming two first inter-layer dielectric (ILD) portions (first and second portion of 252 as shown in annotated Fig 5 of Su ‘199, Para [0025]) respectively on the first epitaxial portion (222 of Su ‘199 as incorporated in Cheng ‘593) and the second epitaxial portion (232 of Su ‘199 as incorporated in Cheng ‘593);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Su ‘199’s further teaching of forming two first inter-layer dielectric (ILD) portions respectively on the first epitaxial portion and the second epitaxial portion into Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391’s method. The ordinary artisan would have been motivated to modify Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 in the manner set forth above, at least, because the ILD layer will provide a level of dielectric protection from parasitic capacitance over the epitaxial regions.
As incorporated, the method of forming two first inter-layer dielectric (ILD) portions (252) respectively on the first epitaxial portion and the second epitaxial portion further taught by Su ‘199 would be used over the first epitaxial portion (222) and second epitaxial portion (232) of Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391.
With respect to Claim 29 Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 discloses all limitations of the method as claimed in claim 21, and Cheng ‘593 further discloses wherein
each of the and the second patterned structure (206) further includes a preformed gate structure (301, Fig 3, Para [0039]) which is disposed over the stack (203) and which extends lengthwise (disclosed in Fig 4) in a third direction different (Y direction as shown in Fig 4 of Cheng ‘593) from the first direction (X direction as shown in Fig 4 of Cheng ‘593) and the second direction (Z direction as shown in Fig 4 of Cheng ‘593), and
the preformed gate structure (301) includes a preformed gate dielectric layer and a preformed gate electrode layer disposed on the preformed gate dielectric layer (Para [0040 and 0041] discloses 301 includes a gate dielectric layer and gate electrode layer).
And Su ‘199 further teaches each of the first patterned structure (1000 of Su ‘199 as incorporated in Cheng ‘593) further includes a preformed gate structure (dummy gate disclosed in Fig 1 of Su ‘199, Para [0021]) which is disposed over (disclosed in Para [0021] of Su ‘199) the stack (206/208 of Su ‘199 as incorporated in Cheng ‘593) and which extends lengthwise (Fig 3 of Su ‘199 discloses gate) in a third direction different (Y direction as shown in Fig 3 of Su ‘199) from the first direction (X direction) and the second direction (Z direction), and
the preformed gate structure (dummy gate) includes a preformed gate dielectric layer and a preformed gate electrode layer disposed on the preformed gate dielectric layer (Para [0021] of Su ‘199 discloses dummy gate “include a dummy dielectric layer and a dummy gate electrode”).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Su ‘199’s further teaching of wherein each of the first patterned structure further includes a preformed gate structure which is disposed over the stack and which extends lengthwise in a third direction different from the first direction and the second direction, and the preformed gate structure includes a preformed gate dielectric layer and a preformed gate electrode layer disposed on the preformed gate dielectric layer into Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391’s method. The ordinary artisan would have been motivated to modify Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 in the manner set forth above, at least, because , as Su ‘199 teaches in Para [0021], this layer protects the stack structure during the formation of the epitaxial regions.
As incorporated, the gate structure (210) of Su ‘199 would be used on the stack (206/208) of Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391.
With respect to Claim 30 Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 discloses all limitations of the method as claimed in claim 29, and Cheng ‘593 discloses further comprising: performing a gate replacement process, in which
the preformed gate electrode layer (gate dielectric layer disclosed in Para [0040] discloses 301 includes a gate electrode layer) of the preformed gate structure (301) and parts of the dielectric regions (206 of Su ‘199 as incorporated above) in the second patterned structure (206) are replaced with an active gate structure (11023/1103, Fig 1 and Fig 11, Para [0059 and 0060] of Cheng ‘593 discloses replacing the dummy gate structure with the active gate structure).
Su ‘199 teaches further comprising: performing a gate replacement process (disclosed and Para [0021] of Su ‘199), in which the preformed gate dielectric layer (dielectric layer of dummy gate disclosed in Para [0021] of Su ‘199) and the preformed gate electrode layer (dummy gate electrode disclosed in Para [0021] of Su ‘199) of the preformed gate structure (dummy gate disclosed in Para [0021] of Su ‘199) in the first patterned structure (1000 of Su ‘199 as incorporated in Cheng ‘593) are replaced with a dummy gate structure (Fig 1 and Para [0021] disclose that dummy gate structure is replaced with a second dummy gate structure),
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Su ‘199’s further teaching of the preformed gate dielectric layer and the preformed gate electrode layer of the preformed gate structure in the first patterned structure are replaced with a dummy gate structure into Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391’s method. The ordinary artisan would have been motivated to modify Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 in the manner set forth above, at least, because , as Su ‘199 teaches in Para [0021], this second gate structure helps to define conductivity regions.
As incorporated, the replacement of the preformed dummy gate structure (210) with a second dummy gate (disclosed in Para [0021] of Su ‘199) would be used on the stack (206/208) of Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391.
With respect to Claim 31 Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 discloses all limitations of the method as claimed in claim 30, wherein after the gate replacement process (disclosed in Fig 1 and Para [0021] of Su ‘199), the stack (206/208 of Su ‘199 as incorporated in Cheng ‘593) of the first patterned structure (1000 as incorporated in Cheng ‘593) remains unchanged (Fig 1 and Figs 4-7 of Su ‘199 disclose that the stack 206/208 does not change after the gate replacement process, there are no further disclosed process or changes to the stack after the gate replacement process).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng ‘593 in view of Su ‘199 in view of Zang ‘391 in further view of Tschumakow et al. (US 2019/0080966 A1, hereinafter Tschumakow ‘966), in view of the following arguments.
With respect to Claim 26 Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 discloses all limitations of the method as claimed in claim 25, but Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 fails to explicitly disclose further comprising:
prior to forming the two isolation portions, forming a patterned photoresist to cover the second patterned structure, after forming the two isolation portions, removing the patterned photoresist
Nevertheless, in a related endeavor (Fig 10-11 of Tschumakow ‘966), Tschumakow ‘966 teaches prior to forming the two isolation portions, forming a patterned photoresist (150, Fig 10 of Tschumakow ‘966, Para [0044] to cover the second patterned structure (162, Fig 10 of Tschumakow ‘966, Para [0043](Tschumakow ‘966 teaches in Fig 10 and Para [0040-0044] discloses the use of a photomask to protect the CMOS structure while processing the diode structure (Para [0019] discloses non-CMOs device as diode)), after forming the two isolation portions, removing the patterned photoresist (150)(Fig 11 discloses 150 removed in subsequent process step).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Tschumakow ‘966’s teaching of forming a patterned photoresist to cover the second patterned structure after forming the two isolation portions, removing the patterned photoresist into Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391’s method. Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 teaches a method for producing a transistor structure and a diode on the same substrate. Tschumakow ‘966 also teaches a method for producing a transistor structure and a diode on the same substrate and adds means to protect one structure while processing the second structure. The ordinary artisan would have been motivated then to modify Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391 in the manner set forth above, at least, because as Tschumakow ‘966 teaches in Para [0040-0044] the use of a mask over one of the devices can be used to protect that device from damage during the manufacturing process step of the second device.
As incorporated, the teaching of a photoresist (150) over the device not being process during the processing of the second device, then removing that photoresist after processing of the second device is completed of Tschumakow ‘966 would be incorporated in the method of Cheng ‘593 as modified by Su ‘199 and further modified by Zang ‘391.
Thus, Cheng ‘593 as modified by Su ‘199 modified by Zang ‘391 and further modified by Tschumakow ‘966 discloses
prior to forming the two isolation portions (first and second 36, Fig 8 of Zang ‘391, Col 4, Lines 40-43), forming a patterned photoresist (150 of Tschumakow ‘966 as incorporated in Cheng ‘593 as modified by Su ‘199 modified by Zang ‘391, described above) to cover the second patterned structure (206), such that the (left 32, Fig 3 of Zang ‘391, Col 4, lines 40-41) and the second recess (second 32, Fig 3 of Zang ‘391, Col 4, lines 40-41 of the first patterned structure (1000) are exposed from the patterned photoresist (150)(as described above, the mask 150 is incorporated to cover 206 while 1000 is being processed); and0
after forming the two isolation portions (first and second 36), removing the patterned photoresist (150)(as described above, the mask 150 is incorporated to cover 206 while 1000 is being processed and removed after processing of 1000 is complete).
Claims 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Su ‘199 in view of Zang ‘391, in view of the following arguments.
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With respect to Claim 33 Su ‘199 discloses all limitations of the method as claimed in claim 32,
but Su ‘199 fails to explicitly discloses prior to growing the two first epitaxial portions and the second epitaxial portion, further comprising:
depositing a dielectric material layer in the left recess, the middle recess and the right recess; and
etching back the dielectric material layer so as to form three isolation portions respectively at bottoms of the left recess, the middle recess and the right recess.
Nevertheless, in a related endeavor (Fig 1-8 of Zang ‘391), Zang ‘391 teaches prior to growing the two first epitaxial portions (left 40 and a further region 40 to the right of the third stack, as shown on annotated Fig 8 of Zang ‘391, Col 6, Line 11) (Fig 8 shows two regions but Col 7, Lines 13-25 disclose the method is for a wafer of chips, therefore additional epitaxial portions are present) and the second epitaxial portion (second 40 as shown on annotated Fig 8 of Zang ‘391), further comprising: depositing a dielectric material layer (silicon dioxide 36, Fig 8 of Zang ‘391, Col 4, Lines 40-43) in the left recess (left trench 32, Fig 3 of Zang ‘391, Col 4, Lines 17-18), the middle recess (middle trench 32, Fig 3 of Zang ‘391, Col 4, Lines 17-18) and the right recess (right trench 32 as show in annotated Fig 3 of Zang ‘391) (Fig 8 shows two regions but Col 7, Lines 13-25 disclose the method is for a wafer of chips, therefore additional recess portions are present); and etching back (etch process disclosed in Col 4, Lines 43-46) the dielectric material layer ) so as to form three isolation portions (left 40/middle 40/right 40, Fig 4 of Zang ‘391, Col 4, Lines 56-61) (Fig 8 shows two regions but Col 7, Lines 13-25 disclose the method is for a wafer of chips, therefore additional isolation portions are present) respectively at bottoms of the left recess (left trench 32), the middle recess (middle trench 32) and the right recess (right trench 32).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Zang ‘391’s teaching prior to growing the two first epitaxial portions and the second epitaxial portion, further comprising: depositing a dielectric material layer in the left recess, the middle recess and the right recess; and etching back the dielectric material layer so as to form three isolation portions respectively at bottoms of the left recess, the middle recess and the right recess into Su ‘199’s method. The ordinary artisan would have been motivated to modify Su ‘199 in the manner set forth above, at least, because as taught in Zang ‘391, Col 6, Lines 10-12, the isolation regions interrupt the continuity of the p-n junction which one of ordinary skill in the art would recognize providing isolation regions between the conductive areas to reduce parasitic capacitance.
As incorporated, the method of forming the isolation portions (left, middle and right 40) as taught by Zang ‘391 would be used in under the epitaxial portions (222, 232, 224) of Su ‘199.
With respect to Claim 34 Su ‘199 as modified by Zang ‘391 discloses all limitations of the method as claimed in claim 33, and Su ‘199 as modified by Zang ‘391 further discloses wherein an upper surface (top surface of left, middle and right 40) of each of the three isolation portions (left, middle and right 40 as incorporated in Su ‘199) is located at a level that is lower than a level of a lower surface of a bottommost one of the semiconductor regions (208) in each of the first stack (ST1) and the second stack (ST2)(as incorporated, described above, the recess areas 40 would be below the epitaxial portions (222, 232, 224 of Su ‘199). Fig 4 of Su ‘199 then discloses the top of these incorporated regions would be lower than a lower surface of semiconductor region 208).
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Allowable subject matter has been indicated because the closest prior art references of record, Su et al. (US 2022/0113199 A1), Cheng et al. (US 2018/0261593 A1) or Cheng et al. (US 2018/0102359 A1) either alone or in combination, fails to teach or fairly suggest the feature, “replacing the preformed semiconductor regions with a plurality of first dielectric layers, respectively, recessing the first dielectric layers such that the first dielectric layers are each recessed to form two lateral grooves and such that each of the recessed first dielectric layers serves as the main part of a corresponding one of the first dielectric regions, and forming the two lateral parts of each of the first dielectric regions respectively in the two lateral grooves of a corresponding one of the recessed first dielectric layers”.
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899