DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang(USPGPUB DOCUMENT: 2020/0020734, hereinafter Wang) in view of Lin (USPATENT: 11456182, hereinafter Lin) and Cheng (USPGPUB DOCUMENT: 2019/0259855, hereinafter Cheng).
Re claim 1 Wang discloses a method of semiconductor device fabrication, the method comprising: forming a plurality of semiconductor structures[0047] extending above a substrate(102); forming a plurality of metal gates(126/128) over the plurality of semiconductor structures[0047]; forming multi-layer interconnect (MLI)layers(152/130) over the plurality of metal gates(126/128); performing a first etching process[0050] to form a first opening(170) extending through the MLI layers to expose(see Fig 9B) a first metal gate structure of the plurality of metal gates(126/128) on a first semiconductor structure of the plurality of semiconductor structures[0047]; depositing a spacer liner layer(172) on sidewalls of the first opening(170);
Wang does not disclose performing a first etching process to expose a top surface of a gate electrode layer, wherein the first etching process further removes isolation features between adjacent semiconductor structures of the plurality of semiconductor structures; performing a second etching process to remove the first metal gate structure; and performing a third etching removing the first semiconductor structure and extending the first opening(170) into the substrate(102) to form an extended opening;
Lin disclose performing a second etching process to remove(R1) the first metal gate structure (158); and performing a third etching removing the first semiconductor structure and extending the first opening(190) into the substrate(102) to form an extended opening (R3).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of Wang in order to increasing production efficiency and lowering associated costs [col1, lines 5-15, Lin].
Wang does not disclose performing a first etching process to expose a top surface of a gate electrode layer, wherein the first etching process further removes isolation features between adjacent semiconductor structures of the plurality of semiconductor structures;
Cheng disclose performing a first etching process to expose a top surface of a gate electrode layer(124b/116b), wherein the first etching process further removes isolation features (130/128) between adjacent semiconductor structures of the plurality of semiconductor structures;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cheng to the teachings of Wang in order to minimize increased resistance that become unsuitable in some instances [0002, Cheng].
Re claim 2 Wang, Lin and Cheng disclose the method of semiconductor device fabrication of claim 1, further comprising: filling the extended opening with conductive material(226 of Lin).
Re claim 3 Wang, Lin and Cheng disclose the method of semiconductor device fabrication of claim 2, further comprising: thinning the substrate(102) to expose a bottom surface of the filled extended opening (R3 of Lin) to form a through silicon via (TSV).
Re claim 4 Wang, Lin and Cheng disclose the method of semiconductor device fabrication of claim 1, wherein the forming the plurality of semiconductor structures[0047] includes forming the first semiconductor structure as a crown structure having a plurality of fins (130 of Lin) extending from the crown structure.
Re claim 5 Wang, Lin and Cheng disclose the method of semiconductor device fabrication of claim 1, wherein forming the multi-layer interconnect layers over the plurality of metal gates(126/128) includes forming a contact structure to a second metal gate structure of the plurality of metal gates(126/128) and forming a first metallization layer over the second metal gate structure and connected to the contact structure.
Re claim 6 Wang, Lin and Cheng disclose the method of semiconductor device fabrication of claim 1, wherein depositing the spacer liner layer(172) on sidewalls of the first opening(170) includes: conformally depositing an oxide layer; and etching the oxide[0031] layer to expose the first metal gate structure.
Re claim 7 Wang, Lin and Cheng disclose the method of semiconductor device fabrication of claim 1, wherein performing the second etching process(R1) to remove the first metal gate structure etches a portion of the first semiconductor structure.
Re claim 8 Wang, Lin and Cheng disclose the method of semiconductor device fabrication of claim 7, wherein the portion of the first semiconductor structure is fins (130 of Lin) extending above a crown structure.
Re claim 9 Wang, Lin and Cheng disclose the method of semiconductor device fabrication of claim 1, wherein the extended opening (R3 of Lin) has a non-planar bottom surface, the non-planar bottom surface having a plurality of recesses(recess from R1).
Re claim 10 Wang, Lin and Cheng disclose the method of semiconductor device fabrication of claim 9, further comprising: depositing a dielectric barrier layer in the extended opening (R3 of Lin) filling the plurality of recesses(recess from R1).
Re claim 11 Wang discloses in Fig 2 a method of forming a semiconductor device, comprising: forming layer including a plurality of transistor features[0051] on a substrate(102); forming layer including a plurality of contact features(146) over the layer; forming layer including a plurality of metal lines and vias(152) over the layer; etching an opening(170) through the layer, wherein the opening has a bottom surface defined by the substrate(102); depositing a spacer liner layer(172) on sidewalls of the opening;
Wang does not disclose forming front-end-of-the-line (FEOL) layer; forming middle-end-of-the-line (MEOL) layer; forming back-end-of-the-line (BEOL) layer; wherein the opening is defined by a first masking element,
and wherein the etching the opening exposes a top surface of a gate electrode of a dummy transistor feature(126/128)[0050] and a source/drain feature of the dummy transistor feature, the source/drain feature adjacent to the gate electrode;
providing a second masking element over the BEOL layer and etching the substrate(102) in a region defined by the second masking element to extend the opening into the substrate(102); and filling the extended opening with conductive material; ,
Lin disclose forming front-end-of-the-line (FEOL) layer[col2, lines 45-55]; forming middle-end-of-the-line (MEOL) layer[col2, lines 45-55]; forming back-end-of-the-line (BEOL) layer[col2, lines 45-55]; wherein the opening is defined by a first masking element[col2, lines 45-55], providing a second masking element(156/158/810) over the BEOL layer and etching the substrate in a region defined by the second masking element to extend the opening into the substrate(110); and filling the extended opening (R3) with conductive material(226 of Lin).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of Wang in order to increasing production efficiency and lowering associated costs [col1, lines 5-15, Lin].
Wang and Lin does not disclose wherein the etching the opening exposes a top surface of a gate electrode of a dummy transistor feature(126/128)[0050] and a source/drain feature of the dummy transistor feature, the source/drain feature adjacent to the gate electrode;
Cheng disclose wherein the etching the opening exposes a top surface of a gate electrode(124b/116b of Cheng) and a source/drain feature(124a/118/108 of Cheng) , the source/drain feature adjacent to the gate electrode;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cheng to the teachings of Wang in order to minimize increased resistance that become unsuitable in some instances [0002, Cheng]. In doing so, wherein the etching the opening exposes a top surface of a gate electrode(124b/116b of Cheng) of a dummy transistor feature(126/128)[0050 of Wang] and a source/drain feature(124a/118/108 of Cheng) of the dummy transistor feature,
Re claim 12 Wang, Lin and Cheng disclose the method of claim 11, further comprising: removing the first masking element(158/158’) before depositing the spacer liner layer(172).
Re claim 13 Wang, Lin and Cheng disclose the method of claim 11, wherein the spacer liner layer(172) is deposited on the dummy transistor feature(150 of Lin).
Re claim 14 Wang, Lin and Cheng disclose the method of claim 13, further comprising: after forming the opening and prior to providing the second masking element(158/158’) and etching the substrate(102), performing another etching process to remove the dummy transistor feature(150 of Lin).
Re claim 15 Wang, Lin and Cheng disclose the method of claim 14, wherein the dummy transistor feature(150 of Lin) is a gate structure disposed on a fin(130 of Lin).
Re claim 16 Wang, Lin and Cheng disclose the method of claim 11, further comprising: thinning the substrate(102) to expose a bottom surface of the filled extended opening (R3 of Lin).
Claim(s) 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang(USPGPUB DOCUMENT: 2020/0020734, hereinafter Wang) in view of Lin (USPATENT: 11456182, hereinafter Lin) and Kang (USPGPUB DOCUMENT: 2024/0087957, hereinafter Kang).
Re claim 21 Wang discloses a method of fabricating a semiconductor structure, comprising: providing a plurality of semiconductor structures[0047] extending above a substrate(102), wherein the plurality of semiconductor structures[0047] includes a first semiconductor structure having a first metal gate(126/128) disposed thereover and a second semiconductor structure having a second metal gate(126/128) disposed thereover; disposing a multi-layer interconnect (MLI) (152/130) over the plurality of semiconductor structures[0047]; connecting the MLI to the first metal gate wherein a spacer liner layer(172) is formed on a sidewall of the second semiconductor structure and is disposed between the sidewall and a first sidewall of the through substrate via(142).
Wang does not disclose and insulating the MLI from the second metal gate; and forming a through substrate via(142) extending vertically through the substrate(102) and the MLI, and forming a through substrate via extending vertically through an entirety of the substrate and the MLI,
Lin disclose insulating the MLI (250) from the second metal gate(220); and forming a through substrate via(200/190) extending vertically through the substrate(110) and the MLI (250),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of Wang in order to increasing production efficiency and lowering associated costs [col1, lines 5-15, Lin].
Wang does not disclose forming a through substrate via extending vertically through an entirety of the substrate and the MLI,
Kang disclose in Fig 24/26 forming a through substrate via(2512/2514) extending vertically through an entirety of the substrate(substrate) and the MLI (within ILD),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kang to the teachings of Wang in order to have robust alignment in integrated circuit design [0001, Kang].
Re claim 22 Wang, Lin and Kang disclose the method of claim 21, further comprising: depositing the spacer liner layer(172) onto the second metal gate.
Re claim 23 Wang, Lin and Kang disclose the method of claim 21, further comprising:forming a source/drain feature[0051] adjacent the second metal gate; and depositing the spacer liner layer(172) onto the source/drain feature.
Re claim 24 Wang, Lin and Kang disclose the method of claim 21, wherein the forming the through substrate via(142) forming the through substrate via(142) extending through the second metal gate.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16 & 21-24 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Prosecution Insights