Prosecution Insights
Last updated: April 19, 2026
Application No. 18/323,688

LAYOUT OF SCRIBE LINE FEATURES

Non-Final OA §102
Filed
May 25, 2023
Examiner
LEE, DA WEI
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
3y 6m
To Grant
96%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
15 granted / 20 resolved
+7.0% vs TC avg
Strong +21% interview lift
Without
With
+20.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
53 currently pending
Career history
73
Total Applications
across all art units

Statute-Specific Performance

§103
54.2%
+14.2% vs TC avg
§102
33.7%
-6.3% vs TC avg
§112
10.8%
-29.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 20 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election of claims 4 – 12 without traverse, in the reply filed on 1/6/2026 is acknowledged. Applicant newly added claims 21 – 31. Newly submitted claims 21 – 31 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: I. Claim 4 – 12, drawn to a method, classified in H10W 46/503. II. Claim 21 – 31, drawn to a method, classified in H10W 72/01951. Inventions I and II are directed to related method. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions have a materially different design. Inventions I requires a scribe line region; identifying a center portion of the scribe line region surrounding the device region; while invention II requires a singulation region; identifying a center portion of the singulation region adjacent the device region; wherein the dummy pattern comprises a plurality of dummy pad patterns; receiving a design layout that includes a device region in a non-device region; wherein each of the plurality of rectangular areas has a length along a lengthwise direction and a width along a widthwise direction, wherein the plurality of rectangular areas have a same width. Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21 – 31 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03. To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention. Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 4 – 12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ha (Pub. No. 20220082926 A1), hereinafter Ha. PNG media_image1.png 1270 1214 media_image1.png Greyscale Regarding Independent Claim 4 (Original), Ha teaches a method, comprising: receiving a design layout ( Ha, FIG. 2, 100; [0039], EUV photomask 100; [0045], EUV photomask 100 may include a main area MR on a mask substrate 101 and a scribe lane area SL surrounding the main area MR ) that includes a device region ( Ha, FIG. 2, FIG. 3, MR; [0045], main area MR ) disposed in a scribe line region ( Ha, FIG. 2, FIG. 3, SL; [0045], scribe lane area SL ); identifying a center portion ( Ha, FIG. 2, 122, 123, 126, 127; [0010], inner sub-lanes; [0052], second sub-lane 122; third sub-lane 123; [0053], sixth sub-lane 126; seventh sub-lane 127 ) of the scribe line region ( Ha, FIG. 2, FIG. 3, SL ) surrounding the device region ( Ha, FIG. 2, FIG. 3, MR ) and an edge portion ( Ha, FIG. 2, 121, 124, 125, 128; [0010], outer sub-lanes; [0052], first sub-lane 121; fourth sub-lane 124; [0053], fifth sub-lane 125; eighth sub-lane 128 ) surrounding the center portion ( Ha, FIG. 2, 122, 123, 126, 127 ); dividing the edge portion ( Ha, FIG. 2, 121, 124, 125, 128 ) into a plurality of rectangular areas ( Ha, [0010], outer sub-lanes; [0052], first sub-lane 121; fourth sub-lane 124; [0053], fifth sub-lane 125; eighth sub-lane 128 ); super-positioning a dummy pattern ( Ha, [0041], a pattern shape of the EUV photomask 100 ) on each of the plurality of rectangular areas ( Ha, FIG. 2, 121, 124, 125, 128 ) to obtain edge dummy patterns ( Ha, FIG. 2, LD1, LD4, LD5, LD8; [0055], first dummy pattern LD1; [0056], fourth dummy pattern LD4; fifth dummy pattern LD5; eighth dummy pattern LD8 ); super-positioning the dummy pattern ( Ha, [0041], a pattern shape of the EUV photomask 100 ) on the center portion ( Ha, FIG. 2, 122, 123, 126, 127 ) to obtain center dummy patterns ( Ha, FIG. 2, LD2, LD3, LD6, LD7; [0055], second dummy pattern LD2; [0056], third dummy pattern LD3; sixth dummy pattern LD6; seventh dummy pattern LD7); carving out a portion of the dummy pattern ( Ha, [0041], a pattern shape of the EUV photomask 100 ) corresponding to the device region ( Ha, FIG. 2, FIG. 3, MR ) from the center dummy patterns ( Ha, FIG. 2, LD2, LD3, LD6, LD7 ) to obtain net center dummy patterns ( Ha, FIG. 2, LD2, LD3, LD6, LD7, without MR ); generating a scribe line dummy pattern ( Ha, FIG. 2, LD1 to LD8, without MR ) based on the edge dummy patterns ( Ha, FIG. 2, LD1, LD4, LD5, LD8 ) and the net center dummy patterns ( Ha, FIG. 2, LD2, LD3, LD6, LD7, without MR ); and fabricating a first photomask ( Ha, FIG. 3, [0046], The EUV photomask 100 may include reflective multilayer films 102, 103, and 104 formed on the mask substrate 101 and an absorption pattern 105 formed on the reflective multilayer films 102, 103, and 104; FIG. 4, S1; [0061], Shot 1 (S1) and the subsequent shot 2 (S2) may be adjusted so that scribe lane areas SL overlap each other ) comprising the scribe line dummy pattern ( Ha, FIG. 2, LD1 to LD8, without MR ). Regarding Claim 5 (Original), Ha teaches the method of claim 4, on which this claim is dependent, Ha further teaches: comprising: fabricating a second photomask ( Ha, FIG. 4, S2; [0061], Shot 1 (S1) and the subsequent shot 2 (S2) may be adjusted so that scribe lane areas SL overlap each other ) comprising a mirror image ( Ha, [0057], In some example embodiments, the first dummy pattern LD1 and the second dummy pattern LD2 may be mirror-symmetrical to the fourth dummy pattern LD4 and the third dummy pattern LD3 with respect to the main area MR, respectively; FIG. 4, S1, S2; [0061], Shot 1 (S1) and the subsequent shot 2 (S2) may be adjusted so that scribe lane areas SL overlap each other ) of the scribe line dummy pattern ( Ha, FIG. 2, LD1 to LD8, without MR ). Regarding Claim 6 (Original), Ha teaches the method of claim 5, on which this claim is dependent, Ha further teaches: further comprising: receiving a wafer ( Ha, [0078], semiconductor substrate 200 ) comprising a photoresist layer ( Ha, FIG. 6C, 220; [0078], photoresist material layer 220 ); and stepwise transferring ( Ha, FIG. 4, S1, S2; FIG. 5, S1, S2, S3, S4; [0015], FIGS. 4 and 5 are conceptual diagrams illustrating a method of exposing a mask pattern on a semiconductor substrate in a step and repeat method using an EUV photomask ) a first image ( Ha, FIG. 4, 120B, 123, 124; [0051], second lane 120B; [0052], third sub-lane 123, a fourth sub-lane 124 ) of the first photomask ( Ha, FIG. 4, S1 ) and a second image ( Ha, FIG. 4, 120A, 121, 122; [0051], first lane 120A; [0052], first sub-lane 121, a second sub-lane 122 ) of the second photomask ( Ha, FIG. 4, S2 ) onto the photoresist layer ( Ha, FIG. 6C, 220 ). Regarding Claim 7 (Original), Ha teaches the method of claim 6, on which this claim is dependent, Ha further teaches: wherein the stepwise transferring ( Ha, FIG. 4, S1, S2; FIG. 5, S1, S2, S3, S4; [0015], step and repeat ) forms an array ( Ha, FIG. 5, DE12; [0061], double overlap area DE12 ) comprising a plurality of the first images ( Ha, FIG. 4, 120B, 123, 124 ) and a plurality of the second images ( Ha, FIG. 4, 120A, 121, 122 ). Regarding Claim 8 (Original), Ha teaches the method of claim 6, on which this claim is dependent, Ha further teaches: wherein the stepwise transferring ( Ha, FIG. 4, S1, S2; FIG. 5, S1, S2, S3, S4; [0015], step and repeat ) is performed such that the first image ( Ha, FIG. 4, 120B, 123, 124 ) overlaps with the second image ( Ha, FIG. 4, 120A, 121, 122 ) at a double exposure region ( Ha, FIG. 5, DE12; [0061], double overlap area DE12 ). Regarding Claim 9 (Original), Ha teaches the method of claim 8, on which this claim is dependent, Ha further teaches: wherein the first image ( Ha, FIG. 4, 120B, 123, 124 ) comprises first dummy features ( Ha, FIG. 6A, the amount of light H of curve C1 ) and the second image ( Ha, FIG. 4, 120A, 121, 122 ) comprises second dummy features ( Ha, FIG. 6B, the amount of light H of curve C2 ), wherein the first dummy features and the second dummy features in the double exposure region completely overlap ( Ha, [0076], Referring to FIG. 6C, the amount of light H of a curve C to which two curves C1 and C2 are added is irradiated to the scribe lane area SL (for example, in a double overlap area), which indicates that EUV light having an amount exceeding the threshold amount of light Th is irradiated to the entire scribe lane area SL ). Regarding Claim 10 (Original), Ha teaches the method of claim 8, on which this claim is dependent, Ha further teaches: wherein the double exposure region ( Ha, FIG. 5, DE12; [0061], double overlap area DE12 ) comprises a rectangular shape ( Ha, FIG. 5, DE12 is rectangular shape ). Regarding Claim 11 (Original), Ha teaches the method of claim 4, on which this claim is dependent, Ha further teaches: wherein the edge portion ( Ha, FIG. 12, 110A1, 110A2, 110A3 ) surrounds the center portion ( Ha, FIG. 12, 110A4 ) on three sides, wherein the plurality of rectangular areas comprises three rectangular areas ( Ha, FIG. 12, 110A1, 110A2, 110A3 ). Regarding Claim 12 (Original), Ha teaches the method of claim 4, on which this claim is dependent, Ha further teaches: wherein the edge portion ( Ha, FIG. 2, 121, 124, 125, 128 ) surrounds the center portion ( Ha, FIG. 2, 122, 123, 126, 127 ) on four sides, wherein the plurality of rectangular areas comprises four rectangular areas ( Ha, FIG. 2, 121, 124, 125, 128 ). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DA-WEI LEE/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

May 25, 2023
Application Filed
Feb 21, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604751
SEMICONDUCTOR PACKAGE
2y 5m to grant Granted Apr 14, 2026
Patent 12563853
BACKSIDE ILLUMINATED CMOS IMAGE SENSOR AND METHOD OF MAKING THE SAME
2y 5m to grant Granted Feb 24, 2026
Patent 12557375
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
2y 5m to grant Granted Feb 17, 2026
Patent 12550513
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Feb 10, 2026
Patent 12543309
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE
2y 5m to grant Granted Feb 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
96%
With Interview (+20.8%)
3y 6m
Median Time to Grant
Low
PTA Risk
Based on 20 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month