DETAILED ACTION
This Office Action is in response to Restriction/Elected, filed on 04/23/2026, on the application filed on 05/25/2023. Claims 16-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-8 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected (Species 1). Claims 9-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Species 2. There being no allowable generic or linking claims. Election was made without traverse in the reply filed on 04/23/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16, 18, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (CN114698255A and Chen hereinafter, cited in the 03/04/2024 IDS and 12/05/2023 Taiwanese Office Action).
Regarding claim 16, Chen discloses a circuit board (Fig. 8 and ¶[n0041 & n0108] from Espacenet Translation shows and indicates a circuit board of Fig. 8 {flowchart of the fabrication process of the third type of printed circuit board}), comprising: a substrate, comprising an opening (items 1, 11 of Fig. 8 and claim 1 & ¶[n0046_0050_n0055-n0056_n0095_n0105 & n0114] from Espacenet Translation shows and indicates circuit board of Fig. 8 is comprised of substrate 1 {core board 1} that is comprised of an opening 11 {through hole 11}); a ceramic substrate, disposed in the opening, and comprising a plurality of through holes (items 1, 11, 7, 3 of Fig. 8 & Fig. 5 and claims 1-2_8-9 & ¶[n0046-n0047_0050_n0055-n0056_n0095_n0105 & n0114] from Espacenet Translation shows and indicates ceramic substrate 4 {ceramic block 4} that is disposed in opening 11; where ceramic substrate 4 is comprised of the plurality of through holes 7-holes {holes that are configured to form the metal bonding layers 7 to eventually construct the adhesive layer 3 channel}); an adhesive layer, disposed between the substrate and the ceramic substrate (item 3 of Fig. 8 and claim 1 & ¶[n0046-n0047] from Espacenet Translation shows and indicates adhesive layer 3 disposed between substrate 1 and ceramic substrate 4); and a circuit layer, disposed on the substrate and the ceramic substrate, wherein the substrate, the ceramic substrate, and the adhesive layer are substantially coplanar with each other (item 2 of Fig. 8 and claims 1_5 & ¶[ n0050_n0055_n0082-n0083 & n0116] from Espacenet Translation shows and indicates circuit layer 2 that is disposed on substrate 1 and ceramic substrate 4; where substrate 1, ceramic substrate 4, and adhesive layer 3 are substantially coplanar with each other).
Regarding claim 18, Chen discloses a circuit board, further comprising: a bonding layer, disposed between the circuit layer and the substrate and disposed between the circuit layer and the ceramic substrate (item 5 of Fig. 8 and claims 5-6 & ¶[n0046_n0050_n0055-n0056_n0082-n0083_n0095_n0105_n0114 & n0116] from Espacenet Translation shows and indicates circuit board of Fig. 8 is further comprised of bonding layer 5 {chemical plating process bonding of metal seed layer 5} that is disposed between circuit layer 2 and substrate 1 and disposed between circuit layer 2 and ceramic substrate 4).
Regarding claim 19, Chen discloses a circuit board, wherein the bonding layer is coplanarly extended across the substrate, the ceramic substrate, and the adhesive layer (Fig. 8 and claims 5-6 & ¶[n0046-n0047_n0050_n0055-n0056_n0082-n0083_n0095_n0105_n0114 & n0116] from Espacenet Translation shows and indicates where bonding layer 5 is coplanarly extended across substrate 1, ceramic substrate 4, and adhesive layer 3).
Regarding claim 20, Chen discloses a circuit board, wherein the bonding layer is extended to the through holes (Figs. 5_8 and claims 5-6_8-9 & ¶[n0046-n0047_n0050_n0055-n0056_n0069-n0073_n0082-n0083_n0095_n0105_n0114 & n0116] from Espacenet Translation shows where bonding layer 5 is extended to through holes 7-holes).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, as detailed in the rejection of claim 16 above, in view of Lin et al. (US20230187598A1 and Lin hereinafter).
Regarding claim 17, Chen discloses a circuit board, wherein the substrate comprises the circuit layer (Fig. 8 and claims 1_5 & ¶[n0046_n0050_n0055-n0056_n0082-n0083_n0095_n0105_n0114 & n0116] from Espacenet Translation shows and indicates substrate 1 comprises circuit layer 2).
However, Chen does not disclose wherein the substrate further comprises a redistribution layer connected to the circuit layer.
Lin disclose wherein the substrate further comprises a redistribution layer connected to the circuit layer (items 120, 130, 140, 1314 of Fig. 3 and ¶[0026-0027 & 0029] shows and indicates where substrate 120_130_140 {substrate formed of the following structures: protective layer 120; substrate forming the redistribution layer 130; and the heat dissipation substrate 140} is further comprised of redistribution layer 130 connected to circuit layer 1314).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the substrate further comprises a redistribution layer connected to the circuit layer into the structure of Chen. One would have been motivated in the circuit board of Chen and have the substrate be further comprised of a redistribution layer that is connected to the circuit layer, in order to design a circuit board and have the redistribution layer electrically connect the heat dissipation component to the semiconductor chip/component and still have the same redistribution layer be the structure to isolate the heat dissipation component from the semiconductor chip/component so as not to make direct contact between each other, as indicated by Lin in ¶[0006], in the circuit board of Chen.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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